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1 | #include "../sh2.h" |
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2 | |
3 | // MAME types |
4 | typedef signed char INT8; |
5 | typedef signed short INT16; |
6 | typedef signed int INT32; |
7 | typedef unsigned int UINT32; |
8 | typedef unsigned short UINT16; |
9 | typedef unsigned char UINT8; |
10 | |
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11 | #define RB(a) p32x_sh2_read8(a,sh2) |
12 | #define RW(a) p32x_sh2_read16(a,sh2) |
13 | #define RL(a) p32x_sh2_read32(a,sh2) |
14 | #define WB(a,d) p32x_sh2_write8(a,d,sh2) |
15 | #define WW(a,d) p32x_sh2_write16(a,d,sh2) |
16 | #define WL(a,d) p32x_sh2_write32(a,d,sh2) |
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17 | |
18 | // some stuff from sh2comn.h |
19 | #define T 0x00000001 |
20 | #define S 0x00000002 |
21 | #define I 0x000000f0 |
22 | #define Q 0x00000100 |
23 | #define M 0x00000200 |
24 | |
25 | #define AM 0xc7ffffff |
26 | |
27 | #define FLAGS (M|Q|I|S|T) |
28 | |
29 | #define Rn ((opcode>>8)&15) |
30 | #define Rm ((opcode>>4)&15) |
31 | |
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32 | #define sh2_icount sh2->icount |
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33 | |
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34 | #ifdef SH2_STATS |
35 | static SH2 sh2_stats; |
36 | static unsigned int op_refs[0x10000]; |
37 | # define LRN 1 |
38 | # define LRM 2 |
39 | # define LRNM (LRN|LRM) |
40 | # define rlog(rnm) { \ |
41 | int op = opcode; \ |
42 | if ((rnm) & LRN) { \ |
43 | op &= ~0x0f00; \ |
44 | sh2_stats.r[Rn]++; \ |
45 | } \ |
46 | if ((rnm) & LRM) { \ |
47 | op &= ~0x00f0; \ |
48 | sh2_stats.r[Rm]++; \ |
49 | } \ |
50 | op_refs[op]++; \ |
51 | } |
52 | # define rlog1(x) sh2_stats.r[x]++ |
53 | # define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++ |
54 | #else |
55 | # define rlog(x) |
56 | # define rlog1(...) |
57 | # define rlog2(...) |
58 | #endif |
59 | |
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60 | #include "sh2.c" |
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61 | |
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62 | #ifndef DRC_SH2 |
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63 | |
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64 | void sh2_execute(SH2 *sh2_, int cycles) |
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65 | { |
66 | sh2 = sh2_; |
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67 | sh2->cycles_aim += cycles; |
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68 | sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done; |
69 | |
70 | if (sh2->icount <= 0) |
71 | return; |
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72 | |
73 | do |
74 | { |
75 | UINT32 opcode; |
76 | |
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77 | if (sh2->delay) |
78 | { |
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79 | sh2->ppc = sh2->delay; |
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80 | opcode = RW(sh2->delay); |
81 | sh2->pc -= 2; |
82 | } |
83 | else |
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84 | { |
85 | sh2->ppc = sh2->pc; |
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86 | opcode = RW(sh2->pc); |
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87 | } |
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88 | |
89 | sh2->delay = 0; |
90 | sh2->pc += 2; |
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91 | |
92 | switch (opcode & ( 15 << 12)) |
93 | { |
94 | case 0<<12: op0000(opcode); break; |
95 | case 1<<12: op0001(opcode); break; |
96 | case 2<<12: op0010(opcode); break; |
97 | case 3<<12: op0011(opcode); break; |
98 | case 4<<12: op0100(opcode); break; |
99 | case 5<<12: op0101(opcode); break; |
100 | case 6<<12: op0110(opcode); break; |
101 | case 7<<12: op0111(opcode); break; |
102 | case 8<<12: op1000(opcode); break; |
103 | case 9<<12: op1001(opcode); break; |
104 | case 10<<12: op1010(opcode); break; |
105 | case 11<<12: op1011(opcode); break; |
106 | case 12<<12: op1100(opcode); break; |
107 | case 13<<12: op1101(opcode); break; |
108 | case 14<<12: op1110(opcode); break; |
109 | default: op1111(opcode); break; |
110 | } |
111 | |
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112 | sh2->icount--; |
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113 | |
114 | if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) |
115 | { |
116 | int level = sh2->pending_level; |
117 | int vector = sh2->irq_callback(sh2, level); |
118 | sh2_do_irq(sh2, level, vector); |
119 | sh2->test_irq = 0; |
120 | } |
121 | |
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122 | } |
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123 | while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */ |
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124 | |
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125 | sh2->cycles_done += cycles - sh2->icount; |
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126 | } |
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127 | |
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128 | #else // DRC_SH2 |
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129 | |
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130 | #ifdef __i386__ |
131 | #define REGPARM(x) __attribute__((regparm(x))) |
132 | #else |
133 | #define REGPARM(x) |
134 | #endif |
135 | |
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136 | // drc debug |
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137 | void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode) |
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138 | { |
139 | sh2 = sh2_; |
140 | sh2->pc += 2; |
141 | |
142 | switch (opcode & ( 15 << 12)) |
143 | { |
144 | case 0<<12: op0000(opcode); break; |
145 | case 1<<12: op0001(opcode); break; |
146 | case 2<<12: op0010(opcode); break; |
147 | case 3<<12: op0011(opcode); break; |
148 | case 4<<12: op0100(opcode); break; |
149 | case 5<<12: op0101(opcode); break; |
150 | case 6<<12: op0110(opcode); break; |
151 | case 7<<12: op0111(opcode); break; |
152 | case 8<<12: op1000(opcode); break; |
153 | case 9<<12: op1001(opcode); break; |
154 | case 10<<12: op1010(opcode); break; |
155 | case 11<<12: op1011(opcode); break; |
156 | case 12<<12: op1100(opcode); break; |
157 | case 13<<12: op1101(opcode); break; |
158 | case 14<<12: op1110(opcode); break; |
159 | default: op1111(opcode); break; |
160 | } |
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161 | } |
162 | |
163 | #endif |
164 | |
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165 | #ifdef SH2_STATS |
166 | #include <stdio.h> |
167 | #include <string.h> |
168 | #include "sh2dasm.h" |
169 | |
170 | void sh2_dump_stats(void) |
171 | { |
172 | static const char *rnames[] = { |
173 | "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", |
174 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP", |
175 | "PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL" |
176 | }; |
177 | long long total; |
178 | char buff[64]; |
179 | int u, i; |
180 | |
181 | // dump reg usage |
182 | total = 0; |
183 | for (i = 0; i < 24; i++) |
184 | total += sh2_stats.r[i]; |
185 | |
186 | for (i = 0; i < 24; i++) { |
187 | if (i == 16 || i == 17 || i == 19) |
188 | continue; |
189 | printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total, |
190 | rnames[i], sh2_stats.r[i]); |
191 | } |
192 | |
193 | memset(&sh2_stats, 0, sizeof(sh2_stats)); |
194 | |
195 | // dump ops |
196 | printf("\n"); |
197 | total = 0; |
198 | for (i = 0; i < 0x10000; i++) |
199 | total += op_refs[i]; |
200 | |
201 | for (u = 0; u < 16; u++) { |
202 | int max = 0, op = 0; |
203 | for (i = 0; i < 0x10000; i++) { |
204 | if (op_refs[i] > max) { |
205 | max = op_refs[i]; |
206 | op = i; |
207 | } |
208 | } |
209 | DasmSH2(buff, 0, op); |
210 | printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total, |
211 | op_refs[op], buff); |
212 | op_refs[op] = 0; |
213 | } |
214 | memset(op_refs, 0, sizeof(op_refs)); |
215 | } |
216 | #endif |
217 | |