[picodrive.git] / cpu / sh2 / mame / sh2pico.c

#include "../sh2.h"

#ifdef DRC_CMP
#include "../compiler.h"
#define BUSY_LOOP_HACKS 0
#else
#define BUSY_LOOP_HACKS 1
#endif

// MAME types
#ifndef INT8
typedef s8  INT8;
typedef s16 INT16;
typedef s32 INT32;
typedef u32 UINT32;
typedef u16 UINT16;
typedef u8  UINT8;
#endif

#ifdef DRC_SH2

// this nasty conversion is needed for drc-expecting memhandlers
#define MAKE_READFUNC(name, cname) \
static __inline unsigned int name(SH2 *sh2, unsigned int a) \
{ \
	unsigned int ret; \
	sh2->sr |= (sh2->icount << 12) | (sh2->no_polling); \
	ret = cname(a, sh2); \
	sh2->icount = (signed int)sh2->sr >> 12; \
	sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
	sh2->sr &= 0x3f3; \
	return ret; \
}

#define MAKE_WRITEFUNC(name, cname) \
static __inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
{ \
	sh2->sr |= (sh2->icount << 12) | (sh2->no_polling); \
	cname(a, d, sh2); \
	sh2->icount = (signed int)sh2->sr >> 12; \
	sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
	sh2->sr &= 0x3f3; \
}

MAKE_READFUNC(RB, p32x_sh2_read8)
MAKE_READFUNC(RW, p32x_sh2_read16)
MAKE_READFUNC(RL, p32x_sh2_read32)
MAKE_WRITEFUNC(WB, p32x_sh2_write8)
MAKE_WRITEFUNC(WW, p32x_sh2_write16)
MAKE_WRITEFUNC(WL, p32x_sh2_write32)

#else

#define RB(sh2, a) p32x_sh2_read8(a, sh2)
#define RW(sh2, a) p32x_sh2_read16(a, sh2)
#define RL(sh2, a) p32x_sh2_read32(a, sh2)
#define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
#define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
#define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)

#endif

// some stuff from sh2comn.h
#define T	0x00000001
#define S	0x00000002
#define I	0x000000f0
#define Q	0x00000100
#define M	0x00000200

#define AM	0xc7ffffff

#define FLAGS	(M|Q|I|S|T)

#define Rn	((opcode>>8)&15)
#define Rm	((opcode>>4)&15)

#define sh2_state SH2

extern void lprintf(const char *fmt, ...);
#define logerror lprintf

#ifdef SH2_STATS
static SH2 sh2_stats;
static unsigned int op_refs[0x10000];
# define LRN  1
# define LRM  2
# define LRNM (LRN|LRM)
# define rlog(rnm) {   \
  int op = opcode;     \
  if ((rnm) & LRN) {   \
    op &= ~0x0f00;     \
    sh2_stats.r[Rn]++; \
  }                    \
  if ((rnm) & LRM) {   \
    op &= ~0x00f0;     \
    sh2_stats.r[Rm]++; \
  }                    \
  op_refs[op]++;       \
}
# define rlog1(x) sh2_stats.r[x]++
# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
#else
# define rlog(x)
# define rlog1(...)
# define rlog2(...)
#endif

#include "sh2.c"

#ifndef DRC_CMP

int sh2_execute_interpreter(SH2 *sh2, int cycles)
{
	UINT32 opcode;

	sh2->icount = cycles;

	if (sh2->icount <= 0)
		goto out;

	do
	{
		if (sh2->delay)
		{
			sh2->ppc = sh2->delay;
			opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);

			// TODO: more branch types
			if ((opcode >> 13) == 5) { // BRA/BSR
				sh2->r[15] -= 4;
				WL(sh2, sh2->r[15], sh2->sr);
				sh2->r[15] -= 4;
				WL(sh2, sh2->r[15], sh2->pc);
				sh2->pc = RL(sh2, sh2->vbr + 6 * 4);
				sh2->icount -= 5;
				opcode = 9; // NOP
			}

			sh2->pc -= 2;
		}
		else
		{
			sh2->ppc = sh2->pc;
			opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
		}

		sh2->delay = 0;
		sh2->pc += 2;

		switch (opcode & ( 15 << 12))
		{
		case  0<<12: op0000(sh2, opcode); break;
		case  1<<12: op0001(sh2, opcode); break;
		case  2<<12: op0010(sh2, opcode); break;
		case  3<<12: op0011(sh2, opcode); break;
		case  4<<12: op0100(sh2, opcode); break;
		case  5<<12: op0101(sh2, opcode); break;
		case  6<<12: op0110(sh2, opcode); break;
		case  7<<12: op0111(sh2, opcode); break;
		case  8<<12: op1000(sh2, opcode); break;
		case  9<<12: op1001(sh2, opcode); break;
		case 10<<12: op1010(sh2, opcode); break;
		case 11<<12: op1011(sh2, opcode); break;
		case 12<<12: op1100(sh2, opcode); break;
		case 13<<12: op1101(sh2, opcode); break;
		case 14<<12: op1110(sh2, opcode); break;
		default: op1111(sh2, opcode); break;
		}

		sh2->icount--;

		if (sh2->test_irq && !sh2->delay)
		{
			int level = sh2->pending_level;
			if (level > ((sh2->sr >> 4) & 0x0f))
			{
				int vector = sh2->irq_callback(sh2, level);
				sh2_do_irq(sh2, level, vector);
			}
			sh2->test_irq = 0;
		}
	}
	while (sh2->icount > 0 || sh2->delay);	/* can't interrupt before delay */

out:
	return sh2->icount;
}

#else // if DRC_CMP

int sh2_execute_interpreter(SH2 *sh2, int cycles)
{
	static unsigned int base_pc_[2] = { 0, 0 };
	static unsigned int end_pc_[2] = { 0, 0 };
	static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
	unsigned int *base_pc = &base_pc_[sh2->is_slave];
	unsigned int *end_pc = &end_pc_[sh2->is_slave];
	unsigned char *op_flags = op_flags_[sh2->is_slave];
	unsigned int pc_expect;
	UINT32 opcode;

	sh2->icount = sh2->cycles_timeslice = cycles;

	if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	{
		int level = sh2->pending_level;
		int vector = sh2->irq_callback(sh2, level);
		sh2_do_irq(sh2, level, vector);
	}
	pc_expect = sh2->pc;

	if (sh2->icount <= 0)
		goto out;

	do
	{
		if (!sh2->delay) {
			if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
				*base_pc = sh2->pc;
				scan_block(*base_pc, sh2->is_slave,
					op_flags, end_pc, NULL, NULL);
			}
			if ((op_flags[(sh2->pc - *base_pc) / 2]
				& OF_BTARGET) || sh2->pc == *base_pc
				|| pc_expect != sh2->pc) // branched
			{
				pc_expect = sh2->pc;
				if (sh2->icount <= 0)
					break;
			}

			do_sh2_trace(sh2, sh2->icount);
		}
		pc_expect += 2;

		if (sh2->delay)
		{
			sh2->ppc = sh2->delay;
			opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
			sh2->pc -= 2;
		}
		else
		{
			sh2->ppc = sh2->pc;
			opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
		}

		sh2->delay = 0;
		sh2->pc += 2;

		switch (opcode & ( 15 << 12))
		{
		case  0<<12: op0000(sh2, opcode); break;
		case  1<<12: op0001(sh2, opcode); break;
		case  2<<12: op0010(sh2, opcode); break;
		case  3<<12: op0011(sh2, opcode); break;
		case  4<<12: op0100(sh2, opcode); break;
		case  5<<12: op0101(sh2, opcode); break;
		case  6<<12: op0110(sh2, opcode); break;
		case  7<<12: op0111(sh2, opcode); break;
		case  8<<12: op1000(sh2, opcode); break;
		case  9<<12: op1001(sh2, opcode); break;
		case 10<<12: op1010(sh2, opcode); break;
		case 11<<12: op1011(sh2, opcode); break;
		case 12<<12: op1100(sh2, opcode); break;
		case 13<<12: op1101(sh2, opcode); break;
		case 14<<12: op1110(sh2, opcode); break;
		default: op1111(sh2, opcode); break;
		}

		sh2->icount--;

		if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
		{
			int level = sh2->pending_level;
			int vector = sh2->irq_callback(sh2, level);
			sh2_do_irq(sh2, level, vector);
			sh2->test_irq = 0;
		}

	}
	while (1);

out:
	return sh2->icount;
}

#endif // DRC_CMP

#ifdef SH2_STATS
#include <stdio.h>
#include <string.h>
#include "sh2dasm.h"

void sh2_dump_stats(void)
{
	static const char *rnames[] = {
		"R0", "R1", "R2",  "R3",  "R4",  "R5",  "R6",  "R7",
		"R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
		"PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
	};
	long long total;
	char buff[64];
	int u, i;

	// dump reg usage
	total = 0;
	for (i = 0; i < 24; i++)
		total += sh2_stats.r[i];

	for (i = 0; i < 24; i++) {
		if (i == 16 || i == 17 || i == 19)
			continue;
		printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
			rnames[i], sh2_stats.r[i]);
	}

	memset(&sh2_stats, 0, sizeof(sh2_stats));

	// dump ops
	printf("\n");
	total = 0;
	for (i = 0; i < 0x10000; i++)
		total += op_refs[i];

	for (u = 0; u < 16; u++) {
		int max = 0, op = 0;
		for (i = 0; i < 0x10000; i++) {
			if (op_refs[i] > max) {
				max = op_refs[i];
				op = i;
			}
		}
		DasmSH2(buff, 0, op);
		printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
			op_refs[op], buff);
		op_refs[op] = 0;
	}
	memset(op_refs, 0, sizeof(op_refs));
}
#endif
Commit	Line	Data
41397701	1	#include "../sh2.h"
405dfdd7	2
00faec9c	3	#ifdef DRC_CMP
31efd454	4	#include "../compiler.h"
405dfdd7	5	#define BUSY_LOOP_HACKS 0
	6	#else
	7	#define BUSY_LOOP_HACKS 1
00faec9c	8	#endif
eaa10a6e	9
eaa10a6e	10	// MAME types
00faec9c	11	#ifndef INT8
f821bb70	12	typedef s8 INT8;
	13	typedef s16 INT16;
	14	typedef s32 INT32;
	15	typedef u32 UINT32;
	16	typedef u16 UINT16;
	17	typedef u8 UINT8;
00faec9c	18	#endif
eaa10a6e	19
0185b677	20	#ifdef DRC_SH2
	21
	22	// this nasty conversion is needed for drc-expecting memhandlers
	23	#define MAKE_READFUNC(name, cname) \
e9a11abb	24	static __inline unsigned int name(SH2 *sh2, unsigned int a) \
0185b677	25	{ \
0185b677	26	unsigned int ret; \
bd078083	27	sh2->sr \|= (sh2->icount << 12) \| (sh2->no_polling); \
0185b677	28	ret = cname(a, sh2); \
0185b677	29	sh2->icount = (signed int)sh2->sr >> 12; \
bd078083	30	sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
0185b677	31	sh2->sr &= 0x3f3; \
	32	return ret; \
	33	}
	34
	35	#define MAKE_WRITEFUNC(name, cname) \
e9a11abb	36	static __inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
0185b677	37	{ \
bd078083	38	sh2->sr \|= (sh2->icount << 12) \| (sh2->no_polling); \
0185b677	39	cname(a, d, sh2); \
0185b677	40	sh2->icount = (signed int)sh2->sr >> 12; \
bd078083	41	sh2->no_polling = (sh2->sr & SH2_NO_POLLING); \
0185b677	42	sh2->sr &= 0x3f3; \
	43	}
	44
	45	MAKE_READFUNC(RB, p32x_sh2_read8)
	46	MAKE_READFUNC(RW, p32x_sh2_read16)
	47	MAKE_READFUNC(RL, p32x_sh2_read32)
	48	MAKE_WRITEFUNC(WB, p32x_sh2_write8)
	49	MAKE_WRITEFUNC(WW, p32x_sh2_write16)
	50	MAKE_WRITEFUNC(WL, p32x_sh2_write32)
	51
	52	#else
	53
	54	#define RB(sh2, a) p32x_sh2_read8(a, sh2)
	55	#define RW(sh2, a) p32x_sh2_read16(a, sh2)
	56	#define RL(sh2, a) p32x_sh2_read32(a, sh2)
	57	#define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
	58	#define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
	59	#define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)
	60
	61	#endif
eaa10a6e	62
	63	// some stuff from sh2comn.h
	64	#define T 0x00000001
	65	#define S 0x00000002
	66	#define I 0x000000f0
	67	#define Q 0x00000100
	68	#define M 0x00000200
	69
	70	#define AM 0xc7ffffff
	71
	72	#define FLAGS (M\|Q\|I\|S\|T)
	73
	74	#define Rn ((opcode>>8)&15)
	75	#define Rm ((opcode>>4)&15)
	76
f4c0720c	77	#define sh2_state SH2
	78
	79	extern void lprintf(const char *fmt, ...);
	80	#define logerror lprintf
1d7a28a7	81
71f68165	82	#ifdef SH2_STATS
	83	static SH2 sh2_stats;
	84	static unsigned int op_refs[0x10000];
	85	# define LRN 1
	86	# define LRM 2
	87	# define LRNM (LRN\|LRM)
	88	# define rlog(rnm) { \
	89	int op = opcode; \
	90	if ((rnm) & LRN) { \
	91	op &= ~0x0f00; \
	92	sh2_stats.r[Rn]++; \
	93	} \
	94	if ((rnm) & LRM) { \
	95	op &= ~0x00f0; \
	96	sh2_stats.r[Rm]++; \
	97	} \
	98	op_refs[op]++; \
	99	}
	100	# define rlog1(x) sh2_stats.r[x]++
	101	# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
	102	#else
	103	# define rlog(x)
	104	# define rlog1(...)
	105	# define rlog2(...)
	106	#endif
	107
41397701	108	#include "sh2.c"
1d7a28a7	109
405dfdd7	110	#ifndef DRC_CMP
405dfdd7	111
0185b677	112	int sh2_execute_interpreter(SH2 *sh2, int cycles)
405dfdd7	113	{
	114	UINT32 opcode;
	115
0185b677	116	sh2->icount = cycles;
405dfdd7	117
	118	if (sh2->icount <= 0)
	119	goto out;
	120
	121	do
	122	{
	123	if (sh2->delay)
	124	{
	125	sh2->ppc = sh2->delay;
aa4c4cb9	126	opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
6a5b1b36	127
	128	// TODO: more branch types
	129	if ((opcode >> 13) == 5) { // BRA/BSR
	130	sh2->r[15] -= 4;
	131	WL(sh2, sh2->r[15], sh2->sr);
	132	sh2->r[15] -= 4;
	133	WL(sh2, sh2->r[15], sh2->pc);
	134	sh2->pc = RL(sh2, sh2->vbr + 6 * 4);
	135	sh2->icount -= 5;
	136	opcode = 9; // NOP
	137	}
	138
405dfdd7	139	sh2->pc -= 2;
	140	}
	141	else
	142	{
	143	sh2->ppc = sh2->pc;
aa4c4cb9	144	opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
405dfdd7	145	}
	146
	147	sh2->delay = 0;
	148	sh2->pc += 2;
	149
	150	switch (opcode & ( 15 << 12))
	151	{
	152	case 0<<12: op0000(sh2, opcode); break;
	153	case 1<<12: op0001(sh2, opcode); break;
	154	case 2<<12: op0010(sh2, opcode); break;
	155	case 3<<12: op0011(sh2, opcode); break;
	156	case 4<<12: op0100(sh2, opcode); break;
	157	case 5<<12: op0101(sh2, opcode); break;
	158	case 6<<12: op0110(sh2, opcode); break;
	159	case 7<<12: op0111(sh2, opcode); break;
	160	case 8<<12: op1000(sh2, opcode); break;
	161	case 9<<12: op1001(sh2, opcode); break;
	162	case 10<<12: op1010(sh2, opcode); break;
	163	case 11<<12: op1011(sh2, opcode); break;
	164	case 12<<12: op1100(sh2, opcode); break;
	165	case 13<<12: op1101(sh2, opcode); break;
	166	case 14<<12: op1110(sh2, opcode); break;
	167	default: op1111(sh2, opcode); break;
	168	}
	169
	170	sh2->icount--;
	171
f99f0794	172	if (sh2->test_irq && !sh2->delay)
405dfdd7	173	{
405dfdd7	174	int level = sh2->pending_level;
f99f0794	175	if (level > ((sh2->sr >> 4) & 0x0f))
	176	{
	177	int vector = sh2->irq_callback(sh2, level);
	178	sh2_do_irq(sh2, level, vector);
	179	}
405dfdd7	180	sh2->test_irq = 0;
405dfdd7	181	}
405dfdd7	182	}
	183	while (sh2->icount > 0 \|\| sh2->delay); /* can't interrupt before delay */
	184
	185	out:
0185b677	186	return sh2->icount;
405dfdd7	187	}
	188
	189	#else // if DRC_CMP
679af8a3	190
0185b677	191	int sh2_execute_interpreter(SH2 *sh2, int cycles)
eaa10a6e	192	{
6d797957	193	static unsigned int base_pc_[2] = { 0, 0 };
	194	static unsigned int end_pc_[2] = { 0, 0 };
	195	static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
	196	unsigned int *base_pc = &base_pc_[sh2->is_slave];
	197	unsigned int *end_pc = &end_pc_[sh2->is_slave];
	198	unsigned char *op_flags = op_flags_[sh2->is_slave];
405dfdd7	199	unsigned int pc_expect;
00faec9c	200	UINT32 opcode;
00faec9c	201
405dfdd7	202	sh2->icount = sh2->cycles_timeslice = cycles;
41397701	203
405dfdd7	204	if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	205	{
	206	int level = sh2->pending_level;
	207	int vector = sh2->irq_callback(sh2, level);
	208	sh2_do_irq(sh2, level, vector);
	209	}
	210	pc_expect = sh2->pc;
ed4402a7	211
405dfdd7	212	if (sh2->icount <= 0)
405dfdd7	213	goto out;
eaa10a6e	214
	215	do
	216	{
00faec9c	217	if (!sh2->delay) {
6d797957	218	if (sh2->pc < base_pc \|\| sh2->pc >= end_pc) {
	219	*base_pc = sh2->pc;
	220	scan_block(*base_pc, sh2->is_slave,
d40a5af4	221	op_flags, end_pc, NULL, NULL);
00faec9c	222	}
6d797957	223	if ((op_flags[(sh2->pc - *base_pc) / 2]
	224	& OF_BTARGET) \|\| sh2->pc == *base_pc
	225	\|\| pc_expect != sh2->pc) // branched
bf092a36	226	{
6d797957	227	pc_expect = sh2->pc;
fa0d0d22	228	if (sh2->icount <= 0)
00faec9c	229	break;
	230	}
	231
	232	do_sh2_trace(sh2, sh2->icount);
	233	}
6d797957	234	pc_expect += 2;
eaa10a6e	235
3cf9570b	236	if (sh2->delay)
3cf9570b	237	{
a44737c1	238	sh2->ppc = sh2->delay;
aa4c4cb9	239	opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
3cf9570b	240	sh2->pc -= 2;
	241	}
	242	else
a44737c1	243	{
a44737c1	244	sh2->ppc = sh2->pc;
aa4c4cb9	245	opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
a44737c1	246	}
eaa10a6e	247
	248	sh2->delay = 0;
	249	sh2->pc += 2;
eaa10a6e	250
	251	switch (opcode & ( 15 << 12))
	252	{
f4c0720c	253	case 0<<12: op0000(sh2, opcode); break;
	254	case 1<<12: op0001(sh2, opcode); break;
	255	case 2<<12: op0010(sh2, opcode); break;
	256	case 3<<12: op0011(sh2, opcode); break;
	257	case 4<<12: op0100(sh2, opcode); break;
	258	case 5<<12: op0101(sh2, opcode); break;
	259	case 6<<12: op0110(sh2, opcode); break;
	260	case 7<<12: op0111(sh2, opcode); break;
	261	case 8<<12: op1000(sh2, opcode); break;
	262	case 9<<12: op1001(sh2, opcode); break;
	263	case 10<<12: op1010(sh2, opcode); break;
	264	case 11<<12: op1011(sh2, opcode); break;
	265	case 12<<12: op1100(sh2, opcode); break;
	266	case 13<<12: op1101(sh2, opcode); break;
	267	case 14<<12: op1110(sh2, opcode); break;
	268	default: op1111(sh2, opcode); break;
eaa10a6e	269	}
eaa10a6e	270
41397701	271	sh2->icount--;
1f1ff763	272
	273	if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
	274	{
	275	int level = sh2->pending_level;
	276	int vector = sh2->irq_callback(sh2, level);
	277	sh2_do_irq(sh2, level, vector);
	278	sh2->test_irq = 0;
	279	}
	280
eaa10a6e	281	}
00faec9c	282	while (1);
553c3eaa	283
405dfdd7	284	out:
0185b677	285	return sh2->icount;
679af8a3	286	}
679af8a3	287
405dfdd7	288	#endif // DRC_CMP
679af8a3	289
71f68165	290	#ifdef SH2_STATS
	291	#include <stdio.h>
	292	#include <string.h>
	293	#include "sh2dasm.h"
	294
	295	void sh2_dump_stats(void)
	296	{
	297	static const char *rnames[] = {
	298	"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
	299	"R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
	300	"PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
	301	};
	302	long long total;
	303	char buff[64];
	304	int u, i;
	305
	306	// dump reg usage
	307	total = 0;
	308	for (i = 0; i < 24; i++)
	309	total += sh2_stats.r[i];
	310
	311	for (i = 0; i < 24; i++) {
	312	if (i == 16 \|\| i == 17 \|\| i == 19)
	313	continue;
	314	printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
	315	rnames[i], sh2_stats.r[i]);
	316	}
	317
	318	memset(&sh2_stats, 0, sizeof(sh2_stats));
	319
	320	// dump ops
	321	printf("\n");
	322	total = 0;
	323	for (i = 0; i < 0x10000; i++)
	324	total += op_refs[i];
	325
	326	for (u = 0; u < 16; u++) {
	327	int max = 0, op = 0;
	328	for (i = 0; i < 0x10000; i++) {
	329	if (op_refs[i] > max) {
	330	max = op_refs[i];
	331	op = i;
	332	}
	333	}
	334	DasmSH2(buff, 0, op);
	335	printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
	336	op_refs[op], buff);
	337	op_refs[op] = 0;
	338	}
	339	memset(op_refs, 0, sizeof(op_refs));
	340	}
	341	#endif
	342