32x: split sh2 code, compiler stub
[picodrive.git] / cpu / sh2 / mame / sh2pico.c
CommitLineData
41397701 1#include "../sh2.h"
eaa10a6e 2
3// MAME types
4typedef signed char INT8;
5typedef signed short INT16;
6typedef signed int INT32;
7typedef unsigned int UINT32;
8typedef unsigned short UINT16;
9typedef unsigned char UINT8;
10
b78efee2 11#define RB(a) p32x_sh2_read8(a,sh2->is_slave)
12#define RW(a) p32x_sh2_read16(a,sh2->is_slave)
13#define RL(a) p32x_sh2_read32(a,sh2->is_slave)
14#define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
15#define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
16#define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)
eaa10a6e 17
18// some stuff from sh2comn.h
19#define T 0x00000001
20#define S 0x00000002
21#define I 0x000000f0
22#define Q 0x00000100
23#define M 0x00000200
24
25#define AM 0xc7ffffff
26
27#define FLAGS (M|Q|I|S|T)
28
29#define Rn ((opcode>>8)&15)
30#define Rm ((opcode>>4)&15)
31
41397701 32#define sh2_icount sh2->icount
1d7a28a7 33
41397701 34#include "sh2.c"
1d7a28a7 35
41397701 36void sh2_execute(SH2 *sh2_, int cycles)
eaa10a6e 37{
38 sh2 = sh2_;
2ea2cbfe 39 sh2->cycles_aim += cycles;
41397701 40 sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
41
42 if (sh2->icount <= 0)
43 return;
eaa10a6e 44
45 do
46 {
47 UINT32 opcode;
48
3cf9570b 49 if (sh2->delay)
50 {
a44737c1 51 sh2->ppc = sh2->delay;
3cf9570b 52 opcode = RW(sh2->delay);
53 sh2->pc -= 2;
54 }
55 else
a44737c1 56 {
57 sh2->ppc = sh2->pc;
3cf9570b 58 opcode = RW(sh2->pc);
a44737c1 59 }
eaa10a6e 60
61 sh2->delay = 0;
62 sh2->pc += 2;
eaa10a6e 63
64 switch (opcode & ( 15 << 12))
65 {
66 case 0<<12: op0000(opcode); break;
67 case 1<<12: op0001(opcode); break;
68 case 2<<12: op0010(opcode); break;
69 case 3<<12: op0011(opcode); break;
70 case 4<<12: op0100(opcode); break;
71 case 5<<12: op0101(opcode); break;
72 case 6<<12: op0110(opcode); break;
73 case 7<<12: op0111(opcode); break;
74 case 8<<12: op1000(opcode); break;
75 case 9<<12: op1001(opcode); break;
76 case 10<<12: op1010(opcode); break;
77 case 11<<12: op1011(opcode); break;
78 case 12<<12: op1100(opcode); break;
79 case 13<<12: op1101(opcode); break;
80 case 14<<12: op1110(opcode); break;
81 default: op1111(opcode); break;
82 }
83
84 if (sh2->test_irq && !sh2->delay)
85 {
1d7a28a7 86 if (sh2->pending_irl > sh2->pending_int_irq)
87 sh2_irl_irq(sh2, sh2->pending_irl);
88 else
89 sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
eaa10a6e 90 sh2->test_irq = 0;
91 }
41397701 92 sh2->icount--;
eaa10a6e 93 }
41397701 94 while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
4ea707e1 95
41397701 96 sh2->cycles_done += cycles - sh2->icount;
4ea707e1 97}
eaa10a6e 98