2823a4c8 |
1 | /* gameplaySP |
2 | * |
3 | * Copyright (C) 2006 Exophase <exophase@gmail.com> |
4 | * |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License as |
7 | * published by the Free Software Foundation; either version 2 of |
8 | * the License, or (at your option) any later version. |
9 | * |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
13 | * General Public License for more details. |
14 | * |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
18 | */ |
19 | |
20 | #ifndef CPU_H |
21 | #define CPU_H |
22 | |
23 | // System mode and user mode are represented as the same here |
24 | |
25 | typedef enum |
26 | { |
27 | MODE_USER, |
28 | MODE_IRQ, |
29 | MODE_FIQ, |
30 | MODE_SUPERVISOR, |
31 | MODE_ABORT, |
32 | MODE_UNDEFINED, |
33 | MODE_INVALID |
34 | } cpu_mode_type; |
35 | |
36 | typedef enum |
37 | { |
38 | CPU_ALERT_NONE, |
39 | CPU_ALERT_HALT, |
40 | CPU_ALERT_SMC, |
41 | CPU_ALERT_IRQ |
42 | } cpu_alert_type; |
43 | |
44 | typedef enum |
45 | { |
46 | CPU_ACTIVE, |
47 | CPU_HALT, |
48 | CPU_STOP |
49 | } cpu_halt_type; |
50 | |
51 | typedef enum |
52 | { |
53 | IRQ_NONE = 0x0000, |
54 | IRQ_VBLANK = 0x0001, |
55 | IRQ_HBLANK = 0x0002, |
56 | IRQ_VCOUNT = 0x0004, |
57 | IRQ_TIMER0 = 0x0008, |
58 | IRQ_TIMER1 = 0x0010, |
59 | IRQ_TIMER2 = 0x0020, |
60 | IRQ_TIMER3 = 0x0040, |
61 | IRQ_SERIAL = 0x0080, |
62 | IRQ_DMA0 = 0x0100, |
63 | IRQ_DMA1 = 0x0200, |
64 | IRQ_DMA2 = 0x0400, |
65 | IRQ_DMA3 = 0x0800, |
66 | IRQ_KEYPAD = 0x1000, |
67 | IRQ_GAMEPAK = 0x2000, |
68 | } irq_type; |
69 | |
70 | typedef enum |
71 | { |
72 | REG_SP = 13, |
73 | REG_LR = 14, |
74 | REG_PC = 15, |
75 | REG_N_FLAG = 16, |
76 | REG_Z_FLAG = 17, |
77 | REG_C_FLAG = 18, |
78 | REG_V_FLAG = 19, |
79 | REG_CPSR = 20, |
80 | REG_SAVE = 21, |
81 | REG_SAVE2 = 22, |
82 | REG_SAVE3 = 23, |
83 | CPU_MODE = 29, |
84 | CPU_HALT_STATE = 30, |
85 | CHANGED_PC_STATUS = 31 |
86 | } ext_reg_numbers; |
87 | |
88 | typedef enum |
89 | { |
90 | STEP, |
91 | PC_BREAKPOINT, |
92 | VCOUNT_BREAKPOINT, |
93 | Z_BREAKPOINT, |
94 | COUNTDOWN_BREAKPOINT, |
95 | COUNTDOWN_BREAKPOINT_B, |
96 | COUNTDOWN_BREAKPOINT_C, |
97 | STEP_RUN, |
98 | RUN |
99 | } debug_state; |
100 | |
101 | typedef enum |
102 | { |
103 | TRANSLATION_REGION_RAM, |
104 | TRANSLATION_REGION_ROM, |
105 | TRANSLATION_REGION_BIOS |
106 | } translation_region_type; |
107 | |
108 | extern debug_state current_debug_state; |
109 | extern u32 instruction_count; |
110 | extern u32 last_instruction; |
111 | |
112 | u32 function_cc step_debug(u32 pc, u32 cycles); |
113 | u32 execute_arm(u32 cycles); |
114 | void raise_interrupt(irq_type irq_raised); |
115 | |
116 | u32 function_cc execute_load_u8(u32 address); |
117 | u32 function_cc execute_load_u16(u32 address); |
118 | u32 function_cc execute_load_u32(u32 address); |
119 | u32 function_cc execute_load_s8(u32 address); |
120 | u32 function_cc execute_load_s16(u32 address); |
121 | void function_cc execute_store_u8(u32 address, u32 source); |
122 | void function_cc execute_store_u16(u32 address, u32 source); |
123 | void function_cc execute_store_u32(u32 address, u32 source); |
124 | u32 function_cc execute_arm_translate(u32 cycles); |
125 | void init_translater(); |
126 | void cpu_write_mem_savestate(file_tag_type savestate_file); |
127 | void cpu_read_savestate(file_tag_type savestate_file); |
128 | |
129 | u8 function_cc *block_lookup_address_arm(u32 pc); |
130 | u8 function_cc *block_lookup_address_thumb(u32 pc); |
131 | s32 translate_block_arm(u32 pc, translation_region_type translation_region, |
132 | u32 smc_enable); |
133 | s32 translate_block_thumb(u32 pc, translation_region_type translation_region, |
134 | u32 smc_enable); |
135 | |
136 | #ifdef GP2X_BUILD |
137 | #define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5) |
138 | #define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2) |
139 | #define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128 * 2) |
140 | #define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32) |
141 | |
142 | #else |
143 | |
144 | #define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4) |
145 | #define RAM_TRANSLATION_CACHE_SIZE (1024 * 384) |
146 | #define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128) |
147 | #define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024) |
148 | |
149 | #endif |
150 | |
151 | extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]; |
152 | extern u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]; |
153 | extern u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]; |
154 | extern u8 *rom_translation_ptr; |
155 | extern u8 *ram_translation_ptr; |
156 | extern u8 *bios_translation_ptr; |
157 | |
158 | #define MAX_TRANSLATION_GATES 8 |
159 | |
160 | extern u32 idle_loop_target_pc; |
161 | extern u32 force_pc_update_target; |
162 | extern u32 iwram_stack_optimize; |
163 | extern u32 allow_smc_ram_u8; |
164 | extern u32 allow_smc_ram_u16; |
165 | extern u32 allow_smc_ram_u32; |
166 | extern u32 direct_map_vram; |
167 | extern u32 translation_gate_targets; |
168 | extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES]; |
169 | |
170 | extern u32 in_interrupt; |
171 | |
172 | #define ROM_BRANCH_HASH_SIZE (1024 * 64) |
173 | |
174 | /* EDIT: Shouldn't this be extern ?! */ |
175 | extern u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE]; |
176 | |
177 | void flush_translation_cache_rom(); |
178 | void flush_translation_cache_ram(); |
179 | void flush_translation_cache_bios(); |
180 | void dump_translation_cache(); |
181 | |
182 | extern u32 reg_mode[7][7]; |
183 | extern u32 spsr[6]; |
184 | |
185 | extern u32 cpu_modes[32]; |
186 | extern const u32 psr_masks[16]; |
187 | |
188 | extern u32 breakpoint_value; |
189 | |
190 | extern u32 memory_region_access_read_u8[16]; |
191 | extern u32 memory_region_access_read_s8[16]; |
192 | extern u32 memory_region_access_read_u16[16]; |
193 | extern u32 memory_region_access_read_s16[16]; |
194 | extern u32 memory_region_access_read_u32[16]; |
195 | extern u32 memory_region_access_write_u8[16]; |
196 | extern u32 memory_region_access_write_u16[16]; |
197 | extern u32 memory_region_access_write_u32[16]; |
198 | extern u32 memory_reads_u8; |
199 | extern u32 memory_reads_s8; |
200 | extern u32 memory_reads_u16; |
201 | extern u32 memory_reads_s16; |
202 | extern u32 memory_reads_u32; |
203 | extern u32 memory_writes_u8; |
204 | extern u32 memory_writes_u16; |
205 | extern u32 memory_writes_u32; |
206 | |
207 | void init_cpu(); |
208 | void move_reg(); |
209 | |
210 | #endif |