9e052883 |
1 | CODE32\r |
2 | \r |
3 | EXPORT |CrcUpdateT4@16|\r |
4 | \r |
5 | AREA |.text|, CODE, ARM\r |
6 | \r |
7 | MACRO\r |
8 | CRC32_STEP_1\r |
9 | \r |
10 | ldrb r4, [r1], #1\r |
11 | subs r2, r2, #1\r |
12 | eor r4, r4, r0\r |
13 | and r4, r4, #0xFF\r |
14 | ldr r4, [r3, +r4, lsl #2]\r |
15 | eor r0, r4, r0, lsr #8\r |
16 | \r |
17 | MEND\r |
18 | \r |
19 | \r |
20 | MACRO\r |
21 | CRC32_STEP_4 $STREAM_WORD\r |
22 | \r |
23 | eor r7, r7, r8\r |
24 | eor r7, r7, r9\r |
25 | eor r0, r0, r7\r |
26 | eor r0, r0, $STREAM_WORD\r |
27 | ldr $STREAM_WORD, [r1], #4\r |
28 | \r |
29 | and r7, r0, #0xFF\r |
30 | and r8, r0, #0xFF00\r |
31 | and r9, r0, #0xFF0000\r |
32 | and r0, r0, #0xFF000000\r |
33 | \r |
34 | ldr r7, [r6, +r7, lsl #2]\r |
35 | ldr r8, [r5, +r8, lsr #6]\r |
36 | ldr r9, [r4, +r9, lsr #14]\r |
37 | ldr r0, [r3, +r0, lsr #22]\r |
38 | \r |
39 | MEND\r |
40 | \r |
41 | \r |
42 | |CrcUpdateT4@16| PROC\r |
43 | \r |
44 | stmdb sp!, {r4-r11, lr}\r |
45 | cmp r2, #0\r |
46 | beq |$fin|\r |
47 | \r |
48 | |$v1|\r |
49 | tst r1, #7\r |
50 | beq |$v2|\r |
51 | CRC32_STEP_1\r |
52 | bne |$v1|\r |
53 | \r |
54 | |$v2|\r |
55 | cmp r2, #16\r |
56 | blo |$v3|\r |
57 | \r |
58 | ldr r10, [r1], #4\r |
59 | ldr r11, [r1], #4\r |
60 | \r |
61 | add r4, r3, #0x400 \r |
62 | add r5, r3, #0x800\r |
63 | add r6, r3, #0xC00\r |
64 | \r |
65 | mov r7, #0\r |
66 | mov r8, #0\r |
67 | mov r9, #0\r |
68 | \r |
69 | sub r2, r2, #16\r |
70 | \r |
71 | |$loop|\r |
72 | ; pld [r1, #0x40]\r |
73 | \r |
74 | CRC32_STEP_4 r10\r |
75 | CRC32_STEP_4 r11\r |
76 | \r |
77 | subs r2, r2, #8\r |
78 | bhs |$loop|\r |
79 | \r |
80 | sub r1, r1, #8\r |
81 | add r2, r2, #16\r |
82 | \r |
83 | eor r7, r7, r8\r |
84 | eor r7, r7, r9\r |
85 | eor r0, r0, r7\r |
86 | \r |
87 | |$v3|\r |
88 | cmp r2, #0\r |
89 | beq |$fin|\r |
90 | \r |
91 | |$v4|\r |
92 | CRC32_STEP_1\r |
93 | bne |$v4|\r |
94 | \r |
95 | |$fin|\r |
96 | ldmia sp!, {r4-r11, pc}\r |
97 | \r |
98 | |CrcUpdateT4@16| ENDP\r |
99 | \r |
100 | END\r |