lightrec: Only sync register cache before savestate if using dynarec
[pcsx_rearmed.git] / deps / lightning / check / alu_rsb.tst
CommitLineData
4a71579b
PC
1#include "alu.inc"
2
3.code
4 prolog
5
6#define RSB(N, I0, I1, V) ALU(N, , rsb, I0, I1, V)
7
8 RSB(0, 1, 0x7fffffff, 0x7ffffffe)
9 RSB(2, 1, 0x80000000, 0x7fffffff)
10 RSB(3, 0x7fffffff, 0x80000000, 1)
11 RSB(4, 0xffffffff, 0xffffffff, 0)
12 RSB(5, 0x7fffffff, 0xffffffff, 0x80000000)
13 RSB(6, 0, 0x7fffffff, 0x7fffffff)
14#if __WORDSIZE == 32
15 RSB(7, 0x7fffffff, 1, 0x80000002)
16 RSB(8, 0x80000000, 1, 0x80000001)
17 RSB(9, 0x80000000, 0x7fffffff, 0xffffffff)
18 RSB(10, 0xffffffff, 0x7fffffff, 0x80000000)
19 RSB(11, 0x7fffffff, 0, 0x80000001)
20#else
21 RSB(7, 0x7fffffff, 1, 0xffffffff80000002)
22 RSB(8, 0xffffffff80000000, 1, 0x80000001)
23 RSB(9, 0xffffffff80000000, 0x7fffffff, 0xffffffff)
24 RSB(10, 0xffffffffffffffff, 0xffffffff7fffffff, 0xffffffff80000000)
25 RSB(11, 0x7fffffff, 0, 0xffffffff80000001)
26 RSB(12, 1, 0x7fffffffffffffff, 0x7ffffffffffffffe)
27 RSB(13, 0x7fffffffffffffff, 1, 0x8000000000000002)
28 RSB(14, 1, 0x8000000000000000, 0x7fffffffffffffff)
29 RSB(15, 0x8000000000000000, 1, 0x8000000000000001)
30 RSB(16, 0x8000000000000000, 0x7fffffffffffffff, 0xffffffffffffffff)
31 RSB(17, 0x7fffffffffffffff, 0x8000000000000000, 1)
32 RSB(18, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000)
33 RSB(19, 0x7fffffffffffffff, 0xffffffffffffffff, 0x8000000000000000)
34 RSB(20, 0xffffffffffffffff, 0xffffffffffffffff, 0)
35#endif
36
37#undef RSB
38#define RSB(N, T, I0, I1, V) FOP(N, T, rsb, I0, I1, V)
39 RSB(0, _f, 0.5, -0.5, -1.0)
40 RSB(1, _f, 0.75, 0.25, -0.5)
41 RSB(0, _d, 0.5, -0.5, -1.0)
42 RSB(1, _d, 0.75, 0.25, -0.5)
43
44 prepare
45 pushargi ok
46 ellipsis
47 finishi @printf
48 ret
49 epilog