[pcsx_rearmed.git] / deps / lightrec / disassembler.h

/* SPDX-License-Identifier: LGPL-2.1-or-later */
/*
 * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
 */

#ifndef __DISASSEMBLER_H__
#define __DISASSEMBLER_H__

#include "debug.h"
#include "lightrec.h"
#include "lightrec-config.h"

#ifndef __packed
#define __packed __attribute__((packed))
#endif

#define BIT(x) (1ULL << (x))

/* Flags for all opcodes */
#define LIGHTREC_NO_DS		BIT(0)
#define LIGHTREC_SYNC		BIT(1)

/* Flags for LUI, ORI, ADDIU */
#define LIGHTREC_MOVI		BIT(2)

/* Flags for load/store opcodes */
#define LIGHTREC_SMC		BIT(2)
#define LIGHTREC_NO_INVALIDATE	BIT(3)
#define LIGHTREC_NO_MASK	BIT(4)
#define LIGHTREC_LOAD_DELAY	BIT(5)

/* I/O mode for load/store opcodes */
#define LIGHTREC_IO_MODE_LSB	6
#define LIGHTREC_IO_MODE(x)	((x) << LIGHTREC_IO_MODE_LSB)
#define LIGHTREC_IO_UNKNOWN	0x0
#define LIGHTREC_IO_DIRECT	0x1
#define LIGHTREC_IO_HW		0x2
#define LIGHTREC_IO_RAM		0x3
#define LIGHTREC_IO_BIOS	0x4
#define LIGHTREC_IO_SCRATCH	0x5
#define LIGHTREC_IO_DIRECT_HW	0x6
#define LIGHTREC_IO_MASK	LIGHTREC_IO_MODE(0x7)
#define LIGHTREC_FLAGS_GET_IO_MODE(x) \
	(((x) & LIGHTREC_IO_MASK) >> LIGHTREC_IO_MODE_LSB)

/* Flags for branches */
#define LIGHTREC_EMULATE_BRANCH	BIT(2)
#define LIGHTREC_LOCAL_BRANCH	BIT(3)

/* Flags for div/mult opcodes */
#define LIGHTREC_NO_LO		BIT(2)
#define LIGHTREC_NO_HI		BIT(3)
#define LIGHTREC_NO_DIV_CHECK	BIT(4)

#define LIGHTREC_REG_RS_LSB	26
#define LIGHTREC_REG_RS(x)	((x) << LIGHTREC_REG_RS_LSB)
#define LIGHTREC_REG_RS_MASK	LIGHTREC_REG_RS(0x3)
#define LIGHTREC_FLAGS_GET_RS(x) \
	(((x) & LIGHTREC_REG_RS_MASK) >> LIGHTREC_REG_RS_LSB)

#define LIGHTREC_REG_RT_LSB	28
#define LIGHTREC_REG_RT(x)	((x) << LIGHTREC_REG_RT_LSB)
#define LIGHTREC_REG_RT_MASK	LIGHTREC_REG_RT(0x3)
#define LIGHTREC_FLAGS_GET_RT(x) \
	(((x) & LIGHTREC_REG_RT_MASK) >> LIGHTREC_REG_RT_LSB)

#define LIGHTREC_REG_RD_LSB	30
#define LIGHTREC_REG_RD(x)	((x) << LIGHTREC_REG_RD_LSB)
#define LIGHTREC_REG_RD_MASK	LIGHTREC_REG_RD(0x3)
#define LIGHTREC_FLAGS_GET_RD(x) \
	(((x) & LIGHTREC_REG_RD_MASK) >> LIGHTREC_REG_RD_LSB)

#define LIGHTREC_REG_NOOP	0x0
#define LIGHTREC_REG_UNLOAD	0x1
#define LIGHTREC_REG_DISCARD	0x2
#define LIGHTREC_REG_CLEAN	0x3

struct block;

enum standard_opcodes {
	OP_SPECIAL		= 0x00,
	OP_REGIMM		= 0x01,
	OP_J			= 0x02,
	OP_JAL			= 0x03,
	OP_BEQ			= 0x04,
	OP_BNE			= 0x05,
	OP_BLEZ			= 0x06,
	OP_BGTZ			= 0x07,
	OP_ADDI			= 0x08,
	OP_ADDIU		= 0x09,
	OP_SLTI			= 0x0a,
	OP_SLTIU		= 0x0b,
	OP_ANDI			= 0x0c,
	OP_ORI			= 0x0d,
	OP_XORI			= 0x0e,
	OP_LUI			= 0x0f,
	OP_CP0			= 0x10,
	OP_CP2			= 0x12,
	OP_LB			= 0x20,
	OP_LH			= 0x21,
	OP_LWL			= 0x22,
	OP_LW			= 0x23,
	OP_LBU			= 0x24,
	OP_LHU			= 0x25,
	OP_LWR			= 0x26,
	OP_SB			= 0x28,
	OP_SH			= 0x29,
	OP_SWL			= 0x2a,
	OP_SW			= 0x2b,
	OP_SWR			= 0x2e,
	OP_LWC2			= 0x32,
	OP_SWC2			= 0x3a,

	OP_META			= 0x3c,

	OP_META_MULT2		= 0x19,
	OP_META_MULTU2		= 0x1a,
};

enum special_opcodes {
	OP_SPECIAL_SLL		= 0x00,
	OP_SPECIAL_SRL		= 0x02,
	OP_SPECIAL_SRA		= 0x03,
	OP_SPECIAL_SLLV		= 0x04,
	OP_SPECIAL_SRLV		= 0x06,
	OP_SPECIAL_SRAV		= 0x07,
	OP_SPECIAL_JR		= 0x08,
	OP_SPECIAL_JALR		= 0x09,
	OP_SPECIAL_SYSCALL	= 0x0c,
	OP_SPECIAL_BREAK	= 0x0d,
	OP_SPECIAL_MFHI		= 0x10,
	OP_SPECIAL_MTHI		= 0x11,
	OP_SPECIAL_MFLO		= 0x12,
	OP_SPECIAL_MTLO		= 0x13,
	OP_SPECIAL_MULT		= 0x18,
	OP_SPECIAL_MULTU	= 0x19,
	OP_SPECIAL_DIV		= 0x1a,
	OP_SPECIAL_DIVU		= 0x1b,
	OP_SPECIAL_ADD		= 0x20,
	OP_SPECIAL_ADDU		= 0x21,
	OP_SPECIAL_SUB		= 0x22,
	OP_SPECIAL_SUBU		= 0x23,
	OP_SPECIAL_AND		= 0x24,
	OP_SPECIAL_OR		= 0x25,
	OP_SPECIAL_XOR		= 0x26,
	OP_SPECIAL_NOR		= 0x27,
	OP_SPECIAL_SLT		= 0x2a,
	OP_SPECIAL_SLTU		= 0x2b,
};

enum regimm_opcodes {
	OP_REGIMM_BLTZ		= 0x00,
	OP_REGIMM_BGEZ		= 0x01,
	OP_REGIMM_BLTZAL	= 0x10,
	OP_REGIMM_BGEZAL	= 0x11,
};

enum cp0_opcodes {
	OP_CP0_MFC0		= 0x00,
	OP_CP0_CFC0		= 0x02,
	OP_CP0_MTC0		= 0x04,
	OP_CP0_CTC0		= 0x06,
	OP_CP0_RFE		= 0x10,
};

enum cp2_opcodes {
	OP_CP2_BASIC		= 0x00,
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

enum cp2_basic_opcodes {
	OP_CP2_BASIC_MFC2	= 0x00,
	OP_CP2_BASIC_CFC2	= 0x02,
	OP_CP2_BASIC_MTC2	= 0x04,
	OP_CP2_BASIC_CTC2	= 0x06,
};

enum meta_opcodes {
	OP_META_MOV		= 0x00,

	OP_META_EXTC		= 0x01,
	OP_META_EXTS		= 0x02,

	OP_META_COM		= 0x03,
};

struct opcode_r {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	u32 zero :6;
	u32 rs   :5;
	u32 rt   :5;
	u32 rd   :5;
	u32 imm  :5;
	u32 op   :6;
#else
	u32 op   :6;
	u32 imm  :5;
	u32 rd   :5;
	u32 rt   :5;
	u32 rs   :5;
	u32 zero :6;
#endif
} __packed;

struct opcode_i {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	u32 op  :6;
	u32 rs  :5;
	u32 rt  :5;
	u32 imm :16;
#else
	u32 imm :16;
	u32 rt  :5;
	u32 rs  :5;
	u32 op  :6;
#endif
} __packed;

struct opcode_j {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	u32 op  :6;
	u32 imm :26;
#else
	u32 imm :26;
	u32 op  :6;
#endif
} __packed;

struct opcode_m {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	u32 meta :6;
	u32 rs   :5;
	u32 rt   :5;
	u32 rd   :5;
	u32 imm  :6;
	u32 op   :5;
#else
	u32 op   :5;
	u32 imm  :6;
	u32 rd   :5;
	u32 rt   :5;
	u32 rs   :5;
	u32 meta :6;
#endif
};

union code {
	/* Keep in sync with struct opcode */
	u32 opcode;
	struct opcode_r r;
	struct opcode_i i;
	struct opcode_j j;
	struct opcode_m m;
};

struct opcode {
	/* Keep this union at the first position */
	union {
		union code c;

		/* Keep in sync with union code */
		u32 opcode;
		struct opcode_r r;
		struct opcode_i i;
		struct opcode_j j;
		struct opcode_m m;
	};
	u32 flags;
};

struct opcode_list {
	u16 nb_ops;
	struct opcode ops[];
};

void lightrec_print_disassembly(const struct block *block, const u32 *code);

static inline _Bool op_flag_no_ds(u32 flags)
{
	return OPT_SWITCH_DELAY_SLOTS && (flags & LIGHTREC_NO_DS);
}

static inline _Bool op_flag_sync(u32 flags)
{
	return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_SYNC);
}

static inline _Bool op_flag_smc(u32 flags)
{
	return OPT_FLAG_IO && (flags & LIGHTREC_SMC);
}

static inline _Bool op_flag_no_invalidate(u32 flags)
{
	return OPT_FLAG_IO && (flags & LIGHTREC_NO_INVALIDATE);
}

static inline _Bool op_flag_no_mask(u32 flags)
{
	return OPT_FLAG_IO && (flags & LIGHTREC_NO_MASK);
}

static inline _Bool op_flag_load_delay(u32 flags)
{
	return OPT_HANDLE_LOAD_DELAYS && (flags & LIGHTREC_LOAD_DELAY);
}

static inline _Bool op_flag_emulate_branch(u32 flags)
{
	return OPT_DETECT_IMPOSSIBLE_BRANCHES &&
		(flags & LIGHTREC_EMULATE_BRANCH);
}

static inline _Bool op_flag_local_branch(u32 flags)
{
	return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_LOCAL_BRANCH);
}

static inline _Bool op_flag_no_lo(u32 flags)
{
	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_LO);
}

static inline _Bool op_flag_no_hi(u32 flags)
{
	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_HI);
}

static inline _Bool op_flag_no_div_check(u32 flags)
{
	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_DIV_CHECK);
}

#endif /* __DISASSEMBLER_H__ */
Commit	Line	Data
98fa08a5	1	/* SPDX-License-Identifier: LGPL-2.1-or-later */
d16005f8	2	/*
98fa08a5	3	* Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
d16005f8 PC	4	*/
	5
	6	#ifndef __DISASSEMBLER_H__
	7	#define __DISASSEMBLER_H__
	8
	9	#include "debug.h"
	10	#include "lightrec.h"
03535202	11	#include "lightrec-config.h"
d16005f8 PC	12
	13	#ifndef __packed
	14	#define __packed __attribute__((packed))
	15	#endif
	16
98fa08a5 PC	17	#define BIT(x) (1ULL << (x))
	18
	19	/* Flags for all opcodes */
	20	#define LIGHTREC_NO_DS BIT(0)
03535202	21	#define LIGHTREC_SYNC BIT(1)
98fa08a5	22
684432ad PC	23	/* Flags for LUI, ORI, ADDIU */
	24	#define LIGHTREC_MOVI BIT(2)
	25
98fa08a5	26	/* Flags for load/store opcodes */
03535202 PC	27	#define LIGHTREC_SMC BIT(2)
	28	#define LIGHTREC_NO_INVALIDATE BIT(3)
	29	#define LIGHTREC_NO_MASK BIT(4)
cb72ea13	30	#define LIGHTREC_LOAD_DELAY BIT(5)
22eee2ac PC	31
22eee2ac PC	32	/* I/O mode for load/store opcodes */
cb72ea13	33	#define LIGHTREC_IO_MODE_LSB 6
22eee2ac PC	34	#define LIGHTREC_IO_MODE(x) ((x) << LIGHTREC_IO_MODE_LSB)
	35	#define LIGHTREC_IO_UNKNOWN 0x0
	36	#define LIGHTREC_IO_DIRECT 0x1
	37	#define LIGHTREC_IO_HW 0x2
	38	#define LIGHTREC_IO_RAM 0x3
	39	#define LIGHTREC_IO_BIOS 0x4
	40	#define LIGHTREC_IO_SCRATCH 0x5
ba3814c1	41	#define LIGHTREC_IO_DIRECT_HW 0x6
22eee2ac PC	42	#define LIGHTREC_IO_MASK LIGHTREC_IO_MODE(0x7)
	43	#define LIGHTREC_FLAGS_GET_IO_MODE(x) \
	44	(((x) & LIGHTREC_IO_MASK) >> LIGHTREC_IO_MODE_LSB)
98fa08a5 PC	45
98fa08a5 PC	46	/* Flags for branches */
03535202 PC	47	#define LIGHTREC_EMULATE_BRANCH BIT(2)
03535202 PC	48	#define LIGHTREC_LOCAL_BRANCH BIT(3)
98fa08a5 PC	49
98fa08a5 PC	50	/* Flags for div/mult opcodes */
03535202 PC	51	#define LIGHTREC_NO_LO BIT(2)
	52	#define LIGHTREC_NO_HI BIT(3)
	53	#define LIGHTREC_NO_DIV_CHECK BIT(4)
	54
	55	#define LIGHTREC_REG_RS_LSB 26
	56	#define LIGHTREC_REG_RS(x) ((x) << LIGHTREC_REG_RS_LSB)
	57	#define LIGHTREC_REG_RS_MASK LIGHTREC_REG_RS(0x3)
	58	#define LIGHTREC_FLAGS_GET_RS(x) \
	59	(((x) & LIGHTREC_REG_RS_MASK) >> LIGHTREC_REG_RS_LSB)
	60
	61	#define LIGHTREC_REG_RT_LSB 28
	62	#define LIGHTREC_REG_RT(x) ((x) << LIGHTREC_REG_RT_LSB)
	63	#define LIGHTREC_REG_RT_MASK LIGHTREC_REG_RT(0x3)
	64	#define LIGHTREC_FLAGS_GET_RT(x) \
	65	(((x) & LIGHTREC_REG_RT_MASK) >> LIGHTREC_REG_RT_LSB)
	66
	67	#define LIGHTREC_REG_RD_LSB 30
	68	#define LIGHTREC_REG_RD(x) ((x) << LIGHTREC_REG_RD_LSB)
	69	#define LIGHTREC_REG_RD_MASK LIGHTREC_REG_RD(0x3)
	70	#define LIGHTREC_FLAGS_GET_RD(x) \
	71	(((x) & LIGHTREC_REG_RD_MASK) >> LIGHTREC_REG_RD_LSB)
	72
	73	#define LIGHTREC_REG_NOOP 0x0
	74	#define LIGHTREC_REG_UNLOAD 0x1
	75	#define LIGHTREC_REG_DISCARD 0x2
	76	#define LIGHTREC_REG_CLEAN 0x3
d16005f8 PC	77
	78	struct block;
	79
	80	enum standard_opcodes {
	81	OP_SPECIAL = 0x00,
	82	OP_REGIMM = 0x01,
	83	OP_J = 0x02,
	84	OP_JAL = 0x03,
	85	OP_BEQ = 0x04,
	86	OP_BNE = 0x05,
	87	OP_BLEZ = 0x06,
	88	OP_BGTZ = 0x07,
	89	OP_ADDI = 0x08,
	90	OP_ADDIU = 0x09,
	91	OP_SLTI = 0x0a,
	92	OP_SLTIU = 0x0b,
	93	OP_ANDI = 0x0c,
	94	OP_ORI = 0x0d,
	95	OP_XORI = 0x0e,
	96	OP_LUI = 0x0f,
	97	OP_CP0 = 0x10,
	98	OP_CP2 = 0x12,
	99	OP_LB = 0x20,
	100	OP_LH = 0x21,
	101	OP_LWL = 0x22,
	102	OP_LW = 0x23,
	103	OP_LBU = 0x24,
	104	OP_LHU = 0x25,
	105	OP_LWR = 0x26,
	106	OP_SB = 0x28,
	107	OP_SH = 0x29,
	108	OP_SWL = 0x2a,
	109	OP_SW = 0x2b,
	110	OP_SWR = 0x2e,
	111	OP_LWC2 = 0x32,
	112	OP_SWC2 = 0x3a,
	113
e26c79a8	114	OP_META = 0x3c,
ba3814c1 PC	115
	116	OP_META_MULT2 = 0x19,
	117	OP_META_MULTU2 = 0x1a,
d16005f8 PC	118	};
	119
	120	enum special_opcodes {
	121	OP_SPECIAL_SLL = 0x00,
	122	OP_SPECIAL_SRL = 0x02,
	123	OP_SPECIAL_SRA = 0x03,
	124	OP_SPECIAL_SLLV = 0x04,
	125	OP_SPECIAL_SRLV = 0x06,
	126	OP_SPECIAL_SRAV = 0x07,
	127	OP_SPECIAL_JR = 0x08,
	128	OP_SPECIAL_JALR = 0x09,
	129	OP_SPECIAL_SYSCALL = 0x0c,
	130	OP_SPECIAL_BREAK = 0x0d,
	131	OP_SPECIAL_MFHI = 0x10,
	132	OP_SPECIAL_MTHI = 0x11,
	133	OP_SPECIAL_MFLO = 0x12,
	134	OP_SPECIAL_MTLO = 0x13,
	135	OP_SPECIAL_MULT = 0x18,
	136	OP_SPECIAL_MULTU = 0x19,
	137	OP_SPECIAL_DIV = 0x1a,
	138	OP_SPECIAL_DIVU = 0x1b,
	139	OP_SPECIAL_ADD = 0x20,
	140	OP_SPECIAL_ADDU = 0x21,
	141	OP_SPECIAL_SUB = 0x22,
	142	OP_SPECIAL_SUBU = 0x23,
	143	OP_SPECIAL_AND = 0x24,
	144	OP_SPECIAL_OR = 0x25,
	145	OP_SPECIAL_XOR = 0x26,
	146	OP_SPECIAL_NOR = 0x27,
	147	OP_SPECIAL_SLT = 0x2a,
	148	OP_SPECIAL_SLTU = 0x2b,
	149	};
	150
	151	enum regimm_opcodes {
	152	OP_REGIMM_BLTZ = 0x00,
	153	OP_REGIMM_BGEZ = 0x01,
	154	OP_REGIMM_BLTZAL = 0x10,
	155	OP_REGIMM_BGEZAL = 0x11,
	156	};
	157
	158	enum cp0_opcodes {
	159	OP_CP0_MFC0 = 0x00,
	160	OP_CP0_CFC0 = 0x02,
	161	OP_CP0_MTC0 = 0x04,
	162	OP_CP0_CTC0 = 0x06,
	163	OP_CP0_RFE = 0x10,
	164	};
	165
	166	enum cp2_opcodes {
	167	OP_CP2_BASIC = 0x00,
ba3814c1 PC	168	OP_CP2_RTPS = 0x01,
	169	OP_CP2_NCLIP = 0x06,
	170	OP_CP2_OP = 0x0c,
	171	OP_CP2_DPCS = 0x10,
	172	OP_CP2_INTPL = 0x11,
	173	OP_CP2_MVMVA = 0x12,
	174	OP_CP2_NCDS = 0x13,
	175	OP_CP2_CDP = 0x14,
	176	OP_CP2_NCDT = 0x16,
	177	OP_CP2_NCCS = 0x1b,
	178	OP_CP2_CC = 0x1c,
	179	OP_CP2_NCS = 0x1e,
	180	OP_CP2_NCT = 0x20,
	181	OP_CP2_SQR = 0x28,
	182	OP_CP2_DCPL = 0x29,
	183	OP_CP2_DPCT = 0x2a,
	184	OP_CP2_AVSZ3 = 0x2d,
	185	OP_CP2_AVSZ4 = 0x2e,
	186	OP_CP2_RTPT = 0x30,
	187	OP_CP2_GPF = 0x3d,
	188	OP_CP2_GPL = 0x3e,
	189	OP_CP2_NCCT = 0x3f,
d16005f8 PC	190	};
	191
	192	enum cp2_basic_opcodes {
	193	OP_CP2_BASIC_MFC2 = 0x00,
	194	OP_CP2_BASIC_CFC2 = 0x02,
	195	OP_CP2_BASIC_MTC2 = 0x04,
	196	OP_CP2_BASIC_CTC2 = 0x06,
	197	};
	198
cb72ea13 PC	199	enum meta_opcodes {
	200	OP_META_MOV = 0x00,
	201
	202	OP_META_EXTC = 0x01,
	203	OP_META_EXTS = 0x02,
	204
	205	OP_META_COM = 0x03,
	206	};
	207
d16005f8 PC	208	struct opcode_r {
	209	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	210	u32 zero :6;
	211	u32 rs :5;
	212	u32 rt :5;
	213	u32 rd :5;
	214	u32 imm :5;
	215	u32 op :6;
	216	#else
	217	u32 op :6;
	218	u32 imm :5;
	219	u32 rd :5;
	220	u32 rt :5;
	221	u32 rs :5;
	222	u32 zero :6;
	223	#endif
	224	} __packed;
	225
	226	struct opcode_i {
	227	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	228	u32 op :6;
	229	u32 rs :5;
	230	u32 rt :5;
	231	u32 imm :16;
	232	#else
	233	u32 imm :16;
	234	u32 rt :5;
	235	u32 rs :5;
	236	u32 op :6;
	237	#endif
	238	} __packed;
	239
	240	struct opcode_j {
	241	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	242	u32 op :6;
	243	u32 imm :26;
	244	#else
	245	u32 imm :26;
	246	u32 op :6;
	247	#endif
	248	} __packed;
	249
cb72ea13 PC	250	struct opcode_m {
	251	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	252	u32 meta :6;
	253	u32 rs :5;
	254	u32 rt :5;
	255	u32 rd :5;
	256	u32 imm :6;
	257	u32 op :5;
	258	#else
	259	u32 op :5;
	260	u32 imm :6;
	261	u32 rd :5;
	262	u32 rt :5;
	263	u32 rs :5;
	264	u32 meta :6;
	265	#endif
	266	};
	267
d16005f8 PC	268	union code {
	269	/* Keep in sync with struct opcode */
	270	u32 opcode;
	271	struct opcode_r r;
	272	struct opcode_i i;
	273	struct opcode_j j;
cb72ea13	274	struct opcode_m m;
d16005f8 PC	275	};
	276
	277	struct opcode {
	278	/* Keep this union at the first position */
	279	union {
	280	union code c;
	281
	282	/* Keep in sync with union code */
	283	u32 opcode;
	284	struct opcode_r r;
	285	struct opcode_i i;
	286	struct opcode_j j;
cb72ea13	287	struct opcode_m m;
d16005f8	288	};
03535202	289	u32 flags;
d16005f8 PC	290	};
d16005f8 PC	291
ba3814c1 PC	292	struct opcode_list {
	293	u16 nb_ops;
	294	struct opcode ops[];
	295	};
	296
98fa08a5	297	void lightrec_print_disassembly(const struct block block, const u32 code);
d16005f8	298
03535202 PC	299	static inline _Bool op_flag_no_ds(u32 flags)
	300	{
	301	return OPT_SWITCH_DELAY_SLOTS && (flags & LIGHTREC_NO_DS);
	302	}
	303
	304	static inline _Bool op_flag_sync(u32 flags)
	305	{
	306	return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_SYNC);
	307	}
	308
	309	static inline _Bool op_flag_smc(u32 flags)
	310	{
cb72ea13	311	return OPT_FLAG_IO && (flags & LIGHTREC_SMC);
03535202 PC	312	}
	313
	314	static inline _Bool op_flag_no_invalidate(u32 flags)
	315	{
cb72ea13	316	return OPT_FLAG_IO && (flags & LIGHTREC_NO_INVALIDATE);
03535202 PC	317	}
	318
	319	static inline _Bool op_flag_no_mask(u32 flags)
	320	{
	321	return OPT_FLAG_IO && (flags & LIGHTREC_NO_MASK);
	322	}
	323
cb72ea13 PC	324	static inline _Bool op_flag_load_delay(u32 flags)
	325	{
	326	return OPT_HANDLE_LOAD_DELAYS && (flags & LIGHTREC_LOAD_DELAY);
	327	}
	328
03535202 PC	329	static inline _Bool op_flag_emulate_branch(u32 flags)
	330	{
	331	return OPT_DETECT_IMPOSSIBLE_BRANCHES &&
	332	(flags & LIGHTREC_EMULATE_BRANCH);
	333	}
	334
	335	static inline _Bool op_flag_local_branch(u32 flags)
	336	{
	337	return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_LOCAL_BRANCH);
	338	}
	339
	340	static inline _Bool op_flag_no_lo(u32 flags)
	341	{
	342	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_LO);
	343	}
	344
	345	static inline _Bool op_flag_no_hi(u32 flags)
	346	{
	347	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_HI);
	348	}
	349
	350	static inline _Bool op_flag_no_div_check(u32 flags)
	351	{
	352	return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_DIV_CHECK);
	353	}
	354
d16005f8	355	#endif /* __DISASSEMBLER_H__ */