Commit | Line | Data |
---|---|---|
b37c639e JW |
1 | .text |
2 | .arm | |
3 | .balign 4 | |
4 | ||
5 | .func ctr_clear_cache_kernel | |
6 | ctr_clear_cache_kernel: | |
7 | cpsid aif | |
8 | mov r0, #0 | |
9 | mcr p15, 0, r0, c7, c10, 0 @ Clean entire data cache | |
10 | mcr p15, 0, r0, c7, c10, 5 @ Data Memory Barrier | |
11 | mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire instruction cache / Flush BTB | |
12 | mcr p15, 0, r0, c7, c10, 4 @ Data Sync Barrier | |
13 | bx lr | |
14 | .endfunc | |
15 | ||
16 | @@ Clear the entire data cache / invalidate the instruction cache. Uses | |
17 | @@ Rosalina svcCustomBackdoor to avoid svcBackdoor stack corruption | |
18 | @@ during interrupts. | |
19 | .global ctr_clear_cache | |
20 | .func ctr_clear_cache | |
21 | ctr_clear_cache: | |
22 | ldr r0, =ctr_clear_cache_kernel | |
23 | svc 0x80 @ svcCustomBackdoor | |
24 | bx lr | |
25 | .endfunc |