55b0eeea |
1 | /* |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2009-2011 |
3 | * |
4 | * This work is licensed under the terms of the GNU GPLv2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
9 | #include <stdlib.h> |
10 | #include <string.h> |
11 | #include <sys/types.h> |
12 | #include <sys/stat.h> |
13 | #include <fcntl.h> |
14 | #include <sys/ioctl.h> |
15 | #include <unistd.h> |
16 | #include <linux/fb.h> |
17 | #include <sys/mman.h> |
18 | |
19 | #include "common/input.h" |
20 | #include "common/menu.h" |
21 | #include "warm/warm.h" |
22 | #include "plugin_lib.h" |
23 | #include "cspace.h" |
24 | #include "main.h" |
25 | #include "menu.h" |
26 | #include "plat.h" |
27 | |
28 | static int fbdev = -1, memdev = -1, battdev = -1; |
29 | static volatile unsigned short *memregs; |
30 | static volatile unsigned int *memregl; |
31 | static void *fb_vaddrs[2]; |
32 | static unsigned int fb_paddrs[2]; |
33 | static int fb_work_buf; |
34 | static int cpu_clock_allowed; |
35 | |
36 | static unsigned short *psx_vram; |
37 | static unsigned int psx_vram_padds[512]; |
38 | static int psx_offset, psx_step, psx_width, psx_height, psx_bpp; |
39 | static int fb_offset; |
40 | |
41 | // TODO: get rid of this |
42 | struct vout_fbdev; |
43 | struct vout_fbdev *layer_fb; |
44 | int g_layer_x, g_layer_y, g_layer_w, g_layer_h; |
45 | |
46 | int omap_enable_layer(int enabled) |
47 | { |
48 | return 0; |
49 | } |
50 | |
51 | static void *fb_flip(void) |
52 | { |
53 | memregl[0x406C>>2] = fb_paddrs[fb_work_buf]; |
54 | memregl[0x4058>>2] |= 0x10; |
55 | fb_work_buf ^= 1; |
56 | return fb_vaddrs[fb_work_buf]; |
57 | } |
58 | |
59 | static void pollux_changemode(int bpp, int is_bgr) |
60 | { |
61 | int code = 0, bytes = 2; |
62 | unsigned int r; |
63 | |
64 | printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb"); |
65 | |
66 | memregl[0x4004>>2] = 0x00ef013f; |
67 | memregl[0x4000>>2] |= 1 << 3; |
68 | |
69 | switch (bpp) |
70 | { |
71 | case 8: |
72 | code = 0x443a; |
73 | bytes = 1; |
74 | break; |
75 | case 16: |
76 | code = is_bgr ? 0xc342 : 0x4432; |
77 | bytes = 2; |
78 | break; |
79 | case 24: |
80 | code = is_bgr ? 0xc653 : 0x4653; |
81 | bytes = 3; |
82 | break; |
83 | default: |
84 | printf("unhandled bpp request: %d\n", bpp); |
85 | return; |
86 | } |
87 | |
88 | memregl[0x405c>>2] = bytes; |
89 | memregl[0x4060>>2] = 320 * bytes; |
90 | |
91 | r = memregl[0x4058>>2]; |
92 | r = (r & 0xffff) | (code << 16) | 0x10; |
93 | memregl[0x4058>>2] = r; |
94 | } |
95 | |
96 | /* note: both PLLs are programmed the same way, |
97 | * the databook incorrectly states that PLL1 differs */ |
98 | static int decode_pll(unsigned int reg) |
99 | { |
100 | long long v; |
101 | int p, m, s; |
102 | |
103 | p = (reg >> 18) & 0x3f; |
104 | m = (reg >> 8) & 0x3ff; |
105 | s = reg & 0xff; |
106 | |
107 | if (p == 0) |
108 | p = 1; |
109 | |
110 | v = 27000000; // master clock |
111 | v = v * m / (p << s); |
112 | return v; |
113 | } |
114 | |
115 | int plat_cpu_clock_get(void) |
116 | { |
117 | return decode_pll(memregl[0xf004>>2]) / 1000000; |
118 | } |
119 | |
120 | int plat_cpu_clock_apply(int mhz) |
121 | { |
122 | int adiv, mdiv, pdiv, sdiv = 0; |
123 | int i, vf000, vf004; |
124 | |
125 | if (!cpu_clock_allowed) |
126 | return -1; |
127 | if (mhz == plat_cpu_clock_get()) |
128 | return 0; |
129 | |
130 | // m = MDIV, p = PDIV, s = SDIV |
131 | #define SYS_CLK_FREQ 27 |
132 | pdiv = 9; |
133 | mdiv = (mhz * pdiv) / SYS_CLK_FREQ; |
134 | if (mdiv & ~0x3ff) |
135 | return -1; |
136 | vf004 = (pdiv<<18) | (mdiv<<8) | sdiv; |
137 | |
138 | // attempt to keep the AHB divider close to 250, but not higher |
139 | for (adiv = 1; mhz / adiv > 250; adiv++) |
140 | ; |
141 | |
142 | vf000 = memregl[0xf000>>2]; |
143 | vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6); |
144 | memregl[0xf000>>2] = vf000; |
145 | memregl[0xf004>>2] = vf004; |
146 | memregl[0xf07c>>2] |= 0x8000; |
147 | for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) |
148 | ; |
149 | |
150 | printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv); |
151 | |
152 | // stupid pll share hack - must restart audio |
153 | extern long SPUopen(void); |
154 | extern long SPUclose(void); |
155 | SPUclose(); |
156 | SPUopen(); |
157 | |
158 | return 0; |
159 | } |
160 | |
161 | int plat_get_bat_capacity(void) |
162 | { |
163 | unsigned short magic_val = 0; |
164 | |
165 | if (battdev < 0) |
166 | return -1; |
167 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
168 | return -1; |
169 | switch (magic_val) { |
170 | default: |
171 | case 1: return 100; |
172 | case 2: return 66; |
173 | case 3: return 40; |
174 | case 4: return 0; |
175 | } |
176 | } |
177 | |
178 | #define TIMER_BASE3 0x1980 |
179 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
180 | |
181 | static __attribute__((unused)) unsigned int timer_get(void) |
182 | { |
183 | TIMER_REG(0x08) |= 0x48; /* run timer, latch value */ |
184 | return TIMER_REG(0); |
185 | } |
186 | |
187 | static void timer_cleanup(void) |
188 | { |
189 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
190 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
191 | TIMER_REG(0x00) = 0; /* clear counter */ |
192 | TIMER_REG(0x40) = 0; /* clocks off */ |
193 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
194 | } |
195 | |
196 | void plat_video_menu_enter(int is_rom_loaded) |
197 | { |
198 | if (pl_vout_buf != NULL) { |
199 | if (psx_bpp == 16) |
200 | // have to do rgb conversion for menu bg |
201 | bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2); |
202 | else |
203 | memset(pl_vout_buf, 0, 320*240*2); |
204 | } |
205 | |
206 | pollux_changemode(16, 0); |
207 | } |
208 | |
209 | void plat_video_menu_begin(void) |
210 | { |
211 | } |
212 | |
213 | void plat_video_menu_end(void) |
214 | { |
215 | g_menuscreen_ptr = fb_flip(); |
216 | } |
217 | |
218 | void plat_video_menu_leave(void) |
219 | { |
220 | pollux_changemode(psx_bpp, 1); |
221 | if (psx_vram == NULL) { |
222 | fprintf(stderr, "GPU plugin did not provide vram\n"); |
223 | exit(1); |
224 | } |
225 | |
226 | in_set_config_int(in_name_to_id("evdev:pollux-analog"), |
227 | IN_CFG_ABS_DEAD_ZONE, analog_deadzone); |
228 | } |
229 | |
230 | static void pl_vout_set_raw_vram(void *vram) |
231 | { |
232 | int i; |
233 | |
234 | psx_vram = vram; |
235 | |
236 | if (vram == NULL) |
237 | return; |
238 | |
239 | if ((long)psx_vram & 0x7ff) |
240 | fprintf(stderr, "GPU plugin did not align vram\n"); |
241 | |
242 | for (i = 0; i < 512; i++) { |
243 | psx_vram[i * 1024] = 0; // touch |
244 | psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]); |
245 | } |
246 | } |
247 | |
248 | static void *pl_vout_set_mode(int w, int h, int bpp) |
249 | { |
250 | static int old_w, old_h, old_bpp; |
251 | int fboff_w, fboff_h; |
252 | int poff_w, poff_h; |
253 | |
254 | if (!w || !h || !bpp || (w == old_w && h == old_h && bpp == old_bpp)) |
255 | return NULL; |
256 | |
257 | printf("psx mode: %dx%d@%d\n", w, h, bpp); |
258 | |
259 | psx_step = 1; |
260 | if (h > 256) { |
261 | psx_step = 2; |
262 | h /= 2; |
263 | } |
264 | |
265 | poff_w = poff_h = 0; |
266 | if (w > 320) { |
267 | poff_w = w / 2 - 320/2; |
268 | w = 320; |
269 | } |
270 | if (h > 240) { |
271 | poff_h = h / 2 - 240/2; |
272 | h = 240; |
273 | } |
274 | fboff_w = 320/2 - w / 2; |
275 | fboff_h = 240/2 - h / 2; |
276 | |
277 | psx_offset = poff_h * 1024 + poff_w; |
278 | psx_width = w; |
279 | psx_height = h; |
280 | psx_bpp = bpp; |
281 | fb_offset = fboff_h * 320 + fboff_w; |
282 | |
283 | pollux_changemode(bpp, 1); |
284 | |
285 | return NULL; |
286 | } |
287 | |
288 | static void spend_cycles(int loops) |
289 | { |
290 | asm volatile ( |
291 | " mov r0,%0 ;\n" |
292 | "0: subs r0,r0,#1 ;\n" |
293 | " bgt 0b" |
294 | :: "r" (loops) : "cc", "r0"); |
295 | } |
296 | |
297 | #define DMA_BASE6 0x0300 |
298 | #define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2] |
299 | |
300 | /* this takes ~1.5ms, while ldm/stm ~1.95ms */ |
301 | static void raw_flip_dma(int x, int y) |
302 | { |
303 | unsigned int dst = fb_paddrs[fb_work_buf] + fb_offset * psx_bpp / 8; |
304 | int spsx_line = y + (psx_offset >> 10); |
305 | int spsx_offset = (x + psx_offset) & 0x3f8; |
306 | int dst_stride = 320 * psx_bpp / 8; |
307 | int len = psx_width * psx_bpp / 8; |
308 | //unsigned int st = timer_get(); |
309 | int i; |
310 | |
311 | warm_cache_op_all(WOP_D_CLEAN); |
312 | |
313 | dst &= ~7; |
314 | len &= ~7; |
315 | |
316 | if (DMA_REG(0x0c) & 0x90000) { |
317 | printf("already runnig DMA?\n"); |
318 | DMA_REG(0x0c) = 0x100000; |
319 | } |
320 | if ((DMA_REG(0x2c) & 0x0f) < 5) { |
321 | printf("DMA queue busy?\n"); |
322 | DMA_REG(0x24) = 1; |
323 | } |
324 | |
325 | for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) { |
326 | while ((DMA_REG(0x2c) & 0x0f) < 4) |
327 | spend_cycles(10); |
328 | |
329 | // XXX: it seems we must always set all regs, what is autoincrement there for? |
330 | DMA_REG(0x20) = 1; // queue wait cmd |
331 | DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src |
332 | DMA_REG(0x14) = dst; // DMA dst |
333 | DMA_REG(0x18) = len - 1; // len |
334 | DMA_REG(0x1c) = 0x80000; // go |
335 | } |
336 | |
337 | //printf("d %d\n", timer_get() - st); |
338 | |
339 | if (psx_bpp == 16) { |
340 | pl_vout_buf = g_menuscreen_ptr; |
341 | pl_print_hud(psx_width, psx_height); |
342 | } |
343 | |
344 | g_menuscreen_ptr = fb_flip(); |
345 | pl_flip_cnt++; |
346 | } |
347 | |
348 | static void raw_flip_soft(int x, int y) |
349 | { |
350 | unsigned short *src = psx_vram + y * 1024 + x + psx_offset; |
351 | unsigned char *dst = (unsigned char *)g_menuscreen_ptr + fb_offset * psx_bpp / 8; |
352 | int dst_stride = 320 * psx_bpp / 8; |
353 | int len = psx_width * psx_bpp / 8; |
354 | //unsigned int st = timer_get(); |
355 | int i; |
356 | |
357 | for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride) |
358 | memcpy(dst, src, len); |
359 | |
360 | //printf("s %d\n", timer_get() - st); |
361 | |
362 | if (psx_bpp == 16) { |
363 | pl_vout_buf = g_menuscreen_ptr; |
364 | pl_print_hud(psx_width, psx_height); |
365 | } |
366 | |
367 | g_menuscreen_ptr = fb_flip(); |
368 | pl_flip_cnt++; |
369 | } |
370 | |
371 | void plat_init(void) |
372 | { |
373 | const char *main_fb_name = "/dev/fb0"; |
374 | struct fb_fix_screeninfo fbfix; |
375 | int rate, timer_div, timer_div2; |
376 | int fbdev, ret, warm_ret; |
377 | |
378 | memdev = open("/dev/mem", O_RDWR); |
379 | if (memdev == -1) { |
380 | perror("open(/dev/mem) failed"); |
381 | exit(1); |
382 | } |
383 | |
384 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); |
385 | if (memregs == MAP_FAILED) { |
386 | perror("mmap(memregs) failed"); |
387 | exit(1); |
388 | } |
389 | memregl = (volatile void *)memregs; |
390 | |
391 | fbdev = open(main_fb_name, O_RDWR); |
392 | if (fbdev == -1) { |
393 | fprintf(stderr, "%s: ", main_fb_name); |
394 | perror("open"); |
395 | exit(1); |
396 | } |
397 | |
398 | ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix); |
399 | if (ret == -1) { |
400 | perror("ioctl(fbdev) failed"); |
401 | exit(1); |
402 | } |
403 | printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start); |
404 | fb_paddrs[0] = fbfix.smem_start; |
405 | fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp |
406 | |
407 | fb_vaddrs[0] = mmap(0, 320*240*2*4, PROT_READ|PROT_WRITE, |
408 | MAP_SHARED, memdev, fb_paddrs[0]); |
409 | if (fb_vaddrs[0] == MAP_FAILED) { |
410 | perror("mmap(fb_vaddrs) failed"); |
411 | exit(1); |
412 | } |
413 | fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4; |
414 | |
415 | pollux_changemode(16, 0); |
416 | g_menuscreen_w = 320; |
417 | g_menuscreen_h = 240; |
418 | g_menuscreen_ptr = fb_flip(); |
419 | |
420 | g_menubg_ptr = calloc(320*240*2, 1); |
421 | if (g_menubg_ptr == NULL) { |
422 | fprintf(stderr, "OOM\n"); |
423 | exit(1); |
424 | } |
425 | |
426 | warm_ret = warm_init(); |
427 | warm_change_cb_upper(WCB_B_BIT, 1); |
428 | |
429 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
430 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
431 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
432 | cpu_clock_allowed = 1; |
433 | else { |
434 | cpu_clock_allowed = 0; |
435 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
436 | memregl[0xf000>>2]); |
437 | } |
438 | |
439 | /* find what PLL1 runs at, for the timer */ |
440 | rate = decode_pll(memregl[0xf008>>2]); |
441 | printf("PLL1 @ %dHz\n", rate); |
442 | |
443 | /* setup timer */ |
444 | timer_div = (rate + 500000) / 1000000; |
445 | timer_div2 = 0; |
446 | while (timer_div > 256) { |
447 | timer_div /= 2; |
448 | timer_div2++; |
449 | } |
450 | if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) { |
451 | int timer_rate = (rate >> timer_div2) / timer_div; |
452 | if (TIMER_REG(0x08) & 8) { |
453 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
454 | timer_cleanup(); |
455 | } |
456 | if (timer_rate != 1000000) |
457 | fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000); |
458 | |
459 | timer_div2 = (timer_div2 + 3) & 3; |
460 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */ |
461 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
462 | TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */ |
463 | } |
464 | else |
465 | fprintf(stderr, "warning: could not make use of timer\n"); |
466 | |
467 | /* setup DMA */ |
468 | DMA_REG(0x0c) = 0x20000; // pending IRQ clear |
469 | |
470 | battdev = open("/dev/pollux_batt", O_RDONLY); |
471 | if (battdev < 0) |
472 | perror("Warning: could't open pollux_batt"); |
473 | |
474 | // hmh |
475 | plat_rescan_inputs(); |
476 | |
477 | pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft; |
478 | pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode; |
479 | pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram; |
480 | |
481 | psx_width = 320; |
482 | psx_height = 240; |
483 | psx_bpp = 16; |
484 | } |
485 | |
486 | void plat_finish(void) |
487 | { |
488 | warm_finish(); |
489 | timer_cleanup(); |
490 | pollux_changemode(16, 0); |
491 | fb_work_buf = 0; |
492 | fb_flip(); |
493 | |
494 | if (battdev >= 0) |
495 | close(battdev); |
496 | munmap(fb_vaddrs[0], 320*240*2*2); |
497 | close(fbdev); |
498 | munmap((void *)memregs, 0x20000); |
499 | close(memdev); |
500 | } |
501 | |
502 | void in_update_analogs(void) |
503 | { |
504 | } |
505 | |
506 | /* Caanoo stuff, perhaps move later */ |
507 | #include <linux/input.h> |
508 | |
509 | struct in_default_bind in_evdev_defbinds[] = { |
510 | { KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP }, |
511 | { KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN }, |
512 | { KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT }, |
513 | { KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT }, |
514 | { BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE }, |
515 | { BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS }, |
516 | { BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE }, |
517 | { BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE }, |
518 | { BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START }, |
519 | { BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT }, |
520 | { BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 }, |
521 | { BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 }, |
522 | { BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU }, |
523 | { 0, 0, 0 }, |
524 | }; |
525 | |
526 | static const char * const caanoo_keys[KEY_MAX + 1] = { |
527 | [0 ... KEY_MAX] = NULL, |
528 | [KEY_UP] = "Up", |
529 | [KEY_LEFT] = "Left", |
530 | [KEY_RIGHT] = "Right", |
531 | [KEY_DOWN] = "Down", |
532 | [BTN_TRIGGER] = "A", |
533 | [BTN_THUMB] = "X", |
534 | [BTN_THUMB2] = "B", |
535 | [BTN_TOP] = "Y", |
536 | [BTN_TOP2] = "L", |
537 | [BTN_PINKIE] = "R", |
538 | [BTN_BASE] = "Home", |
539 | [BTN_BASE2] = "Lock", |
540 | [BTN_BASE3] = "I", |
541 | [BTN_BASE4] = "II", |
542 | [BTN_BASE5] = "Push", |
543 | }; |
544 | |
545 | int plat_rescan_inputs(void) |
546 | { |
547 | in_probe(); |
548 | in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES, |
549 | caanoo_keys, sizeof(caanoo_keys)); |
550 | return 0; |
551 | } |