2823a4c8 |
1 | #ifndef GP2X_H |
2 | #define GP2X_H |
3 | |
4 | enum |
5 | { |
6 | GP2X_UP = 1 << 0, |
7 | GP2X_LEFT = 1 << 2, |
8 | GP2X_DOWN = 1 << 4, |
9 | GP2X_RIGHT = 1 << 6, |
10 | GP2X_START = 1 << 8, |
11 | GP2X_SELECT = 1 << 9, |
12 | GP2X_L = 1 << 10, |
13 | GP2X_R = 1 << 11, |
14 | GP2X_A = 1 << 12, |
15 | GP2X_B = 1 << 13, |
16 | GP2X_X = 1 << 14, |
17 | GP2X_Y = 1 << 15, |
18 | GP2X_VOL_DOWN = 1 << 22, |
19 | GP2X_VOL_UP = 1 << 23, |
20 | GP2X_PUSH = 1 << 27 |
21 | }; |
22 | |
23 | |
24 | extern u32 gpsp_gp2x_dev_audio; |
25 | extern u32 gpsp_gp2x_dev; |
26 | extern volatile u16 *gpsp_gp2x_memregs; |
27 | extern volatile u32 *gpsp_gp2x_memregl; |
28 | |
29 | void gp2x_sound_volume(u32 volume_up); |
30 | void gp2x_quit(); |
31 | |
32 | // call this at first |
33 | void cpuctrl_init(void); |
34 | void save_system_regs(void); |
35 | void cpuctrl_deinit(void); |
36 | void set_display_clock_div(unsigned div); |
37 | |
38 | void set_FCLK(u32 MHZ); |
39 | // 0 to 7 divider (freq = FCLK / (1 + div)) |
40 | void set_920_Div(u16 div); |
41 | void set_DCLK_Div(u16 div); |
42 | |
43 | void Disable_940(void); |
44 | void gp2x_video_wait_vsync(void); |
45 | unsigned short get_920_Div(); |
46 | void set_940_Div(u16 div); |
47 | |
48 | s32 gp2x_load_mmuhack(); |
49 | |
50 | #endif |