[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <lightrec.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>

#if P_HAVE_MMAP
#include <sys/mman.h>
#endif

#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../psxhle.h"
#include "../psxevents.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

void* code_buffer;

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

extern u32 lightrec_hacks;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
{
	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
	lightrec_reset_cycle_count(state, 0);
}

static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
	s32 cycles_left = next_interupt - psxRegs.cycle;

	if (block_stepping || cycles_left <= 0 || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else {
		lightrec_set_target_cycle_count(state, cycles_left * 1024);
	}
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite8(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite16(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite32(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead8(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead16(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead32(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x8000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},

	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	[PSX_MAP_PPORT_MIRROR] = {
		.pc = 0x1fa00000,
		.length = 0x10000,
		.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	},

	/* Code buffer */
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	if (is_write && size != 32) {
		// force32 so must go through handlers
		if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
			return false;
		if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
			return false;
	}

	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

#if defined(HW_DOL) || defined(HW_RVL)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	extern void DCFlushRange(void *ptr, u32 len);
	extern void ICInvalidateRange(void *ptr, u32 len);

	DCFlushRange(ptr, len);
	ICInvalidateRange(ptr, len);
}
#elif defined(HW_WUP)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
}
#endif

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
	.code_inv = lightrec_code_inv,
#endif
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		code_buffer = mmap(0, CODE_BUFFER_SIZE,
				   PROT_EXEC | PROT_READ | PROT_WRITE,
				   MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
		if (code_buffer == MAP_FAILED)
			return -ENOMEM;
#else
		code_buffer = malloc(CODE_BUFFER_SIZE);
		if (!code_buffer)
			return -ENOMEM;
#endif
	}

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	}

	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags, cycles_pcsx;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);
	if (!block_only && stop)
		return;

	cycles_pcsx = next_interupt - psxRegs.cycle;
	assert((s32)cycles_pcsx > 0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		cycles_pcsx = 0;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		u32 cycles_lightrec = cycles_pcsx * 1024;
		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      cycles_lightrec);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, cycles_lightrec);
		}

		lightrec_tansition_to_pcsx(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
		if (flags & LIGHTREC_EXIT_BREAK)
			psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
		else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
			u32 op = intFakeFetch(psxRegs.pc);
			u32 hlec = op & 0x03ffffff;
			if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
				lightrec_plugin_sync_regs_to_pcsx(0);
				psxHLEt[hlec]();
				lightrec_plugin_sync_regs_from_pcsx(0);
			}
			else
				psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
		}
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if ((addr == 0 && size == UINT32_MAX)
	    || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		/* non-null 'data' means this is HLE related sync */
		lightrec_plugin_sync_regs_to_pcsx(data == NULL);
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx(data == NULL);
		if (data == NULL)
			lightrec_invalidate_all(lightrec_state);
		break;
	}
}

static void lightrec_plugin_apply_config()
{
	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
		? Config.cycle_multiplier_override : Config.cycle_multiplier;
	assert(cycle_mult);

	lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		munmap(code_buffer, CODE_BUFFER_SIZE);
#else
		free(code_buffer);
#endif
	}
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A

	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
}

static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
6f1edc3c	1	#include <lightrec.h>
82183d4c	2	#include <errno.h>
6f1edc3c PC	3	#include <stdbool.h>
	4	#include <stdio.h>
	5	#include <unistd.h>
	6	#include <signal.h>
c174cf6a	7	#include <assert.h>
6f1edc3c	8
c4f51fd8 PC	9	#if P_HAVE_MMAP
	10	#include <sys/mman.h>
	11	#endif
	12
6f1edc3c PC	13	#include "../cdrom.h"
	14	#include "../gpu.h"
	15	#include "../gte.h"
	16	#include "../mdec.h"
	17	#include "../psxdma.h"
	18	#include "../psxhw.h"
	19	#include "../psxmem.h"
	20	#include "../r3000a.h"
f2100c3d	21	#include "../psxinterpreter.h"
ec4baa7d	22	#include "../psxhle.h"
c6a249e3	23	#include "../psxevents.h"
6f1edc3c PC	24
	25	#include "../frontend/main.h"
	26
f8548105	27	#include "mem.h"
70939d49	28	#include "plugin.h"
f8548105	29
46a38bda	30	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	31	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	32	#endif
	33
6f1edc3c PC	34	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	35
	36	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	37	# define LE32TOH(x) __builtin_bswap32(x)
	38	# define HTOLE32(x) __builtin_bswap32(x)
	39	# define LE16TOH(x) __builtin_bswap16(x)
	40	# define HTOLE16(x) __builtin_bswap16(x)
	41	#else
	42	# define LE32TOH(x) (x)
	43	# define HTOLE32(x) (x)
	44	# define LE16TOH(x) (x)
	45	# define HTOLE16(x) (x)
	46	#endif
	47
	48	#ifdef __GNUC__
	49	# define likely(x) __builtin_expect(!!(x),1)
	50	# define unlikely(x) __builtin_expect(!!(x),0)
	51	#else
	52	# define likely(x) (x)
	53	# define unlikely(x) (x)
	54	#endif
	55
630b122b	56	psxRegisters psxRegs;
	57	Rcnt rcnts[4];
	58
82183d4c PC	59	void* code_buffer;
82183d4c PC	60
6f1edc3c PC	61	static struct lightrec_state *lightrec_state;
	62
	63	static char *name = "retroarch.exe";
	64
	65	static bool use_lightrec_interpreter;
6b02f240	66	static bool use_pcsx_interpreter;
6c62131f	67	static bool block_stepping;
6f1edc3c	68
8bccdd17 PC	69	extern u32 lightrec_hacks;
8bccdd17 PC	70
6f1edc3c PC	71	enum my_cp2_opcodes {
	72	OP_CP2_RTPS = 0x01,
	73	OP_CP2_NCLIP = 0x06,
	74	OP_CP2_OP = 0x0c,
	75	OP_CP2_DPCS = 0x10,
	76	OP_CP2_INTPL = 0x11,
	77	OP_CP2_MVMVA = 0x12,
	78	OP_CP2_NCDS = 0x13,
	79	OP_CP2_CDP = 0x14,
	80	OP_CP2_NCDT = 0x16,
	81	OP_CP2_NCCS = 0x1b,
	82	OP_CP2_CC = 0x1c,
	83	OP_CP2_NCS = 0x1e,
	84	OP_CP2_NCT = 0x20,
	85	OP_CP2_SQR = 0x28,
	86	OP_CP2_DCPL = 0x29,
	87	OP_CP2_DPCT = 0x2a,
	88	OP_CP2_AVSZ3 = 0x2d,
	89	OP_CP2_AVSZ4 = 0x2e,
	90	OP_CP2_RTPT = 0x30,
	91	OP_CP2_GPF = 0x3d,
	92	OP_CP2_GPL = 0x3e,
	93	OP_CP2_NCCT = 0x3f,
	94	};
	95
	96	static void (cp2_ops[])(struct psxCP2Regs ) = {
	97	[OP_CP2_RTPS] = gteRTPS,
	98	[OP_CP2_RTPS] = gteRTPS,
	99	[OP_CP2_NCLIP] = gteNCLIP,
	100	[OP_CP2_OP] = gteOP,
	101	[OP_CP2_DPCS] = gteDPCS,
	102	[OP_CP2_INTPL] = gteINTPL,
	103	[OP_CP2_MVMVA] = gteMVMVA,
	104	[OP_CP2_NCDS] = gteNCDS,
	105	[OP_CP2_CDP] = gteCDP,
	106	[OP_CP2_NCDT] = gteNCDT,
	107	[OP_CP2_NCCS] = gteNCCS,
	108	[OP_CP2_CC] = gteCC,
	109	[OP_CP2_NCS] = gteNCS,
	110	[OP_CP2_NCT] = gteNCT,
	111	[OP_CP2_SQR] = gteSQR,
	112	[OP_CP2_DCPL] = gteDCPL,
	113	[OP_CP2_DPCT] = gteDPCT,
	114	[OP_CP2_AVSZ3] = gteAVSZ3,
	115	[OP_CP2_AVSZ4] = gteAVSZ4,
	116	[OP_CP2_RTPT] = gteRTPT,
	117	[OP_CP2_GPF] = gteGPF,
	118	[OP_CP2_GPL] = gteGPL,
	119	[OP_CP2_NCCT] = gteNCCT,
	120	};
	121
	122	static char cache_buf[64 * 1024];
	123
0733c3ab	124	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	125	{
0733c3ab	126	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	127
0733c3ab	128	psxRegs.code = func;
6f1edc3c	129
0733c3ab PC	130	if (unlikely(!cp2_ops[func & 0x3f])) {
	131	fprintf(stderr, "Invalid CP2 function %u\n", func);
	132	} else {
	133	/* This works because regs->cp2c comes right after regs->cp2d,
	134	* so it can be cast to a pcsxCP2Regs pointer. */
	135	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	136	}
6f1edc3c PC	137	}
6f1edc3c PC	138
2bf88032 PC	139	static bool has_interrupt(void)
2bf88032 PC	140	{
6ce0b00a PC	141	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	142
2bf88032	143	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	144	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	145	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	146	}
2bf88032 PC	147
c174cf6a	148	static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
c174cf6a	149	{
b45c3e27	150	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
c174cf6a	151	lightrec_reset_cycle_count(state, 0);
	152	}
	153
	154	static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
	155	{
	156	s32 cycles_left = next_interupt - psxRegs.cycle;
	157
	158	if (block_stepping \|\| cycles_left <= 0 \|\| has_interrupt())
2bf88032	159	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
c174cf6a	160	else {
b45c3e27	161	lightrec_set_target_cycle_count(state, cycles_left * 1024);
c174cf6a	162	}
f4f9f2a4 PC	163	}
f4f9f2a4 PC	164
6b02f240	165	static void hw_write_byte(struct lightrec_state *state,
909bfa63	166	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	167	{
c174cf6a	168	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	169
6f1edc3c PC	170	psxHwWrite8(mem, val);
6f1edc3c	171
c174cf6a	172	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	173	}
6f1edc3c PC	174
6b02f240	175	static void hw_write_half(struct lightrec_state *state,
909bfa63	176	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	177	{
c174cf6a	178	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	179
6f1edc3c PC	180	psxHwWrite16(mem, val);
6f1edc3c	181
c174cf6a	182	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	183	}
6f1edc3c PC	184
6b02f240	185	static void hw_write_word(struct lightrec_state *state,
6b02f240	186	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	187	{
c174cf6a	188	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	189
6f1edc3c PC	190	psxHwWrite32(mem, val);
6f1edc3c	191
c174cf6a	192	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	193	}
6f1edc3c PC	194
6b02f240	195	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	196	{
	197	u8 val;
	198
c174cf6a	199	lightrec_tansition_to_pcsx(state);
6f1edc3c	200
6f1edc3c	201	val = psxHwRead8(mem);
f4f9f2a4	202
c174cf6a	203	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	204
	205	return val;
	206	}
	207
6b02f240	208	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	209	u32 op, void *host, u32 mem)
6f1edc3c PC	210	{
	211	u16 val;
	212
c174cf6a	213	lightrec_tansition_to_pcsx(state);
6f1edc3c	214
6f1edc3c	215	val = psxHwRead16(mem);
f4f9f2a4	216
c174cf6a	217	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	218
	219	return val;
	220	}
	221
6b02f240	222	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	223	u32 op, void *host, u32 mem)
6f1edc3c PC	224	{
	225	u32 val;
	226
c174cf6a	227	lightrec_tansition_to_pcsx(state);
6f1edc3c	228
6f1edc3c	229	val = psxHwRead32(mem);
f4f9f2a4	230
c174cf6a	231	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	232
	233	return val;
	234	}
	235
	236	static struct lightrec_mem_map_ops hw_regs_ops = {
	237	.sb = hw_write_byte,
	238	.sh = hw_write_half,
	239	.sw = hw_write_word,
	240	.lb = hw_read_byte,
	241	.lh = hw_read_half,
	242	.lw = hw_read_word,
	243	};
	244
	245	static u32 cache_ctrl;
	246
6b02f240	247	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	248	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	249	{
	250	cache_ctrl = val;
	251	}
	252
6b02f240	253	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	254	u32 op, void *host, u32 mem)
6f1edc3c PC	255	{
	256	return cache_ctrl;
	257	}
	258
	259	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	260	.sw = cache_ctrl_write_word,
	261	.lw = cache_ctrl_read_word,
	262	};
	263
	264	static struct lightrec_mem_map lightrec_map[] = {
	265	[PSX_MAP_KERNEL_USER_RAM] = {
	266	/* Kernel and user memory */
	267	.pc = 0x00000000,
	268	.length = 0x200000,
	269	},
	270	[PSX_MAP_BIOS] = {
	271	/* BIOS */
	272	.pc = 0x1fc00000,
	273	.length = 0x80000,
	274	},
	275	[PSX_MAP_SCRATCH_PAD] = {
	276	/* Scratch pad */
	277	.pc = 0x1f800000,
	278	.length = 0x400,
	279	},
	280	[PSX_MAP_PARALLEL_PORT] = {
	281	/* Parallel port */
	282	.pc = 0x1f000000,
	283	.length = 0x10000,
	284	},
	285	[PSX_MAP_HW_REGISTERS] = {
	286	/* Hardware registers */
	287	.pc = 0x1f801000,
82d04936	288	.length = 0x8000,
6f1edc3c PC	289	.ops = &hw_regs_ops,
	290	},
	291	[PSX_MAP_CACHE_CONTROL] = {
	292	/* Cache control */
	293	.pc = 0x5ffe0130,
	294	.length = 4,
	295	.ops = &cache_ctrl_ops,
	296	},
	297
	298	/* Mirrors of the kernel/user memory */
	299	[PSX_MAP_MIRROR1] = {
	300	.pc = 0x00200000,
	301	.length = 0x200000,
	302	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	303	},
	304	[PSX_MAP_MIRROR2] = {
	305	.pc = 0x00400000,
	306	.length = 0x200000,
	307	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	308	},
	309	[PSX_MAP_MIRROR3] = {
	310	.pc = 0x00600000,
	311	.length = 0x200000,
	312	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	313	},
6e394614 PC	314
	315	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	316	[PSX_MAP_PPORT_MIRROR] = {
	317	.pc = 0x1fa00000,
	318	.length = 0x10000,
	319	.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	320	},
	321
	322	/* Code buffer */
f8548105 PC	323	[PSX_MAP_CODE_BUFFER] = {
	324	.length = CODE_BUFFER_SIZE,
	325	},
6f1edc3c PC	326	};
6f1edc3c PC	327
0733c3ab PC	328	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	329	{
	330	if (enable)
	331	memcpy(psxM, cache_buf, sizeof(cache_buf));
	332	else
	333	memcpy(cache_buf, psxM, sizeof(cache_buf));
	334	}
	335
ba3814c1 PC	336	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
ba3814c1 PC	337	{
ab206b0c	338	if (is_write && size != 32) {
	339	// force32 so must go through handlers
	340	if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
	341	return false;
	342	if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
	343	return false;
	344	}
	345
ba3814c1 PC	346	switch (size) {
	347	case 8:
	348	switch (kaddr) {
	349	case 0x1f801040:
	350	case 0x1f801050:
	351	case 0x1f801800:
	352	case 0x1f801801:
	353	case 0x1f801802:
	354	case 0x1f801803:
	355	return false;
	356	default:
	357	return true;
	358	}
	359	case 16:
	360	switch (kaddr) {
	361	case 0x1f801040:
	362	case 0x1f801044:
	363	case 0x1f801048:
	364	case 0x1f80104a:
	365	case 0x1f80104e:
	366	case 0x1f801050:
	367	case 0x1f801054:
	368	case 0x1f80105a:
	369	case 0x1f80105e:
	370	case 0x1f801100:
	371	case 0x1f801104:
	372	case 0x1f801108:
	373	case 0x1f801110:
	374	case 0x1f801114:
	375	case 0x1f801118:
	376	case 0x1f801120:
	377	case 0x1f801124:
	378	case 0x1f801128:
	379	return false;
	380	case 0x1f801070:
	381	case 0x1f801074:
	382	return !is_write;
	383	default:
cdfa3536	384	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	385	}
	386	default:
	387	switch (kaddr) {
	388	case 0x1f801040:
	389	case 0x1f801050:
	390	case 0x1f801100:
	391	case 0x1f801104:
	392	case 0x1f801108:
	393	case 0x1f801110:
	394	case 0x1f801114:
	395	case 0x1f801118:
	396	case 0x1f801120:
	397	case 0x1f801124:
	398	case 0x1f801128:
	399	case 0x1f801810:
	400	case 0x1f801814:
	401	case 0x1f801820:
	402	case 0x1f801824:
	403	return false;
	404	case 0x1f801070:
	405	case 0x1f801074:
	406	case 0x1f801088:
	407	case 0x1f801098:
	408	case 0x1f8010a8:
	409	case 0x1f8010b8:
	410	case 0x1f8010c8:
	411	case 0x1f8010e8:
	412	case 0x1f8010f4:
	413	return !is_write;
	414	default:
	415	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	416	}
	417	}
	418	}
	419
323bb280 AL	420	#if defined(HW_DOL) \|\| defined(HW_RVL)
	421	static void lightrec_code_inv(void *ptr, uint32_t len)
	422	{
	423	extern void DCFlushRange(void *ptr, u32 len);
	424	extern void ICInvalidateRange(void *ptr, u32 len);
	425
	426	DCFlushRange(ptr, len);
	427	ICInvalidateRange(ptr, len);
	428	}
	429	#elif defined(HW_WUP)
	430	static void lightrec_code_inv(void *ptr, uint32_t len)
	431	{
	432	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
	433	}
	434	#endif
	435
6f1edc3c	436	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	437	.cop2_op = cop2_op,
0733c3ab PC	438	.enable_ram = lightrec_enable_ram,
ba3814c1	439	.hw_direct = lightrec_can_hw_direct,
323bb280 AL	440	#if defined(HW_DOL) \|\| defined(HW_RVL) \|\| defined(HW_WUP)
	441	.code_inv = lightrec_code_inv,
	442	#endif
6f1edc3c PC	443	};
	444
	445	static int lightrec_plugin_init(void)
	446	{
	447	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	448	lightrec_map[PSX_MAP_BIOS].address = psxR;
	449	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	450	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	451	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	452
82183d4c	453	if (!LIGHTREC_CUSTOM_MAP) {
c4f51fd8 PC	454	#if P_HAVE_MMAP
	455	code_buffer = mmap(0, CODE_BUFFER_SIZE,
	456	PROT_EXEC \| PROT_READ \| PROT_WRITE,
	457	MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	458	if (code_buffer == MAP_FAILED)
	459	return -ENOMEM;
	460	#else
82183d4c PC	461	code_buffer = malloc(CODE_BUFFER_SIZE);
	462	if (!code_buffer)
	463	return -ENOMEM;
c4f51fd8	464	#endif
82183d4c PC	465	}
82183d4c PC	466
479d58cf PC	467	if (LIGHTREC_CUSTOM_MAP) {
	468	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	469	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	470	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	471	}
	472
82183d4c PC	473	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
82183d4c PC	474
6f1edc3c	475	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	476
	477	lightrec_state = lightrec_init(name,
	478	lightrec_map, ARRAY_SIZE(lightrec_map),
	479	&lightrec_ops);
	480
9361a5aa EC	481	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	482	// (uintptr_t) psxM,
	483	// (uintptr_t) psxP,
	484	// (uintptr_t) psxR,
	485	// (uintptr_t) psxH);
6f1edc3c PC	486
	487	#ifndef _WIN32
	488	signal(SIGPIPE, exit);
	489	#endif
	490	return 0;
	491	}
	492
ec4baa7d	493	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
	494	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
	495
d0abba5d	496	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	497	{
6c62131f	498	struct lightrec_registers *regs;
c174cf6a	499	u32 flags, cycles_pcsx;
6f1edc3c	500
6c62131f	501	regs = lightrec_get_registers(lightrec_state);
6c62131f	502	gen_interupt((psxCP0Regs *)regs->cp0);
403a6290	503	if (!block_only && stop)
	504	return;
	505
c174cf6a	506	cycles_pcsx = next_interupt - psxRegs.cycle;
c174cf6a	507	assert((s32)cycles_pcsx > 0);
2bf88032	508
ba3814c1	509	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	510	block_stepping = block_only;
d0abba5d	511	if (block_only)
c174cf6a	512	cycles_pcsx = 0;
ba3814c1	513
6b02f240	514	if (use_pcsx_interpreter) {
f2100c3d	515	intExecuteBlock(0);
6b02f240	516	} else {
b45c3e27	517	u32 cycles_lightrec = cycles_pcsx * 1024;
ba3814c1	518	if (unlikely(use_lightrec_interpreter)) {
6b02f240	519	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1	520	psxRegs.pc,
c174cf6a	521	cycles_lightrec);
ba3814c1	522	} else {
2bf88032	523	psxRegs.pc = lightrec_execute(lightrec_state,
c174cf6a	524	psxRegs.pc, cycles_lightrec);
ba3814c1	525	}
6f1edc3c	526
c174cf6a	527	lightrec_tansition_to_pcsx(lightrec_state);
6f1edc3c	528
6b02f240	529	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	530
6b02f240	531	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	532	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	533	psxRegs.cycle);
	534	exit(1);
	535	}
6f1edc3c	536
6b02f240	537	if (flags & LIGHTREC_EXIT_SYSCALL)
ec4baa7d	538	psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
a95fc05a PC	539	if (flags & LIGHTREC_EXIT_BREAK)
a95fc05a PC	540	psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
ec4baa7d	541	else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
	542	u32 op = intFakeFetch(psxRegs.pc);
	543	u32 hlec = op & 0x03ffffff;
	544	if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
	545	lightrec_plugin_sync_regs_to_pcsx(0);
	546	psxHLEt[hlec]();
	547	lightrec_plugin_sync_regs_from_pcsx(0);
	548	}
	549	else
	550	psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
	551	}
2bf88032	552	}
6f1edc3c	553
6c62131f	554	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	555	/* Handle software interrupts */
6c62131f	556	regs->cp0[13] &= ~0x7c;
6c62131f	557	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	558	}
6f1edc3c PC	559	}
	560
	561	static void lightrec_plugin_execute(void)
	562	{
6f1edc3c	563	while (!stop)
d0abba5d	564	lightrec_plugin_execute_internal(false);
d0abba5d	565	}
d0abba5d	566
f3bc907d	567	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	568	{
d0abba5d	569	lightrec_plugin_execute_internal(true);
6f1edc3c PC	570	}
	571
	572	static void lightrec_plugin_clear(u32 addr, u32 size)
	573	{
0e481d53 PC	574	if ((addr == 0 && size == UINT32_MAX)
0e481d53 PC	575	\|\| (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
8c9468f1 ZC	576	lightrec_invalidate_all(lightrec_state);
	577	else
	578	/* size * 4: PCSX uses DMA units */
	579	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	580	}
6f1edc3c PC	581
20196899	582	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	583	{
7a811716	584	switch (note)
7a811716	585	{
20196899	586	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	587	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	588	/* not used, lightrec calls lightrec_enable_ram() instead */
	589	break;
	590	case R3000ACPU_NOTIFY_BEFORE_SAVE:
ec4baa7d	591	/* non-null 'data' means this is HLE related sync */
ec4baa7d	592	lightrec_plugin_sync_regs_to_pcsx(data == NULL);
20196899	593	break;
20196899	594	case R3000ACPU_NOTIFY_AFTER_LOAD:
ec4baa7d	595	lightrec_plugin_sync_regs_from_pcsx(data == NULL);
	596	if (data == NULL)
	597	lightrec_invalidate_all(lightrec_state);
20196899	598	break;
20196899	599	}
7a811716	600	}
630b122b	601
	602	static void lightrec_plugin_apply_config()
	603	{
c174cf6a	604	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
	605	? Config.cycle_multiplier_override : Config.cycle_multiplier;
	606	assert(cycle_mult);
b45c3e27 PC	607
b45c3e27 PC	608	lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
630b122b	609	}
7a811716	610
6f1edc3c PC	611	static void lightrec_plugin_shutdown(void)
	612	{
	613	lightrec_destroy(lightrec_state);
82183d4c	614
c4f51fd8 PC	615	if (!LIGHTREC_CUSTOM_MAP) {
	616	#if P_HAVE_MMAP
	617	munmap(code_buffer, CODE_BUFFER_SIZE);
	618	#else
82183d4c	619	free(code_buffer);
c4f51fd8 PC	620	#endif
c4f51fd8 PC	621	}
6f1edc3c PC	622	}
	623
	624	static void lightrec_plugin_reset(void)
	625	{
0733c3ab PC	626	struct lightrec_registers *regs;
0733c3ab PC	627
0733c3ab PC	628	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	629
03535202 PC	630	/* Invalidate all blocks */
	631	lightrec_invalidate_all(lightrec_state);
	632
	633	/* Reset registers */
	634	memset(regs, 0, sizeof(*regs));
	635
0733c3ab PC	636	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	637	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6c307d2d PC	638
6c307d2d PC	639	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
6f1edc3c PC	640	}
6f1edc3c PC	641
ec4baa7d	642	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
6962f770 PC	643	{
	644	struct lightrec_registers *regs;
	645
	646	regs = lightrec_get_registers(lightrec_state);
6962f770	647	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
ec4baa7d	648	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	649	if (need_cp2)
	650	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	651	}
6962f770 PC	652
ec4baa7d	653	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
6962f770 PC	654	{
	655	struct lightrec_registers *regs;
	656
	657	regs = lightrec_get_registers(lightrec_state);
6962f770	658	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
ec4baa7d	659	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	660	if (need_cp2)
	661	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	662	}
6962f770 PC	663
6f1edc3c PC	664	R3000Acpu psxRec =
	665	{
	666	lightrec_plugin_init,
	667	lightrec_plugin_reset,
	668	lightrec_plugin_execute,
	669	lightrec_plugin_execute_block,
	670	lightrec_plugin_clear,
7a811716	671	lightrec_plugin_notify,
630b122b	672	lightrec_plugin_apply_config,
6f1edc3c PC	673	lightrec_plugin_shutdown,
6f1edc3c PC	674	};