[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <lightrec.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>

#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../new_dynarec/events.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_restore_state(struct lightrec_state *state)
{
	lightrec_reset_cycle_count(state, psxRegs.cycle);

	if (block_stepping || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else
		lightrec_set_target_cycle_count(state, next_interupt);
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u8 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite8(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u16 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite16(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite32(mem, val);

	lightrec_restore_state(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead8(mem);

	lightrec_restore_state(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead16(mem);

	lightrec_restore_state(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead32(mem);

	lightrec_restore_state(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x2000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
		lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
	}

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

extern void intExecuteBlock();

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		next_interupt = psxRegs.cycle;

	if (use_pcsx_interpreter) {
		intExecuteBlock();
	} else {
		lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);

		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      next_interupt);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, next_interupt);
		}

		psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	extern int stop;

	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(void)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if (addr == 0 && size == UINT32_MAX)
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_sync_regs_to_pcsx(void);
static void lightrec_plugin_sync_regs_from_pcsx(void);

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		lightrec_plugin_sync_regs_to_pcsx();
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx();
		break;
	}
}

static void lightrec_plugin_apply_config()
{
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
}

static void lightrec_plugin_sync_regs_from_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));

	lightrec_invalidate_all(lightrec_state);
}

static void lightrec_plugin_sync_regs_to_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
6f1edc3c PC	1	#include <lightrec.h>
	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
	6
	7	#include "../cdrom.h"
	8	#include "../gpu.h"
	9	#include "../gte.h"
	10	#include "../mdec.h"
	11	#include "../psxdma.h"
	12	#include "../psxhw.h"
	13	#include "../psxmem.h"
	14	#include "../r3000a.h"
6c62131f	15	#include "../new_dynarec/events.h"
6f1edc3c PC	16
	17	#include "../frontend/main.h"
	18
f8548105	19	#include "mem.h"
70939d49	20	#include "plugin.h"
f8548105	21
46a38bda	22	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	23	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	24	#endif
	25
6f1edc3c PC	26	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	27
	28	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	29	# define LE32TOH(x) __builtin_bswap32(x)
	30	# define HTOLE32(x) __builtin_bswap32(x)
	31	# define LE16TOH(x) __builtin_bswap16(x)
	32	# define HTOLE16(x) __builtin_bswap16(x)
	33	#else
	34	# define LE32TOH(x) (x)
	35	# define HTOLE32(x) (x)
	36	# define LE16TOH(x) (x)
	37	# define HTOLE16(x) (x)
	38	#endif
	39
	40	#ifdef __GNUC__
	41	# define likely(x) __builtin_expect(!!(x),1)
	42	# define unlikely(x) __builtin_expect(!!(x),0)
	43	#else
	44	# define likely(x) (x)
	45	# define unlikely(x) (x)
	46	#endif
	47
630b122b	48	psxRegisters psxRegs;
	49	Rcnt rcnts[4];
	50
6f1edc3c PC	51	static struct lightrec_state *lightrec_state;
	52
	53	static char *name = "retroarch.exe";
	54
	55	static bool use_lightrec_interpreter;
6b02f240	56	static bool use_pcsx_interpreter;
6c62131f	57	static bool block_stepping;
6f1edc3c	58
6f1edc3c PC	59	enum my_cp2_opcodes {
	60	OP_CP2_RTPS = 0x01,
	61	OP_CP2_NCLIP = 0x06,
	62	OP_CP2_OP = 0x0c,
	63	OP_CP2_DPCS = 0x10,
	64	OP_CP2_INTPL = 0x11,
	65	OP_CP2_MVMVA = 0x12,
	66	OP_CP2_NCDS = 0x13,
	67	OP_CP2_CDP = 0x14,
	68	OP_CP2_NCDT = 0x16,
	69	OP_CP2_NCCS = 0x1b,
	70	OP_CP2_CC = 0x1c,
	71	OP_CP2_NCS = 0x1e,
	72	OP_CP2_NCT = 0x20,
	73	OP_CP2_SQR = 0x28,
	74	OP_CP2_DCPL = 0x29,
	75	OP_CP2_DPCT = 0x2a,
	76	OP_CP2_AVSZ3 = 0x2d,
	77	OP_CP2_AVSZ4 = 0x2e,
	78	OP_CP2_RTPT = 0x30,
	79	OP_CP2_GPF = 0x3d,
	80	OP_CP2_GPL = 0x3e,
	81	OP_CP2_NCCT = 0x3f,
	82	};
	83
	84	static void (cp2_ops[])(struct psxCP2Regs ) = {
	85	[OP_CP2_RTPS] = gteRTPS,
	86	[OP_CP2_RTPS] = gteRTPS,
	87	[OP_CP2_NCLIP] = gteNCLIP,
	88	[OP_CP2_OP] = gteOP,
	89	[OP_CP2_DPCS] = gteDPCS,
	90	[OP_CP2_INTPL] = gteINTPL,
	91	[OP_CP2_MVMVA] = gteMVMVA,
	92	[OP_CP2_NCDS] = gteNCDS,
	93	[OP_CP2_CDP] = gteCDP,
	94	[OP_CP2_NCDT] = gteNCDT,
	95	[OP_CP2_NCCS] = gteNCCS,
	96	[OP_CP2_CC] = gteCC,
	97	[OP_CP2_NCS] = gteNCS,
	98	[OP_CP2_NCT] = gteNCT,
	99	[OP_CP2_SQR] = gteSQR,
	100	[OP_CP2_DCPL] = gteDCPL,
	101	[OP_CP2_DPCT] = gteDPCT,
	102	[OP_CP2_AVSZ3] = gteAVSZ3,
	103	[OP_CP2_AVSZ4] = gteAVSZ4,
	104	[OP_CP2_RTPT] = gteRTPT,
	105	[OP_CP2_GPF] = gteGPF,
	106	[OP_CP2_GPL] = gteGPL,
	107	[OP_CP2_NCCT] = gteNCCT,
	108	};
	109
	110	static char cache_buf[64 * 1024];
	111
0733c3ab	112	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	113	{
0733c3ab	114	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	115
0733c3ab	116	psxRegs.code = func;
6f1edc3c	117
0733c3ab PC	118	if (unlikely(!cp2_ops[func & 0x3f])) {
	119	fprintf(stderr, "Invalid CP2 function %u\n", func);
	120	} else {
	121	/* This works because regs->cp2c comes right after regs->cp2d,
	122	* so it can be cast to a pcsxCP2Regs pointer. */
	123	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	124	}
6f1edc3c PC	125	}
6f1edc3c PC	126
2bf88032 PC	127	static bool has_interrupt(void)
2bf88032 PC	128	{
6ce0b00a PC	129	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	130
2bf88032	131	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	132	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	133	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	134	}
2bf88032 PC	135
f4f9f2a4 PC	136	static void lightrec_restore_state(struct lightrec_state *state)
	137	{
	138	lightrec_reset_cycle_count(state, psxRegs.cycle);
2bf88032	139
6c62131f	140	if (block_stepping \|\| has_interrupt())
2bf88032 PC	141	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	142	else
	143	lightrec_set_target_cycle_count(state, next_interupt);
f4f9f2a4 PC	144	}
f4f9f2a4 PC	145
6b02f240	146	static void hw_write_byte(struct lightrec_state *state,
6b02f240	147	u32 op, void *host, u32 mem, u8 val)
6f1edc3c PC	148	{
	149	psxRegs.cycle = lightrec_current_cycle_count(state);
	150
	151	psxHwWrite8(mem, val);
6f1edc3c	152
f4f9f2a4	153	lightrec_restore_state(state);
6f1edc3c PC	154	}
6f1edc3c PC	155
6b02f240	156	static void hw_write_half(struct lightrec_state *state,
6b02f240	157	u32 op, void *host, u32 mem, u16 val)
6f1edc3c PC	158	{
	159	psxRegs.cycle = lightrec_current_cycle_count(state);
	160
	161	psxHwWrite16(mem, val);
6f1edc3c	162
f4f9f2a4	163	lightrec_restore_state(state);
6f1edc3c PC	164	}
6f1edc3c PC	165
6b02f240	166	static void hw_write_word(struct lightrec_state *state,
6b02f240	167	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	168	{
	169	psxRegs.cycle = lightrec_current_cycle_count(state);
	170
	171	psxHwWrite32(mem, val);
6f1edc3c	172
f4f9f2a4	173	lightrec_restore_state(state);
6f1edc3c PC	174	}
6f1edc3c PC	175
6b02f240	176	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	177	{
	178	u8 val;
	179
	180	psxRegs.cycle = lightrec_current_cycle_count(state);
	181
6f1edc3c	182	val = psxHwRead8(mem);
f4f9f2a4 PC	183
f4f9f2a4 PC	184	lightrec_restore_state(state);
6f1edc3c PC	185
	186	return val;
	187	}
	188
6b02f240	189	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	190	u32 op, void *host, u32 mem)
6f1edc3c PC	191	{
	192	u16 val;
	193
	194	psxRegs.cycle = lightrec_current_cycle_count(state);
	195
6f1edc3c	196	val = psxHwRead16(mem);
f4f9f2a4 PC	197
f4f9f2a4 PC	198	lightrec_restore_state(state);
6f1edc3c PC	199
	200	return val;
	201	}
	202
6b02f240	203	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	204	u32 op, void *host, u32 mem)
6f1edc3c PC	205	{
	206	u32 val;
	207
	208	psxRegs.cycle = lightrec_current_cycle_count(state);
	209
6f1edc3c	210	val = psxHwRead32(mem);
f4f9f2a4 PC	211
f4f9f2a4 PC	212	lightrec_restore_state(state);
6f1edc3c PC	213
	214	return val;
	215	}
	216
	217	static struct lightrec_mem_map_ops hw_regs_ops = {
	218	.sb = hw_write_byte,
	219	.sh = hw_write_half,
	220	.sw = hw_write_word,
	221	.lb = hw_read_byte,
	222	.lh = hw_read_half,
	223	.lw = hw_read_word,
	224	};
	225
	226	static u32 cache_ctrl;
	227
6b02f240	228	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	229	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	230	{
	231	cache_ctrl = val;
	232	}
	233
6b02f240	234	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	235	u32 op, void *host, u32 mem)
6f1edc3c PC	236	{
	237	return cache_ctrl;
	238	}
	239
	240	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	241	.sw = cache_ctrl_write_word,
	242	.lw = cache_ctrl_read_word,
	243	};
	244
	245	static struct lightrec_mem_map lightrec_map[] = {
	246	[PSX_MAP_KERNEL_USER_RAM] = {
	247	/* Kernel and user memory */
	248	.pc = 0x00000000,
	249	.length = 0x200000,
	250	},
	251	[PSX_MAP_BIOS] = {
	252	/* BIOS */
	253	.pc = 0x1fc00000,
	254	.length = 0x80000,
	255	},
	256	[PSX_MAP_SCRATCH_PAD] = {
	257	/* Scratch pad */
	258	.pc = 0x1f800000,
	259	.length = 0x400,
	260	},
	261	[PSX_MAP_PARALLEL_PORT] = {
	262	/* Parallel port */
	263	.pc = 0x1f000000,
	264	.length = 0x10000,
	265	},
	266	[PSX_MAP_HW_REGISTERS] = {
	267	/* Hardware registers */
	268	.pc = 0x1f801000,
	269	.length = 0x2000,
	270	.ops = &hw_regs_ops,
	271	},
	272	[PSX_MAP_CACHE_CONTROL] = {
	273	/* Cache control */
	274	.pc = 0x5ffe0130,
	275	.length = 4,
	276	.ops = &cache_ctrl_ops,
	277	},
	278
	279	/* Mirrors of the kernel/user memory */
	280	[PSX_MAP_MIRROR1] = {
	281	.pc = 0x00200000,
	282	.length = 0x200000,
	283	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	284	},
	285	[PSX_MAP_MIRROR2] = {
	286	.pc = 0x00400000,
	287	.length = 0x200000,
	288	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	289	},
	290	[PSX_MAP_MIRROR3] = {
	291	.pc = 0x00600000,
	292	.length = 0x200000,
	293	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	294	},
f8548105 PC	295	[PSX_MAP_CODE_BUFFER] = {
	296	.length = CODE_BUFFER_SIZE,
	297	},
6f1edc3c PC	298	};
6f1edc3c PC	299
0733c3ab PC	300	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	301	{
	302	if (enable)
	303	memcpy(psxM, cache_buf, sizeof(cache_buf));
	304	else
	305	memcpy(cache_buf, psxM, sizeof(cache_buf));
	306	}
	307
ba3814c1 PC	308	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
	309	{
	310	switch (size) {
	311	case 8:
	312	switch (kaddr) {
	313	case 0x1f801040:
	314	case 0x1f801050:
	315	case 0x1f801800:
	316	case 0x1f801801:
	317	case 0x1f801802:
	318	case 0x1f801803:
	319	return false;
	320	default:
	321	return true;
	322	}
	323	case 16:
	324	switch (kaddr) {
	325	case 0x1f801040:
	326	case 0x1f801044:
	327	case 0x1f801048:
	328	case 0x1f80104a:
	329	case 0x1f80104e:
	330	case 0x1f801050:
	331	case 0x1f801054:
	332	case 0x1f80105a:
	333	case 0x1f80105e:
	334	case 0x1f801100:
	335	case 0x1f801104:
	336	case 0x1f801108:
	337	case 0x1f801110:
	338	case 0x1f801114:
	339	case 0x1f801118:
	340	case 0x1f801120:
	341	case 0x1f801124:
	342	case 0x1f801128:
	343	return false;
	344	case 0x1f801070:
	345	case 0x1f801074:
	346	return !is_write;
	347	default:
cdfa3536	348	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	349	}
	350	default:
	351	switch (kaddr) {
	352	case 0x1f801040:
	353	case 0x1f801050:
	354	case 0x1f801100:
	355	case 0x1f801104:
	356	case 0x1f801108:
	357	case 0x1f801110:
	358	case 0x1f801114:
	359	case 0x1f801118:
	360	case 0x1f801120:
	361	case 0x1f801124:
	362	case 0x1f801128:
	363	case 0x1f801810:
	364	case 0x1f801814:
	365	case 0x1f801820:
	366	case 0x1f801824:
	367	return false;
	368	case 0x1f801070:
	369	case 0x1f801074:
	370	case 0x1f801088:
	371	case 0x1f801098:
	372	case 0x1f8010a8:
	373	case 0x1f8010b8:
	374	case 0x1f8010c8:
	375	case 0x1f8010e8:
	376	case 0x1f8010f4:
	377	return !is_write;
	378	default:
	379	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	380	}
	381	}
	382	}
	383
6f1edc3c	384	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	385	.cop2_op = cop2_op,
0733c3ab PC	386	.enable_ram = lightrec_enable_ram,
ba3814c1	387	.hw_direct = lightrec_can_hw_direct,
6f1edc3c PC	388	};
	389
	390	static int lightrec_plugin_init(void)
	391	{
	392	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	393	lightrec_map[PSX_MAP_BIOS].address = psxR;
	394	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	395	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	396	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	397
479d58cf PC	398	if (LIGHTREC_CUSTOM_MAP) {
	399	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	400	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	401	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
f8548105	402	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
479d58cf PC	403	}
479d58cf PC	404
6f1edc3c	405	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	406
	407	lightrec_state = lightrec_init(name,
	408	lightrec_map, ARRAY_SIZE(lightrec_map),
	409	&lightrec_ops);
	410
9361a5aa EC	411	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	412	// (uintptr_t) psxM,
	413	// (uintptr_t) psxP,
	414	// (uintptr_t) psxR,
	415	// (uintptr_t) psxH);
6f1edc3c PC	416
	417	#ifndef _WIN32
	418	signal(SIGPIPE, exit);
	419	#endif
	420	return 0;
	421	}
	422
6b02f240	423	extern void intExecuteBlock();
6b02f240	424
d0abba5d	425	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	426	{
6c62131f	427	struct lightrec_registers *regs;
6f1edc3c PC	428	u32 flags;
6f1edc3c PC	429
6c62131f	430	regs = lightrec_get_registers(lightrec_state);
6c62131f	431	gen_interupt((psxCP0Regs *)regs->cp0);
2bf88032	432
ba3814c1	433	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	434	block_stepping = block_only;
d0abba5d	435	if (block_only)
ba3814c1 PC	436	next_interupt = psxRegs.cycle;
ba3814c1 PC	437
6b02f240	438	if (use_pcsx_interpreter) {
	439	intExecuteBlock();
	440	} else {
	441	lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
6f1edc3c	442
ba3814c1	443	if (unlikely(use_lightrec_interpreter)) {
6b02f240	444	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1 PC	445	psxRegs.pc,
	446	next_interupt);
	447	} else {
2bf88032 PC	448	psxRegs.pc = lightrec_execute(lightrec_state,
2bf88032 PC	449	psxRegs.pc, next_interupt);
ba3814c1	450	}
6f1edc3c	451
6b02f240	452	psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
6f1edc3c	453
6b02f240	454	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	455
6b02f240	456	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	457	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	458	psxRegs.cycle);
	459	exit(1);
	460	}
6f1edc3c	461
6b02f240	462	if (flags & LIGHTREC_EXIT_SYSCALL)
6c62131f	463	psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
2bf88032	464	}
6f1edc3c	465
6c62131f	466	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	467	/* Handle software interrupts */
6c62131f	468	regs->cp0[13] &= ~0x7c;
6c62131f	469	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	470	}
6f1edc3c PC	471	}
	472
	473	static void lightrec_plugin_execute(void)
	474	{
	475	extern int stop;
	476
	477	while (!stop)
d0abba5d	478	lightrec_plugin_execute_internal(false);
d0abba5d	479	}
	480
	481	static void lightrec_plugin_execute_block(void)
	482	{
	483	lightrec_plugin_execute_internal(true);
6f1edc3c PC	484	}
	485
	486	static void lightrec_plugin_clear(u32 addr, u32 size)
	487	{
8c9468f1 ZC	488	if (addr == 0 && size == UINT32_MAX)
	489	lightrec_invalidate_all(lightrec_state);
	490	else
	491	/* size * 4: PCSX uses DMA units */
	492	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	493	}
6f1edc3c PC	494
20196899	495	static void lightrec_plugin_sync_regs_to_pcsx(void);
	496	static void lightrec_plugin_sync_regs_from_pcsx(void);
	497
	498	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	499	{
7a811716	500	switch (note)
7a811716	501	{
20196899	502	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	503	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	504	/* not used, lightrec calls lightrec_enable_ram() instead */
	505	break;
	506	case R3000ACPU_NOTIFY_BEFORE_SAVE:
	507	lightrec_plugin_sync_regs_to_pcsx();
	508	break;
	509	case R3000ACPU_NOTIFY_AFTER_LOAD:
	510	lightrec_plugin_sync_regs_from_pcsx();
	511	break;
	512	}
7a811716	513	}
630b122b	514
	515	static void lightrec_plugin_apply_config()
	516	{
	517	}
7a811716	518
6f1edc3c PC	519	static void lightrec_plugin_shutdown(void)
	520	{
	521	lightrec_destroy(lightrec_state);
	522	}
	523
	524	static void lightrec_plugin_reset(void)
	525	{
0733c3ab PC	526	struct lightrec_registers *regs;
0733c3ab PC	527
0733c3ab PC	528	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	529
03535202 PC	530	/* Invalidate all blocks */
	531	lightrec_invalidate_all(lightrec_state);
	532
	533	/* Reset registers */
	534	memset(regs, 0, sizeof(*regs));
	535
0733c3ab PC	536	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	537	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6f1edc3c PC	538	}
6f1edc3c PC	539
20196899	540	static void lightrec_plugin_sync_regs_from_pcsx(void)
6962f770 PC	541	{
	542	struct lightrec_registers *regs;
	543
	544	regs = lightrec_get_registers(lightrec_state);
	545	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	546	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	547	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	548
	549	lightrec_invalidate_all(lightrec_state);
	550	}
	551
20196899	552	static void lightrec_plugin_sync_regs_to_pcsx(void)
6962f770 PC	553	{
	554	struct lightrec_registers *regs;
	555
	556	regs = lightrec_get_registers(lightrec_state);
	557	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	558	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	559	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	560	}
	561
6f1edc3c PC	562	R3000Acpu psxRec =
	563	{
	564	lightrec_plugin_init,
	565	lightrec_plugin_reset,
	566	lightrec_plugin_execute,
	567	lightrec_plugin_execute_block,
	568	lightrec_plugin_clear,
7a811716	569	lightrec_plugin_notify,
630b122b	570	lightrec_plugin_apply_config,
6f1edc3c PC	571	lightrec_plugin_shutdown,
6f1edc3c PC	572	};