[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <lightrec.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>

#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool booting;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_restore_state(struct lightrec_state *state)
{
	lightrec_reset_cycle_count(state, psxRegs.cycle);

	if (booting || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else
		lightrec_set_target_cycle_count(state, next_interupt);
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u8 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite8(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u16 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite16(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite32(mem, val);

	lightrec_restore_state(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead8(mem);

	lightrec_restore_state(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead16(mem);

	lightrec_restore_state(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead32(mem);

	lightrec_restore_state(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x2000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
		lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
	}

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_dump_regs(struct lightrec_state *state)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	if (unlikely(booting))
		memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	psxRegs.CP0.n.Status = regs->cp0[12];
	psxRegs.CP0.n.Cause = regs->cp0[13];
}

static void lightrec_restore_regs(struct lightrec_state *state)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	if (unlikely(booting))
		memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	regs->cp0[12] = psxRegs.CP0.n.Status;
	regs->cp0[13] = psxRegs.CP0.n.Cause;
	regs->cp0[14] = psxRegs.CP0.n.EPC;
}

extern void intExecuteBlock();
extern void gen_interupt();

static void lightrec_plugin_execute_internal(bool block_only)
{
	u32 flags;

	gen_interupt();

	// step during early boot so that 0x80030000 fastboot hack works
	booting = block_only;
	if (block_only)
		next_interupt = psxRegs.cycle;

	if (use_pcsx_interpreter) {
		intExecuteBlock();
	} else {
		lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
		lightrec_restore_regs(lightrec_state);

		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      next_interupt);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, next_interupt);
		}

		psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);

		lightrec_dump_regs(lightrec_state);
		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(0x20, 0);
	}

	if ((psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x300) &&
			(psxRegs.CP0.n.Status & 0x1)) {
		/* Handle software interrupts */
		psxRegs.CP0.n.Cause &= ~0x7c;
		psxException(psxRegs.CP0.n.Cause, 0);
	}
}

static void lightrec_plugin_execute(void)
{
	extern int stop;

	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(void)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if (addr == 0 && size == UINT32_MAX)
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_sync_regs_to_pcsx(void);
static void lightrec_plugin_sync_regs_from_pcsx(void);

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		lightrec_plugin_sync_regs_to_pcsx();
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx();
		break;
	}
}

static void lightrec_plugin_apply_config()
{
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
}

static void lightrec_plugin_sync_regs_from_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));

	lightrec_invalidate_all(lightrec_state);
}

static void lightrec_plugin_sync_regs_to_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
6f1edc3c PC	1	#include <lightrec.h>
	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
	6
	7	#include "../cdrom.h"
	8	#include "../gpu.h"
	9	#include "../gte.h"
	10	#include "../mdec.h"
	11	#include "../psxdma.h"
	12	#include "../psxhw.h"
	13	#include "../psxmem.h"
	14	#include "../r3000a.h"
	15
	16	#include "../frontend/main.h"
	17
f8548105	18	#include "mem.h"
70939d49	19	#include "plugin.h"
f8548105	20
46a38bda	21	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	22	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	23	#endif
	24
6f1edc3c PC	25	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	26
	27	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	28	# define LE32TOH(x) __builtin_bswap32(x)
	29	# define HTOLE32(x) __builtin_bswap32(x)
	30	# define LE16TOH(x) __builtin_bswap16(x)
	31	# define HTOLE16(x) __builtin_bswap16(x)
	32	#else
	33	# define LE32TOH(x) (x)
	34	# define HTOLE32(x) (x)
	35	# define LE16TOH(x) (x)
	36	# define HTOLE16(x) (x)
	37	#endif
	38
	39	#ifdef __GNUC__
	40	# define likely(x) __builtin_expect(!!(x),1)
	41	# define unlikely(x) __builtin_expect(!!(x),0)
	42	#else
	43	# define likely(x) (x)
	44	# define unlikely(x) (x)
	45	#endif
	46
630b122b	47	psxRegisters psxRegs;
	48	Rcnt rcnts[4];
	49
6f1edc3c PC	50	static struct lightrec_state *lightrec_state;
	51
	52	static char *name = "retroarch.exe";
	53
	54	static bool use_lightrec_interpreter;
6b02f240	55	static bool use_pcsx_interpreter;
2bf88032	56	static bool booting;
6f1edc3c	57
6f1edc3c PC	58	enum my_cp2_opcodes {
	59	OP_CP2_RTPS = 0x01,
	60	OP_CP2_NCLIP = 0x06,
	61	OP_CP2_OP = 0x0c,
	62	OP_CP2_DPCS = 0x10,
	63	OP_CP2_INTPL = 0x11,
	64	OP_CP2_MVMVA = 0x12,
	65	OP_CP2_NCDS = 0x13,
	66	OP_CP2_CDP = 0x14,
	67	OP_CP2_NCDT = 0x16,
	68	OP_CP2_NCCS = 0x1b,
	69	OP_CP2_CC = 0x1c,
	70	OP_CP2_NCS = 0x1e,
	71	OP_CP2_NCT = 0x20,
	72	OP_CP2_SQR = 0x28,
	73	OP_CP2_DCPL = 0x29,
	74	OP_CP2_DPCT = 0x2a,
	75	OP_CP2_AVSZ3 = 0x2d,
	76	OP_CP2_AVSZ4 = 0x2e,
	77	OP_CP2_RTPT = 0x30,
	78	OP_CP2_GPF = 0x3d,
	79	OP_CP2_GPL = 0x3e,
	80	OP_CP2_NCCT = 0x3f,
	81	};
	82
	83	static void (cp2_ops[])(struct psxCP2Regs ) = {
	84	[OP_CP2_RTPS] = gteRTPS,
	85	[OP_CP2_RTPS] = gteRTPS,
	86	[OP_CP2_NCLIP] = gteNCLIP,
	87	[OP_CP2_OP] = gteOP,
	88	[OP_CP2_DPCS] = gteDPCS,
	89	[OP_CP2_INTPL] = gteINTPL,
	90	[OP_CP2_MVMVA] = gteMVMVA,
	91	[OP_CP2_NCDS] = gteNCDS,
	92	[OP_CP2_CDP] = gteCDP,
	93	[OP_CP2_NCDT] = gteNCDT,
	94	[OP_CP2_NCCS] = gteNCCS,
	95	[OP_CP2_CC] = gteCC,
	96	[OP_CP2_NCS] = gteNCS,
	97	[OP_CP2_NCT] = gteNCT,
	98	[OP_CP2_SQR] = gteSQR,
	99	[OP_CP2_DCPL] = gteDCPL,
	100	[OP_CP2_DPCT] = gteDPCT,
	101	[OP_CP2_AVSZ3] = gteAVSZ3,
	102	[OP_CP2_AVSZ4] = gteAVSZ4,
	103	[OP_CP2_RTPT] = gteRTPT,
	104	[OP_CP2_GPF] = gteGPF,
	105	[OP_CP2_GPL] = gteGPL,
	106	[OP_CP2_NCCT] = gteNCCT,
	107	};
	108
	109	static char cache_buf[64 * 1024];
	110
0733c3ab	111	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	112	{
0733c3ab	113	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	114
0733c3ab	115	psxRegs.code = func;
6f1edc3c	116
0733c3ab PC	117	if (unlikely(!cp2_ops[func & 0x3f])) {
	118	fprintf(stderr, "Invalid CP2 function %u\n", func);
	119	} else {
	120	/* This works because regs->cp2c comes right after regs->cp2d,
	121	* so it can be cast to a pcsxCP2Regs pointer. */
	122	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	123	}
6f1edc3c PC	124	}
6f1edc3c PC	125
2bf88032 PC	126	static bool has_interrupt(void)
2bf88032 PC	127	{
6ce0b00a PC	128	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	129
2bf88032	130	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	131	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	132	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	133	}
2bf88032 PC	134
f4f9f2a4 PC	135	static void lightrec_restore_state(struct lightrec_state *state)
	136	{
	137	lightrec_reset_cycle_count(state, psxRegs.cycle);
2bf88032 PC	138
	139	if (booting \|\| has_interrupt())
	140	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	141	else
	142	lightrec_set_target_cycle_count(state, next_interupt);
f4f9f2a4 PC	143	}
f4f9f2a4 PC	144
6b02f240	145	static void hw_write_byte(struct lightrec_state *state,
6b02f240	146	u32 op, void *host, u32 mem, u8 val)
6f1edc3c PC	147	{
	148	psxRegs.cycle = lightrec_current_cycle_count(state);
	149
	150	psxHwWrite8(mem, val);
6f1edc3c	151
f4f9f2a4	152	lightrec_restore_state(state);
6f1edc3c PC	153	}
6f1edc3c PC	154
6b02f240	155	static void hw_write_half(struct lightrec_state *state,
6b02f240	156	u32 op, void *host, u32 mem, u16 val)
6f1edc3c PC	157	{
	158	psxRegs.cycle = lightrec_current_cycle_count(state);
	159
	160	psxHwWrite16(mem, val);
6f1edc3c	161
f4f9f2a4	162	lightrec_restore_state(state);
6f1edc3c PC	163	}
6f1edc3c PC	164
6b02f240	165	static void hw_write_word(struct lightrec_state *state,
6b02f240	166	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	167	{
	168	psxRegs.cycle = lightrec_current_cycle_count(state);
	169
	170	psxHwWrite32(mem, val);
6f1edc3c	171
f4f9f2a4	172	lightrec_restore_state(state);
6f1edc3c PC	173	}
6f1edc3c PC	174
6b02f240	175	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	176	{
	177	u8 val;
	178
	179	psxRegs.cycle = lightrec_current_cycle_count(state);
	180
6f1edc3c	181	val = psxHwRead8(mem);
f4f9f2a4 PC	182
f4f9f2a4 PC	183	lightrec_restore_state(state);
6f1edc3c PC	184
	185	return val;
	186	}
	187
6b02f240	188	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	189	u32 op, void *host, u32 mem)
6f1edc3c PC	190	{
	191	u16 val;
	192
	193	psxRegs.cycle = lightrec_current_cycle_count(state);
	194
6f1edc3c	195	val = psxHwRead16(mem);
f4f9f2a4 PC	196
f4f9f2a4 PC	197	lightrec_restore_state(state);
6f1edc3c PC	198
	199	return val;
	200	}
	201
6b02f240	202	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	203	u32 op, void *host, u32 mem)
6f1edc3c PC	204	{
	205	u32 val;
	206
	207	psxRegs.cycle = lightrec_current_cycle_count(state);
	208
6f1edc3c	209	val = psxHwRead32(mem);
f4f9f2a4 PC	210
f4f9f2a4 PC	211	lightrec_restore_state(state);
6f1edc3c PC	212
	213	return val;
	214	}
	215
	216	static struct lightrec_mem_map_ops hw_regs_ops = {
	217	.sb = hw_write_byte,
	218	.sh = hw_write_half,
	219	.sw = hw_write_word,
	220	.lb = hw_read_byte,
	221	.lh = hw_read_half,
	222	.lw = hw_read_word,
	223	};
	224
	225	static u32 cache_ctrl;
	226
6b02f240	227	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	228	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	229	{
	230	cache_ctrl = val;
	231	}
	232
6b02f240	233	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	234	u32 op, void *host, u32 mem)
6f1edc3c PC	235	{
	236	return cache_ctrl;
	237	}
	238
	239	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	240	.sw = cache_ctrl_write_word,
	241	.lw = cache_ctrl_read_word,
	242	};
	243
	244	static struct lightrec_mem_map lightrec_map[] = {
	245	[PSX_MAP_KERNEL_USER_RAM] = {
	246	/* Kernel and user memory */
	247	.pc = 0x00000000,
	248	.length = 0x200000,
	249	},
	250	[PSX_MAP_BIOS] = {
	251	/* BIOS */
	252	.pc = 0x1fc00000,
	253	.length = 0x80000,
	254	},
	255	[PSX_MAP_SCRATCH_PAD] = {
	256	/* Scratch pad */
	257	.pc = 0x1f800000,
	258	.length = 0x400,
	259	},
	260	[PSX_MAP_PARALLEL_PORT] = {
	261	/* Parallel port */
	262	.pc = 0x1f000000,
	263	.length = 0x10000,
	264	},
	265	[PSX_MAP_HW_REGISTERS] = {
	266	/* Hardware registers */
	267	.pc = 0x1f801000,
	268	.length = 0x2000,
	269	.ops = &hw_regs_ops,
	270	},
	271	[PSX_MAP_CACHE_CONTROL] = {
	272	/* Cache control */
	273	.pc = 0x5ffe0130,
	274	.length = 4,
	275	.ops = &cache_ctrl_ops,
	276	},
	277
	278	/* Mirrors of the kernel/user memory */
	279	[PSX_MAP_MIRROR1] = {
	280	.pc = 0x00200000,
	281	.length = 0x200000,
	282	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	283	},
	284	[PSX_MAP_MIRROR2] = {
	285	.pc = 0x00400000,
	286	.length = 0x200000,
	287	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	288	},
	289	[PSX_MAP_MIRROR3] = {
	290	.pc = 0x00600000,
	291	.length = 0x200000,
	292	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	293	},
f8548105 PC	294	[PSX_MAP_CODE_BUFFER] = {
	295	.length = CODE_BUFFER_SIZE,
	296	},
6f1edc3c PC	297	};
6f1edc3c PC	298
0733c3ab PC	299	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	300	{
	301	if (enable)
	302	memcpy(psxM, cache_buf, sizeof(cache_buf));
	303	else
	304	memcpy(cache_buf, psxM, sizeof(cache_buf));
	305	}
	306
ba3814c1 PC	307	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
	308	{
	309	switch (size) {
	310	case 8:
	311	switch (kaddr) {
	312	case 0x1f801040:
	313	case 0x1f801050:
	314	case 0x1f801800:
	315	case 0x1f801801:
	316	case 0x1f801802:
	317	case 0x1f801803:
	318	return false;
	319	default:
	320	return true;
	321	}
	322	case 16:
	323	switch (kaddr) {
	324	case 0x1f801040:
	325	case 0x1f801044:
	326	case 0x1f801048:
	327	case 0x1f80104a:
	328	case 0x1f80104e:
	329	case 0x1f801050:
	330	case 0x1f801054:
	331	case 0x1f80105a:
	332	case 0x1f80105e:
	333	case 0x1f801100:
	334	case 0x1f801104:
	335	case 0x1f801108:
	336	case 0x1f801110:
	337	case 0x1f801114:
	338	case 0x1f801118:
	339	case 0x1f801120:
	340	case 0x1f801124:
	341	case 0x1f801128:
	342	return false;
	343	case 0x1f801070:
	344	case 0x1f801074:
	345	return !is_write;
	346	default:
cdfa3536	347	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	348	}
	349	default:
	350	switch (kaddr) {
	351	case 0x1f801040:
	352	case 0x1f801050:
	353	case 0x1f801100:
	354	case 0x1f801104:
	355	case 0x1f801108:
	356	case 0x1f801110:
	357	case 0x1f801114:
	358	case 0x1f801118:
	359	case 0x1f801120:
	360	case 0x1f801124:
	361	case 0x1f801128:
	362	case 0x1f801810:
	363	case 0x1f801814:
	364	case 0x1f801820:
	365	case 0x1f801824:
	366	return false;
	367	case 0x1f801070:
	368	case 0x1f801074:
	369	case 0x1f801088:
	370	case 0x1f801098:
	371	case 0x1f8010a8:
	372	case 0x1f8010b8:
	373	case 0x1f8010c8:
	374	case 0x1f8010e8:
	375	case 0x1f8010f4:
	376	return !is_write;
	377	default:
	378	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	379	}
	380	}
	381	}
	382
6f1edc3c	383	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	384	.cop2_op = cop2_op,
0733c3ab PC	385	.enable_ram = lightrec_enable_ram,
ba3814c1	386	.hw_direct = lightrec_can_hw_direct,
6f1edc3c PC	387	};
	388
	389	static int lightrec_plugin_init(void)
	390	{
	391	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	392	lightrec_map[PSX_MAP_BIOS].address = psxR;
	393	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	394	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	395	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	396
479d58cf PC	397	if (LIGHTREC_CUSTOM_MAP) {
	398	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	399	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	400	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
f8548105	401	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
479d58cf PC	402	}
479d58cf PC	403
6f1edc3c	404	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	405
	406	lightrec_state = lightrec_init(name,
	407	lightrec_map, ARRAY_SIZE(lightrec_map),
	408	&lightrec_ops);
	409
9361a5aa EC	410	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	411	// (uintptr_t) psxM,
	412	// (uintptr_t) psxP,
	413	// (uintptr_t) psxR,
	414	// (uintptr_t) psxH);
6f1edc3c PC	415
	416	#ifndef _WIN32
	417	signal(SIGPIPE, exit);
	418	#endif
	419	return 0;
	420	}
	421
0733c3ab PC	422	static void lightrec_dump_regs(struct lightrec_state *state)
	423	{
	424	struct lightrec_registers *regs = lightrec_get_registers(state);
	425
	426	if (unlikely(booting))
	427	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	428	psxRegs.CP0.n.Status = regs->cp0[12];
	429	psxRegs.CP0.n.Cause = regs->cp0[13];
	430	}
	431
	432	static void lightrec_restore_regs(struct lightrec_state *state)
	433	{
	434	struct lightrec_registers *regs = lightrec_get_registers(state);
	435
	436	if (unlikely(booting))
	437	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	438	regs->cp0[12] = psxRegs.CP0.n.Status;
	439	regs->cp0[13] = psxRegs.CP0.n.Cause;
	440	regs->cp0[14] = psxRegs.CP0.n.EPC;
	441	}
6b02f240	442
6b02f240	443	extern void intExecuteBlock();
2bf88032	444	extern void gen_interupt();
6b02f240	445
d0abba5d	446	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	447	{
6f1edc3c PC	448	u32 flags;
6f1edc3c PC	449
2bf88032 PC	450	gen_interupt();
2bf88032 PC	451
ba3814c1	452	// step during early boot so that 0x80030000 fastboot hack works
d0abba5d	453	booting = block_only;
d0abba5d	454	if (block_only)
ba3814c1 PC	455	next_interupt = psxRegs.cycle;
ba3814c1 PC	456
6b02f240	457	if (use_pcsx_interpreter) {
	458	intExecuteBlock();
	459	} else {
	460	lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
0733c3ab	461	lightrec_restore_regs(lightrec_state);
6f1edc3c	462
ba3814c1	463	if (unlikely(use_lightrec_interpreter)) {
6b02f240	464	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1 PC	465	psxRegs.pc,
	466	next_interupt);
	467	} else {
2bf88032 PC	468	psxRegs.pc = lightrec_execute(lightrec_state,
2bf88032 PC	469	psxRegs.pc, next_interupt);
ba3814c1	470	}
6f1edc3c	471
6b02f240	472	psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
6f1edc3c	473
0733c3ab	474	lightrec_dump_regs(lightrec_state);
6b02f240	475	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	476
6b02f240	477	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	478	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	479	psxRegs.cycle);
	480	exit(1);
	481	}
6f1edc3c	482
6b02f240	483	if (flags & LIGHTREC_EXIT_SYSCALL)
6b02f240	484	psxException(0x20, 0);
2bf88032	485	}
6f1edc3c	486
6f1edc3c PC	487	if ((psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x300) &&
	488	(psxRegs.CP0.n.Status & 0x1)) {
	489	/* Handle software interrupts */
	490	psxRegs.CP0.n.Cause &= ~0x7c;
	491	psxException(psxRegs.CP0.n.Cause, 0);
	492	}
6f1edc3c PC	493	}
	494
	495	static void lightrec_plugin_execute(void)
	496	{
	497	extern int stop;
	498
	499	while (!stop)
d0abba5d	500	lightrec_plugin_execute_internal(false);
d0abba5d	501	}
	502
	503	static void lightrec_plugin_execute_block(void)
	504	{
	505	lightrec_plugin_execute_internal(true);
6f1edc3c PC	506	}
	507
	508	static void lightrec_plugin_clear(u32 addr, u32 size)
	509	{
8c9468f1 ZC	510	if (addr == 0 && size == UINT32_MAX)
	511	lightrec_invalidate_all(lightrec_state);
	512	else
	513	/* size * 4: PCSX uses DMA units */
	514	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	515	}
6f1edc3c PC	516
20196899	517	static void lightrec_plugin_sync_regs_to_pcsx(void);
	518	static void lightrec_plugin_sync_regs_from_pcsx(void);
	519
	520	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	521	{
7a811716	522	switch (note)
7a811716	523	{
20196899	524	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	525	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	526	/* not used, lightrec calls lightrec_enable_ram() instead */
	527	break;
	528	case R3000ACPU_NOTIFY_BEFORE_SAVE:
	529	lightrec_plugin_sync_regs_to_pcsx();
	530	break;
	531	case R3000ACPU_NOTIFY_AFTER_LOAD:
	532	lightrec_plugin_sync_regs_from_pcsx();
	533	break;
	534	}
7a811716	535	}
630b122b	536
	537	static void lightrec_plugin_apply_config()
	538	{
	539	}
7a811716	540
6f1edc3c PC	541	static void lightrec_plugin_shutdown(void)
	542	{
	543	lightrec_destroy(lightrec_state);
	544	}
	545
	546	static void lightrec_plugin_reset(void)
	547	{
0733c3ab PC	548	struct lightrec_registers *regs;
0733c3ab PC	549
0733c3ab PC	550	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	551
03535202 PC	552	/* Invalidate all blocks */
	553	lightrec_invalidate_all(lightrec_state);
	554
	555	/* Reset registers */
	556	memset(regs, 0, sizeof(*regs));
	557
0733c3ab PC	558	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	559	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6f1edc3c PC	560	}
6f1edc3c PC	561
20196899	562	static void lightrec_plugin_sync_regs_from_pcsx(void)
6962f770 PC	563	{
	564	struct lightrec_registers *regs;
	565
	566	regs = lightrec_get_registers(lightrec_state);
	567	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	568	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	569	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	570
	571	lightrec_invalidate_all(lightrec_state);
	572	}
	573
20196899	574	static void lightrec_plugin_sync_regs_to_pcsx(void)
6962f770 PC	575	{
	576	struct lightrec_registers *regs;
	577
	578	regs = lightrec_get_registers(lightrec_state);
	579	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	580	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	581	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	582	}
	583
6f1edc3c PC	584	R3000Acpu psxRec =
	585	{
	586	lightrec_plugin_init,
	587	lightrec_plugin_reset,
	588	lightrec_plugin_execute,
	589	lightrec_plugin_execute_block,
	590	lightrec_plugin_clear,
7a811716	591	lightrec_plugin_notify,
630b122b	592	lightrec_plugin_apply_config,
6f1edc3c PC	593	lightrec_plugin_shutdown,
6f1edc3c PC	594	};