[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>

#if P_HAVE_MMAP
#include <sys/mman.h>
#endif

#include "lightrec.h"
#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../psxhle.h"
#include "../psxevents.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

#ifndef LIGHTREC_PROG_NAME
#  ifdef __linux__
#    define LIGHTREC_PROG_NAME "/proc/self/exe"
#  else
#    define LIGHTREC_PROG_NAME "retroarch.exe"
#  endif
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

void* code_buffer;

static struct lightrec_state *lightrec_state;

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

extern u32 lightrec_hacks;

extern void lightrec_code_inv(void *ptr, uint32_t len);

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
{
	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
	lightrec_reset_cycle_count(state, 0);
}

static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
	s32 cycles_left = next_interupt - psxRegs.cycle;

	if (block_stepping || cycles_left <= 0 || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else {
		lightrec_set_target_cycle_count(state, cycles_left * 1024);
	}
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite8(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite16(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite32(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead8(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead16(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead32(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x8000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},

	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	[PSX_MAP_PPORT_MIRROR] = {
		.pc = 0x1fa00000,
		.length = 0x10000,
		.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	},

	/* Code buffer */
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	if (is_write && size != 32) {
		// force32 so must go through handlers
		if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
			return false;
		if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
			return false;
	}

	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
	.code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		code_buffer = mmap(0, CODE_BUFFER_SIZE,
				   PROT_EXEC | PROT_READ | PROT_WRITE,
				   MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
		if (code_buffer == MAP_FAILED)
			return -ENOMEM;
#else
		code_buffer = malloc(CODE_BUFFER_SIZE);
		if (!code_buffer)
			return -ENOMEM;
#endif
	}

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	}

	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(LIGHTREC_PROG_NAME,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags, cycles_pcsx;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);
	if (!block_only && stop)
		return;

	cycles_pcsx = next_interupt - psxRegs.cycle;
	assert((s32)cycles_pcsx > 0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		cycles_pcsx = 0;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		u32 cycles_lightrec = cycles_pcsx * 1024;
		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      cycles_lightrec);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, cycles_lightrec);
		}

		lightrec_tansition_to_pcsx(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
		if (flags & LIGHTREC_EXIT_BREAK)
			psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
		else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
			u32 op = intFakeFetch(psxRegs.pc);
			u32 hlec = op & 0x03ffffff;
			if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
				lightrec_plugin_sync_regs_to_pcsx(0);
				psxHLEt[hlec]();
				lightrec_plugin_sync_regs_from_pcsx(0);
			}
			else
				psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
		}
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if ((addr == 0 && size == UINT32_MAX)
	    || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		/* non-null 'data' means this is HLE related sync */
		lightrec_plugin_sync_regs_to_pcsx(data == NULL);
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx(data == NULL);
		if (data == NULL)
			lightrec_invalidate_all(lightrec_state);
		break;
	}
}

static void lightrec_plugin_apply_config()
{
	static u32 cycles_per_op_old;
	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
		? Config.cycle_multiplier_override : Config.cycle_multiplier;
	u32 cycles_per_op = cycle_mult * 1024 / 100;
	assert(cycles_per_op);

	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
		SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
			cycles_per_op / 1024.f);
	}
	cycles_per_op_old = cycles_per_op;
	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		munmap(code_buffer, CODE_BUFFER_SIZE);
#else
		free(code_buffer);
#endif
	}
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A

	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
}

static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
82183d4c	1	#include <errno.h>
6f1edc3c PC	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
c174cf6a	6	#include <assert.h>
6f1edc3c	7
c4f51fd8 PC	8	#if P_HAVE_MMAP
	9	#include <sys/mman.h>
	10	#endif
	11
7cbd2996	12	#include "lightrec.h"
6f1edc3c PC	13	#include "../cdrom.h"
	14	#include "../gpu.h"
	15	#include "../gte.h"
	16	#include "../mdec.h"
	17	#include "../psxdma.h"
	18	#include "../psxhw.h"
	19	#include "../psxmem.h"
	20	#include "../r3000a.h"
f2100c3d	21	#include "../psxinterpreter.h"
ec4baa7d	22	#include "../psxhle.h"
c6a249e3	23	#include "../psxevents.h"
6f1edc3c PC	24
	25	#include "../frontend/main.h"
	26
f8548105	27	#include "mem.h"
70939d49	28	#include "plugin.h"
f8548105	29
46a38bda	30	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	31	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	32	#endif
	33
6f1edc3c PC	34	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	35
	36	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	37	# define LE32TOH(x) __builtin_bswap32(x)
	38	# define HTOLE32(x) __builtin_bswap32(x)
	39	# define LE16TOH(x) __builtin_bswap16(x)
	40	# define HTOLE16(x) __builtin_bswap16(x)
	41	#else
	42	# define LE32TOH(x) (x)
	43	# define HTOLE32(x) (x)
	44	# define LE16TOH(x) (x)
	45	# define HTOLE16(x) (x)
	46	#endif
	47
	48	#ifdef __GNUC__
	49	# define likely(x) __builtin_expect(!!(x),1)
	50	# define unlikely(x) __builtin_expect(!!(x),0)
	51	#else
	52	# define likely(x) (x)
	53	# define unlikely(x) (x)
	54	#endif
	55
3bf2e5ab PC	56	#ifndef LIGHTREC_PROG_NAME
	57	# ifdef __linux__
	58	# define LIGHTREC_PROG_NAME "/proc/self/exe"
	59	# else
	60	# define LIGHTREC_PROG_NAME "retroarch.exe"
	61	# endif
	62	#endif
	63
630b122b	64	psxRegisters psxRegs;
	65	Rcnt rcnts[4];
	66
82183d4c PC	67	void* code_buffer;
82183d4c PC	68
6f1edc3c PC	69	static struct lightrec_state *lightrec_state;
6f1edc3c PC	70
6f1edc3c	71	static bool use_lightrec_interpreter;
6b02f240	72	static bool use_pcsx_interpreter;
6c62131f	73	static bool block_stepping;
6f1edc3c	74
8bccdd17 PC	75	extern u32 lightrec_hacks;
8bccdd17 PC	76
8ba7993c PC	77	extern void lightrec_code_inv(void *ptr, uint32_t len);
8ba7993c PC	78
6f1edc3c PC	79	enum my_cp2_opcodes {
	80	OP_CP2_RTPS = 0x01,
	81	OP_CP2_NCLIP = 0x06,
	82	OP_CP2_OP = 0x0c,
	83	OP_CP2_DPCS = 0x10,
	84	OP_CP2_INTPL = 0x11,
	85	OP_CP2_MVMVA = 0x12,
	86	OP_CP2_NCDS = 0x13,
	87	OP_CP2_CDP = 0x14,
	88	OP_CP2_NCDT = 0x16,
	89	OP_CP2_NCCS = 0x1b,
	90	OP_CP2_CC = 0x1c,
	91	OP_CP2_NCS = 0x1e,
	92	OP_CP2_NCT = 0x20,
	93	OP_CP2_SQR = 0x28,
	94	OP_CP2_DCPL = 0x29,
	95	OP_CP2_DPCT = 0x2a,
	96	OP_CP2_AVSZ3 = 0x2d,
	97	OP_CP2_AVSZ4 = 0x2e,
	98	OP_CP2_RTPT = 0x30,
	99	OP_CP2_GPF = 0x3d,
	100	OP_CP2_GPL = 0x3e,
	101	OP_CP2_NCCT = 0x3f,
	102	};
	103
	104	static void (cp2_ops[])(struct psxCP2Regs ) = {
	105	[OP_CP2_RTPS] = gteRTPS,
	106	[OP_CP2_RTPS] = gteRTPS,
	107	[OP_CP2_NCLIP] = gteNCLIP,
	108	[OP_CP2_OP] = gteOP,
	109	[OP_CP2_DPCS] = gteDPCS,
	110	[OP_CP2_INTPL] = gteINTPL,
	111	[OP_CP2_MVMVA] = gteMVMVA,
	112	[OP_CP2_NCDS] = gteNCDS,
	113	[OP_CP2_CDP] = gteCDP,
	114	[OP_CP2_NCDT] = gteNCDT,
	115	[OP_CP2_NCCS] = gteNCCS,
	116	[OP_CP2_CC] = gteCC,
	117	[OP_CP2_NCS] = gteNCS,
	118	[OP_CP2_NCT] = gteNCT,
	119	[OP_CP2_SQR] = gteSQR,
	120	[OP_CP2_DCPL] = gteDCPL,
	121	[OP_CP2_DPCT] = gteDPCT,
	122	[OP_CP2_AVSZ3] = gteAVSZ3,
	123	[OP_CP2_AVSZ4] = gteAVSZ4,
	124	[OP_CP2_RTPT] = gteRTPT,
	125	[OP_CP2_GPF] = gteGPF,
	126	[OP_CP2_GPL] = gteGPL,
	127	[OP_CP2_NCCT] = gteNCCT,
	128	};
	129
	130	static char cache_buf[64 * 1024];
	131
0733c3ab	132	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	133	{
0733c3ab	134	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	135
0733c3ab	136	psxRegs.code = func;
6f1edc3c	137
0733c3ab PC	138	if (unlikely(!cp2_ops[func & 0x3f])) {
	139	fprintf(stderr, "Invalid CP2 function %u\n", func);
	140	} else {
	141	/* This works because regs->cp2c comes right after regs->cp2d,
	142	* so it can be cast to a pcsxCP2Regs pointer. */
	143	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	144	}
6f1edc3c PC	145	}
6f1edc3c PC	146
2bf88032 PC	147	static bool has_interrupt(void)
2bf88032 PC	148	{
6ce0b00a PC	149	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	150
2bf88032	151	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	152	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	153	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	154	}
2bf88032 PC	155
c174cf6a	156	static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
c174cf6a	157	{
b45c3e27	158	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
c174cf6a	159	lightrec_reset_cycle_count(state, 0);
	160	}
	161
	162	static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
	163	{
	164	s32 cycles_left = next_interupt - psxRegs.cycle;
	165
	166	if (block_stepping \|\| cycles_left <= 0 \|\| has_interrupt())
2bf88032	167	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
c174cf6a	168	else {
b45c3e27	169	lightrec_set_target_cycle_count(state, cycles_left * 1024);
c174cf6a	170	}
f4f9f2a4 PC	171	}
f4f9f2a4 PC	172
6b02f240	173	static void hw_write_byte(struct lightrec_state *state,
909bfa63	174	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	175	{
c174cf6a	176	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	177
6f1edc3c PC	178	psxHwWrite8(mem, val);
6f1edc3c	179
c174cf6a	180	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	181	}
6f1edc3c PC	182
6b02f240	183	static void hw_write_half(struct lightrec_state *state,
909bfa63	184	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	185	{
c174cf6a	186	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	187
6f1edc3c PC	188	psxHwWrite16(mem, val);
6f1edc3c	189
c174cf6a	190	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	191	}
6f1edc3c PC	192
6b02f240	193	static void hw_write_word(struct lightrec_state *state,
6b02f240	194	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	195	{
c174cf6a	196	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	197
6f1edc3c PC	198	psxHwWrite32(mem, val);
6f1edc3c	199
c174cf6a	200	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	201	}
6f1edc3c PC	202
6b02f240	203	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	204	{
	205	u8 val;
	206
c174cf6a	207	lightrec_tansition_to_pcsx(state);
6f1edc3c	208
6f1edc3c	209	val = psxHwRead8(mem);
f4f9f2a4	210
c174cf6a	211	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	212
	213	return val;
	214	}
	215
6b02f240	216	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	217	u32 op, void *host, u32 mem)
6f1edc3c PC	218	{
	219	u16 val;
	220
c174cf6a	221	lightrec_tansition_to_pcsx(state);
6f1edc3c	222
6f1edc3c	223	val = psxHwRead16(mem);
f4f9f2a4	224
c174cf6a	225	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	226
	227	return val;
	228	}
	229
6b02f240	230	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	231	u32 op, void *host, u32 mem)
6f1edc3c PC	232	{
	233	u32 val;
	234
c174cf6a	235	lightrec_tansition_to_pcsx(state);
6f1edc3c	236
6f1edc3c	237	val = psxHwRead32(mem);
f4f9f2a4	238
c174cf6a	239	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	240
	241	return val;
	242	}
	243
	244	static struct lightrec_mem_map_ops hw_regs_ops = {
	245	.sb = hw_write_byte,
	246	.sh = hw_write_half,
	247	.sw = hw_write_word,
	248	.lb = hw_read_byte,
	249	.lh = hw_read_half,
	250	.lw = hw_read_word,
	251	};
	252
	253	static u32 cache_ctrl;
	254
6b02f240	255	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	256	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	257	{
	258	cache_ctrl = val;
	259	}
	260
6b02f240	261	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	262	u32 op, void *host, u32 mem)
6f1edc3c PC	263	{
	264	return cache_ctrl;
	265	}
	266
	267	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	268	.sw = cache_ctrl_write_word,
	269	.lw = cache_ctrl_read_word,
	270	};
	271
	272	static struct lightrec_mem_map lightrec_map[] = {
	273	[PSX_MAP_KERNEL_USER_RAM] = {
	274	/* Kernel and user memory */
	275	.pc = 0x00000000,
	276	.length = 0x200000,
	277	},
	278	[PSX_MAP_BIOS] = {
	279	/* BIOS */
	280	.pc = 0x1fc00000,
	281	.length = 0x80000,
	282	},
	283	[PSX_MAP_SCRATCH_PAD] = {
	284	/* Scratch pad */
	285	.pc = 0x1f800000,
	286	.length = 0x400,
	287	},
	288	[PSX_MAP_PARALLEL_PORT] = {
	289	/* Parallel port */
	290	.pc = 0x1f000000,
	291	.length = 0x10000,
	292	},
	293	[PSX_MAP_HW_REGISTERS] = {
	294	/* Hardware registers */
	295	.pc = 0x1f801000,
82d04936	296	.length = 0x8000,
6f1edc3c PC	297	.ops = &hw_regs_ops,
	298	},
	299	[PSX_MAP_CACHE_CONTROL] = {
	300	/* Cache control */
	301	.pc = 0x5ffe0130,
	302	.length = 4,
	303	.ops = &cache_ctrl_ops,
	304	},
	305
	306	/* Mirrors of the kernel/user memory */
	307	[PSX_MAP_MIRROR1] = {
	308	.pc = 0x00200000,
	309	.length = 0x200000,
	310	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	311	},
	312	[PSX_MAP_MIRROR2] = {
	313	.pc = 0x00400000,
	314	.length = 0x200000,
	315	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	316	},
	317	[PSX_MAP_MIRROR3] = {
	318	.pc = 0x00600000,
	319	.length = 0x200000,
	320	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	321	},
6e394614 PC	322
	323	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	324	[PSX_MAP_PPORT_MIRROR] = {
	325	.pc = 0x1fa00000,
	326	.length = 0x10000,
	327	.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	328	},
	329
	330	/* Code buffer */
f8548105 PC	331	[PSX_MAP_CODE_BUFFER] = {
	332	.length = CODE_BUFFER_SIZE,
	333	},
6f1edc3c PC	334	};
6f1edc3c PC	335
0733c3ab PC	336	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	337	{
	338	if (enable)
	339	memcpy(psxM, cache_buf, sizeof(cache_buf));
	340	else
	341	memcpy(cache_buf, psxM, sizeof(cache_buf));
	342	}
	343
ba3814c1 PC	344	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
ba3814c1 PC	345	{
ab206b0c	346	if (is_write && size != 32) {
	347	// force32 so must go through handlers
	348	if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
	349	return false;
	350	if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
	351	return false;
	352	}
	353
ba3814c1 PC	354	switch (size) {
	355	case 8:
	356	switch (kaddr) {
	357	case 0x1f801040:
	358	case 0x1f801050:
	359	case 0x1f801800:
	360	case 0x1f801801:
	361	case 0x1f801802:
	362	case 0x1f801803:
	363	return false;
	364	default:
	365	return true;
	366	}
	367	case 16:
	368	switch (kaddr) {
	369	case 0x1f801040:
	370	case 0x1f801044:
	371	case 0x1f801048:
	372	case 0x1f80104a:
	373	case 0x1f80104e:
	374	case 0x1f801050:
	375	case 0x1f801054:
	376	case 0x1f80105a:
	377	case 0x1f80105e:
	378	case 0x1f801100:
	379	case 0x1f801104:
	380	case 0x1f801108:
	381	case 0x1f801110:
	382	case 0x1f801114:
	383	case 0x1f801118:
	384	case 0x1f801120:
	385	case 0x1f801124:
	386	case 0x1f801128:
	387	return false;
	388	case 0x1f801070:
	389	case 0x1f801074:
	390	return !is_write;
	391	default:
cdfa3536	392	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	393	}
	394	default:
	395	switch (kaddr) {
	396	case 0x1f801040:
	397	case 0x1f801050:
	398	case 0x1f801100:
	399	case 0x1f801104:
	400	case 0x1f801108:
	401	case 0x1f801110:
	402	case 0x1f801114:
	403	case 0x1f801118:
	404	case 0x1f801120:
	405	case 0x1f801124:
	406	case 0x1f801128:
	407	case 0x1f801810:
	408	case 0x1f801814:
	409	case 0x1f801820:
	410	case 0x1f801824:
	411	return false;
	412	case 0x1f801070:
	413	case 0x1f801074:
	414	case 0x1f801088:
	415	case 0x1f801098:
	416	case 0x1f8010a8:
	417	case 0x1f8010b8:
	418	case 0x1f8010c8:
	419	case 0x1f8010e8:
	420	case 0x1f8010f4:
	421	return !is_write;
	422	default:
	423	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	424	}
	425	}
	426	}
	427
6f1edc3c	428	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	429	.cop2_op = cop2_op,
0733c3ab PC	430	.enable_ram = lightrec_enable_ram,
ba3814c1	431	.hw_direct = lightrec_can_hw_direct,
8ba7993c	432	.code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
6f1edc3c PC	433	};
	434
	435	static int lightrec_plugin_init(void)
	436	{
	437	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	438	lightrec_map[PSX_MAP_BIOS].address = psxR;
	439	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	440	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	441	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	442
82183d4c	443	if (!LIGHTREC_CUSTOM_MAP) {
c4f51fd8 PC	444	#if P_HAVE_MMAP
	445	code_buffer = mmap(0, CODE_BUFFER_SIZE,
	446	PROT_EXEC \| PROT_READ \| PROT_WRITE,
	447	MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	448	if (code_buffer == MAP_FAILED)
	449	return -ENOMEM;
	450	#else
82183d4c PC	451	code_buffer = malloc(CODE_BUFFER_SIZE);
	452	if (!code_buffer)
	453	return -ENOMEM;
c4f51fd8	454	#endif
82183d4c PC	455	}
82183d4c PC	456
479d58cf PC	457	if (LIGHTREC_CUSTOM_MAP) {
	458	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	459	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	460	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	461	}
	462
82183d4c PC	463	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
82183d4c PC	464
6f1edc3c	465	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c	466
3bf2e5ab	467	lightrec_state = lightrec_init(LIGHTREC_PROG_NAME,
6f1edc3c PC	468	lightrec_map, ARRAY_SIZE(lightrec_map),
	469	&lightrec_ops);
	470
9361a5aa EC	471	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	472	// (uintptr_t) psxM,
	473	// (uintptr_t) psxP,
	474	// (uintptr_t) psxR,
	475	// (uintptr_t) psxH);
6f1edc3c PC	476
	477	#ifndef _WIN32
	478	signal(SIGPIPE, exit);
	479	#endif
	480	return 0;
	481	}
	482
ec4baa7d	483	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
	484	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
	485
d0abba5d	486	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	487	{
6c62131f	488	struct lightrec_registers *regs;
c174cf6a	489	u32 flags, cycles_pcsx;
6f1edc3c	490
6c62131f	491	regs = lightrec_get_registers(lightrec_state);
6c62131f	492	gen_interupt((psxCP0Regs *)regs->cp0);
403a6290	493	if (!block_only && stop)
	494	return;
	495
c174cf6a	496	cycles_pcsx = next_interupt - psxRegs.cycle;
c174cf6a	497	assert((s32)cycles_pcsx > 0);
2bf88032	498
ba3814c1	499	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	500	block_stepping = block_only;
d0abba5d	501	if (block_only)
c174cf6a	502	cycles_pcsx = 0;
ba3814c1	503
6b02f240	504	if (use_pcsx_interpreter) {
f2100c3d	505	intExecuteBlock(0);
6b02f240	506	} else {
b45c3e27	507	u32 cycles_lightrec = cycles_pcsx * 1024;
ba3814c1	508	if (unlikely(use_lightrec_interpreter)) {
6b02f240	509	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1	510	psxRegs.pc,
c174cf6a	511	cycles_lightrec);
ba3814c1	512	} else {
2bf88032	513	psxRegs.pc = lightrec_execute(lightrec_state,
c174cf6a	514	psxRegs.pc, cycles_lightrec);
ba3814c1	515	}
6f1edc3c	516
c174cf6a	517	lightrec_tansition_to_pcsx(lightrec_state);
6f1edc3c	518
6b02f240	519	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	520
6b02f240	521	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	522	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	523	psxRegs.cycle);
	524	exit(1);
	525	}
6f1edc3c	526
6b02f240	527	if (flags & LIGHTREC_EXIT_SYSCALL)
ec4baa7d	528	psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
a95fc05a PC	529	if (flags & LIGHTREC_EXIT_BREAK)
a95fc05a PC	530	psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
ec4baa7d	531	else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
	532	u32 op = intFakeFetch(psxRegs.pc);
	533	u32 hlec = op & 0x03ffffff;
	534	if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
	535	lightrec_plugin_sync_regs_to_pcsx(0);
	536	psxHLEt[hlec]();
	537	lightrec_plugin_sync_regs_from_pcsx(0);
	538	}
	539	else
	540	psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
	541	}
2bf88032	542	}
6f1edc3c	543
6c62131f	544	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	545	/* Handle software interrupts */
6c62131f	546	regs->cp0[13] &= ~0x7c;
6c62131f	547	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	548	}
6f1edc3c PC	549	}
	550
	551	static void lightrec_plugin_execute(void)
	552	{
6f1edc3c	553	while (!stop)
d0abba5d	554	lightrec_plugin_execute_internal(false);
d0abba5d	555	}
d0abba5d	556
f3bc907d	557	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	558	{
d0abba5d	559	lightrec_plugin_execute_internal(true);
6f1edc3c PC	560	}
	561
	562	static void lightrec_plugin_clear(u32 addr, u32 size)
	563	{
0e481d53 PC	564	if ((addr == 0 && size == UINT32_MAX)
0e481d53 PC	565	\|\| (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
8c9468f1 ZC	566	lightrec_invalidate_all(lightrec_state);
	567	else
	568	/* size * 4: PCSX uses DMA units */
	569	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	570	}
6f1edc3c PC	571
20196899	572	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	573	{
7a811716	574	switch (note)
7a811716	575	{
20196899	576	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	577	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	578	/* not used, lightrec calls lightrec_enable_ram() instead */
	579	break;
	580	case R3000ACPU_NOTIFY_BEFORE_SAVE:
ec4baa7d	581	/* non-null 'data' means this is HLE related sync */
ec4baa7d	582	lightrec_plugin_sync_regs_to_pcsx(data == NULL);
20196899	583	break;
20196899	584	case R3000ACPU_NOTIFY_AFTER_LOAD:
ec4baa7d	585	lightrec_plugin_sync_regs_from_pcsx(data == NULL);
	586	if (data == NULL)
	587	lightrec_invalidate_all(lightrec_state);
20196899	588	break;
20196899	589	}
7a811716	590	}
630b122b	591
	592	static void lightrec_plugin_apply_config()
	593	{
7cbd2996	594	static u32 cycles_per_op_old;
c174cf6a	595	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
c174cf6a	596	? Config.cycle_multiplier_override : Config.cycle_multiplier;
7cbd2996	597	u32 cycles_per_op = cycle_mult * 1024 / 100;
7cbd2996	598	assert(cycles_per_op);
b45c3e27	599
7cbd2996	600	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
	601	SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
	602	cycles_per_op / 1024.f);
7cbd2996	603	}
	604	cycles_per_op_old = cycles_per_op;
	605	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
630b122b	606	}
7a811716	607
6f1edc3c PC	608	static void lightrec_plugin_shutdown(void)
	609	{
	610	lightrec_destroy(lightrec_state);
82183d4c	611
c4f51fd8 PC	612	if (!LIGHTREC_CUSTOM_MAP) {
	613	#if P_HAVE_MMAP
	614	munmap(code_buffer, CODE_BUFFER_SIZE);
	615	#else
82183d4c	616	free(code_buffer);
c4f51fd8 PC	617	#endif
c4f51fd8 PC	618	}
6f1edc3c PC	619	}
	620
	621	static void lightrec_plugin_reset(void)
	622	{
0733c3ab PC	623	struct lightrec_registers *regs;
0733c3ab PC	624
0733c3ab PC	625	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	626
03535202 PC	627	/* Invalidate all blocks */
	628	lightrec_invalidate_all(lightrec_state);
	629
	630	/* Reset registers */
	631	memset(regs, 0, sizeof(*regs));
	632
0733c3ab PC	633	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	634	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6c307d2d PC	635
6c307d2d PC	636	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
6f1edc3c PC	637	}
6f1edc3c PC	638
ec4baa7d	639	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
6962f770 PC	640	{
	641	struct lightrec_registers *regs;
	642
	643	regs = lightrec_get_registers(lightrec_state);
6962f770	644	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
ec4baa7d	645	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	646	if (need_cp2)
	647	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	648	}
6962f770 PC	649
ec4baa7d	650	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
6962f770 PC	651	{
	652	struct lightrec_registers *regs;
	653
	654	regs = lightrec_get_registers(lightrec_state);
6962f770	655	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
ec4baa7d	656	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	657	if (need_cp2)
	658	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	659	}
6962f770 PC	660
6f1edc3c PC	661	R3000Acpu psxRec =
	662	{
	663	lightrec_plugin_init,
	664	lightrec_plugin_reset,
	665	lightrec_plugin_execute,
	666	lightrec_plugin_execute_block,
	667	lightrec_plugin_clear,
7a811716	668	lightrec_plugin_notify,
630b122b	669	lightrec_plugin_apply_config,
6f1edc3c PC	670	lightrec_plugin_shutdown,
6f1edc3c PC	671	};