[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>

#if P_HAVE_MMAP
#include <sys/mman.h>
#endif

#include "lightrec.h"
#include "internals.h"
#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../psxhle.h"
#include "../psxevents.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

void* code_buffer;

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

extern u32 lightrec_hacks;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
{
	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
	lightrec_reset_cycle_count(state, 0);
}

static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
	s32 cycles_left = next_interupt - psxRegs.cycle;

	if (block_stepping || cycles_left <= 0 || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else {
		lightrec_set_target_cycle_count(state, cycles_left * 1024);
	}
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite8(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite16(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite32(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead8(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead16(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead32(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x8000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},

	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	[PSX_MAP_PPORT_MIRROR] = {
		.pc = 0x1fa00000,
		.length = 0x10000,
		.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	},

	/* Code buffer */
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	if (is_write && size != 32) {
		// force32 so must go through handlers
		if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
			return false;
		if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
			return false;
	}

	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

#if defined(HW_DOL) || defined(HW_RVL)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	extern void DCFlushRange(void *ptr, u32 len);
	extern void ICInvalidateRange(void *ptr, u32 len);

	DCFlushRange(ptr, len);
	ICInvalidateRange(ptr, len);
}
#elif defined(HW_WUP)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
}
#endif

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
	.code_inv = lightrec_code_inv,
#endif
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		code_buffer = mmap(0, CODE_BUFFER_SIZE,
				   PROT_EXEC | PROT_READ | PROT_WRITE,
				   MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
		if (code_buffer == MAP_FAILED)
			return -ENOMEM;
#else
		code_buffer = malloc(CODE_BUFFER_SIZE);
		if (!code_buffer)
			return -ENOMEM;
#endif
	}

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	}

	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags, cycles_pcsx;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);
	if (!block_only && stop)
		return;

	cycles_pcsx = next_interupt - psxRegs.cycle;
	assert((s32)cycles_pcsx > 0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		cycles_pcsx = 0;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		u32 cycles_lightrec = cycles_pcsx * 1024;
		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      cycles_lightrec);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, cycles_lightrec);
		}

		lightrec_tansition_to_pcsx(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
		if (flags & LIGHTREC_EXIT_BREAK)
			psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
		else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
			u32 op = intFakeFetch(psxRegs.pc);
			u32 hlec = op & 0x03ffffff;
			if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
				lightrec_plugin_sync_regs_to_pcsx(0);
				psxHLEt[hlec]();
				lightrec_plugin_sync_regs_from_pcsx(0);
			}
			else
				psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
		}
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if ((addr == 0 && size == UINT32_MAX)
	    || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		/* non-null 'data' means this is HLE related sync */
		lightrec_plugin_sync_regs_to_pcsx(data == NULL);
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx(data == NULL);
		if (data == NULL)
			lightrec_invalidate_all(lightrec_state);
		break;
	}
}

static void lightrec_plugin_apply_config()
{
	static u32 cycles_per_op_old;
	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
		? Config.cycle_multiplier_override : Config.cycle_multiplier;
	u32 cycles_per_op = cycle_mult * 1024 / 100;
	assert(cycles_per_op);

	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
		SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
			cycles_per_op / 1024.f);
		lightrec_plugin_clear_block_caches(lightrec_state);
	}
	cycles_per_op_old = cycles_per_op;
	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		munmap(code_buffer, CODE_BUFFER_SIZE);
#else
		free(code_buffer);
#endif
	}
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A

	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
}

static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
82183d4c	1	#include <errno.h>
6f1edc3c PC	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
c174cf6a	6	#include <assert.h>
6f1edc3c	7
c4f51fd8 PC	8	#if P_HAVE_MMAP
	9	#include <sys/mman.h>
	10	#endif
	11
7cbd2996	12	#include "lightrec.h"
7cbd2996	13	#include "internals.h"
6f1edc3c PC	14	#include "../cdrom.h"
	15	#include "../gpu.h"
	16	#include "../gte.h"
	17	#include "../mdec.h"
	18	#include "../psxdma.h"
	19	#include "../psxhw.h"
	20	#include "../psxmem.h"
	21	#include "../r3000a.h"
f2100c3d	22	#include "../psxinterpreter.h"
ec4baa7d	23	#include "../psxhle.h"
c6a249e3	24	#include "../psxevents.h"
6f1edc3c PC	25
	26	#include "../frontend/main.h"
	27
f8548105	28	#include "mem.h"
70939d49	29	#include "plugin.h"
f8548105	30
46a38bda	31	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	32	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	33	#endif
	34
6f1edc3c PC	35	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	36
	37	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	38	# define LE32TOH(x) __builtin_bswap32(x)
	39	# define HTOLE32(x) __builtin_bswap32(x)
	40	# define LE16TOH(x) __builtin_bswap16(x)
	41	# define HTOLE16(x) __builtin_bswap16(x)
	42	#else
	43	# define LE32TOH(x) (x)
	44	# define HTOLE32(x) (x)
	45	# define LE16TOH(x) (x)
	46	# define HTOLE16(x) (x)
	47	#endif
	48
	49	#ifdef __GNUC__
	50	# define likely(x) __builtin_expect(!!(x),1)
	51	# define unlikely(x) __builtin_expect(!!(x),0)
	52	#else
	53	# define likely(x) (x)
	54	# define unlikely(x) (x)
	55	#endif
	56
630b122b	57	psxRegisters psxRegs;
	58	Rcnt rcnts[4];
	59
82183d4c PC	60	void* code_buffer;
82183d4c PC	61
6f1edc3c PC	62	static struct lightrec_state *lightrec_state;
	63
	64	static char *name = "retroarch.exe";
	65
	66	static bool use_lightrec_interpreter;
6b02f240	67	static bool use_pcsx_interpreter;
6c62131f	68	static bool block_stepping;
6f1edc3c	69
8bccdd17 PC	70	extern u32 lightrec_hacks;
8bccdd17 PC	71
6f1edc3c PC	72	enum my_cp2_opcodes {
	73	OP_CP2_RTPS = 0x01,
	74	OP_CP2_NCLIP = 0x06,
	75	OP_CP2_OP = 0x0c,
	76	OP_CP2_DPCS = 0x10,
	77	OP_CP2_INTPL = 0x11,
	78	OP_CP2_MVMVA = 0x12,
	79	OP_CP2_NCDS = 0x13,
	80	OP_CP2_CDP = 0x14,
	81	OP_CP2_NCDT = 0x16,
	82	OP_CP2_NCCS = 0x1b,
	83	OP_CP2_CC = 0x1c,
	84	OP_CP2_NCS = 0x1e,
	85	OP_CP2_NCT = 0x20,
	86	OP_CP2_SQR = 0x28,
	87	OP_CP2_DCPL = 0x29,
	88	OP_CP2_DPCT = 0x2a,
	89	OP_CP2_AVSZ3 = 0x2d,
	90	OP_CP2_AVSZ4 = 0x2e,
	91	OP_CP2_RTPT = 0x30,
	92	OP_CP2_GPF = 0x3d,
	93	OP_CP2_GPL = 0x3e,
	94	OP_CP2_NCCT = 0x3f,
	95	};
	96
	97	static void (cp2_ops[])(struct psxCP2Regs ) = {
	98	[OP_CP2_RTPS] = gteRTPS,
	99	[OP_CP2_RTPS] = gteRTPS,
	100	[OP_CP2_NCLIP] = gteNCLIP,
	101	[OP_CP2_OP] = gteOP,
	102	[OP_CP2_DPCS] = gteDPCS,
	103	[OP_CP2_INTPL] = gteINTPL,
	104	[OP_CP2_MVMVA] = gteMVMVA,
	105	[OP_CP2_NCDS] = gteNCDS,
	106	[OP_CP2_CDP] = gteCDP,
	107	[OP_CP2_NCDT] = gteNCDT,
	108	[OP_CP2_NCCS] = gteNCCS,
	109	[OP_CP2_CC] = gteCC,
	110	[OP_CP2_NCS] = gteNCS,
	111	[OP_CP2_NCT] = gteNCT,
	112	[OP_CP2_SQR] = gteSQR,
	113	[OP_CP2_DCPL] = gteDCPL,
	114	[OP_CP2_DPCT] = gteDPCT,
	115	[OP_CP2_AVSZ3] = gteAVSZ3,
	116	[OP_CP2_AVSZ4] = gteAVSZ4,
	117	[OP_CP2_RTPT] = gteRTPT,
	118	[OP_CP2_GPF] = gteGPF,
	119	[OP_CP2_GPL] = gteGPL,
	120	[OP_CP2_NCCT] = gteNCCT,
	121	};
	122
	123	static char cache_buf[64 * 1024];
	124
0733c3ab	125	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	126	{
0733c3ab	127	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	128
0733c3ab	129	psxRegs.code = func;
6f1edc3c	130
0733c3ab PC	131	if (unlikely(!cp2_ops[func & 0x3f])) {
	132	fprintf(stderr, "Invalid CP2 function %u\n", func);
	133	} else {
	134	/* This works because regs->cp2c comes right after regs->cp2d,
	135	* so it can be cast to a pcsxCP2Regs pointer. */
	136	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	137	}
6f1edc3c PC	138	}
6f1edc3c PC	139
2bf88032 PC	140	static bool has_interrupt(void)
2bf88032 PC	141	{
6ce0b00a PC	142	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	143
2bf88032	144	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	145	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	146	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	147	}
2bf88032 PC	148
c174cf6a	149	static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
c174cf6a	150	{
b45c3e27	151	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
c174cf6a	152	lightrec_reset_cycle_count(state, 0);
	153	}
	154
	155	static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
	156	{
	157	s32 cycles_left = next_interupt - psxRegs.cycle;
	158
	159	if (block_stepping \|\| cycles_left <= 0 \|\| has_interrupt())
2bf88032	160	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
c174cf6a	161	else {
b45c3e27	162	lightrec_set_target_cycle_count(state, cycles_left * 1024);
c174cf6a	163	}
f4f9f2a4 PC	164	}
f4f9f2a4 PC	165
6b02f240	166	static void hw_write_byte(struct lightrec_state *state,
909bfa63	167	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	168	{
c174cf6a	169	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	170
6f1edc3c PC	171	psxHwWrite8(mem, val);
6f1edc3c	172
c174cf6a	173	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	174	}
6f1edc3c PC	175
6b02f240	176	static void hw_write_half(struct lightrec_state *state,
909bfa63	177	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	178	{
c174cf6a	179	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	180
6f1edc3c PC	181	psxHwWrite16(mem, val);
6f1edc3c	182
c174cf6a	183	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	184	}
6f1edc3c PC	185
6b02f240	186	static void hw_write_word(struct lightrec_state *state,
6b02f240	187	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	188	{
c174cf6a	189	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	190
6f1edc3c PC	191	psxHwWrite32(mem, val);
6f1edc3c	192
c174cf6a	193	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	194	}
6f1edc3c PC	195
6b02f240	196	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	197	{
	198	u8 val;
	199
c174cf6a	200	lightrec_tansition_to_pcsx(state);
6f1edc3c	201
6f1edc3c	202	val = psxHwRead8(mem);
f4f9f2a4	203
c174cf6a	204	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	205
	206	return val;
	207	}
	208
6b02f240	209	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	210	u32 op, void *host, u32 mem)
6f1edc3c PC	211	{
	212	u16 val;
	213
c174cf6a	214	lightrec_tansition_to_pcsx(state);
6f1edc3c	215
6f1edc3c	216	val = psxHwRead16(mem);
f4f9f2a4	217
c174cf6a	218	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	219
	220	return val;
	221	}
	222
6b02f240	223	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	224	u32 op, void *host, u32 mem)
6f1edc3c PC	225	{
	226	u32 val;
	227
c174cf6a	228	lightrec_tansition_to_pcsx(state);
6f1edc3c	229
6f1edc3c	230	val = psxHwRead32(mem);
f4f9f2a4	231
c174cf6a	232	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	233
	234	return val;
	235	}
	236
	237	static struct lightrec_mem_map_ops hw_regs_ops = {
	238	.sb = hw_write_byte,
	239	.sh = hw_write_half,
	240	.sw = hw_write_word,
	241	.lb = hw_read_byte,
	242	.lh = hw_read_half,
	243	.lw = hw_read_word,
	244	};
	245
	246	static u32 cache_ctrl;
	247
6b02f240	248	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	249	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	250	{
	251	cache_ctrl = val;
	252	}
	253
6b02f240	254	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	255	u32 op, void *host, u32 mem)
6f1edc3c PC	256	{
	257	return cache_ctrl;
	258	}
	259
	260	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	261	.sw = cache_ctrl_write_word,
	262	.lw = cache_ctrl_read_word,
	263	};
	264
	265	static struct lightrec_mem_map lightrec_map[] = {
	266	[PSX_MAP_KERNEL_USER_RAM] = {
	267	/* Kernel and user memory */
	268	.pc = 0x00000000,
	269	.length = 0x200000,
	270	},
	271	[PSX_MAP_BIOS] = {
	272	/* BIOS */
	273	.pc = 0x1fc00000,
	274	.length = 0x80000,
	275	},
	276	[PSX_MAP_SCRATCH_PAD] = {
	277	/* Scratch pad */
	278	.pc = 0x1f800000,
	279	.length = 0x400,
	280	},
	281	[PSX_MAP_PARALLEL_PORT] = {
	282	/* Parallel port */
	283	.pc = 0x1f000000,
	284	.length = 0x10000,
	285	},
	286	[PSX_MAP_HW_REGISTERS] = {
	287	/* Hardware registers */
	288	.pc = 0x1f801000,
82d04936	289	.length = 0x8000,
6f1edc3c PC	290	.ops = &hw_regs_ops,
	291	},
	292	[PSX_MAP_CACHE_CONTROL] = {
	293	/* Cache control */
	294	.pc = 0x5ffe0130,
	295	.length = 4,
	296	.ops = &cache_ctrl_ops,
	297	},
	298
	299	/* Mirrors of the kernel/user memory */
	300	[PSX_MAP_MIRROR1] = {
	301	.pc = 0x00200000,
	302	.length = 0x200000,
	303	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	304	},
	305	[PSX_MAP_MIRROR2] = {
	306	.pc = 0x00400000,
	307	.length = 0x200000,
	308	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	309	},
	310	[PSX_MAP_MIRROR3] = {
	311	.pc = 0x00600000,
	312	.length = 0x200000,
	313	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	314	},
6e394614 PC	315
	316	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	317	[PSX_MAP_PPORT_MIRROR] = {
	318	.pc = 0x1fa00000,
	319	.length = 0x10000,
	320	.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	321	},
	322
	323	/* Code buffer */
f8548105 PC	324	[PSX_MAP_CODE_BUFFER] = {
	325	.length = CODE_BUFFER_SIZE,
	326	},
6f1edc3c PC	327	};
6f1edc3c PC	328
0733c3ab PC	329	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	330	{
	331	if (enable)
	332	memcpy(psxM, cache_buf, sizeof(cache_buf));
	333	else
	334	memcpy(cache_buf, psxM, sizeof(cache_buf));
	335	}
	336
ba3814c1 PC	337	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
ba3814c1 PC	338	{
ab206b0c	339	if (is_write && size != 32) {
	340	// force32 so must go through handlers
	341	if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
	342	return false;
	343	if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
	344	return false;
	345	}
	346
ba3814c1 PC	347	switch (size) {
	348	case 8:
	349	switch (kaddr) {
	350	case 0x1f801040:
	351	case 0x1f801050:
	352	case 0x1f801800:
	353	case 0x1f801801:
	354	case 0x1f801802:
	355	case 0x1f801803:
	356	return false;
	357	default:
	358	return true;
	359	}
	360	case 16:
	361	switch (kaddr) {
	362	case 0x1f801040:
	363	case 0x1f801044:
	364	case 0x1f801048:
	365	case 0x1f80104a:
	366	case 0x1f80104e:
	367	case 0x1f801050:
	368	case 0x1f801054:
	369	case 0x1f80105a:
	370	case 0x1f80105e:
	371	case 0x1f801100:
	372	case 0x1f801104:
	373	case 0x1f801108:
	374	case 0x1f801110:
	375	case 0x1f801114:
	376	case 0x1f801118:
	377	case 0x1f801120:
	378	case 0x1f801124:
	379	case 0x1f801128:
	380	return false;
	381	case 0x1f801070:
	382	case 0x1f801074:
	383	return !is_write;
	384	default:
cdfa3536	385	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	386	}
	387	default:
	388	switch (kaddr) {
	389	case 0x1f801040:
	390	case 0x1f801050:
	391	case 0x1f801100:
	392	case 0x1f801104:
	393	case 0x1f801108:
	394	case 0x1f801110:
	395	case 0x1f801114:
	396	case 0x1f801118:
	397	case 0x1f801120:
	398	case 0x1f801124:
	399	case 0x1f801128:
	400	case 0x1f801810:
	401	case 0x1f801814:
	402	case 0x1f801820:
	403	case 0x1f801824:
	404	return false;
	405	case 0x1f801070:
	406	case 0x1f801074:
	407	case 0x1f801088:
	408	case 0x1f801098:
	409	case 0x1f8010a8:
	410	case 0x1f8010b8:
	411	case 0x1f8010c8:
	412	case 0x1f8010e8:
	413	case 0x1f8010f4:
	414	return !is_write;
	415	default:
	416	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	417	}
	418	}
	419	}
	420
323bb280 AL	421	#if defined(HW_DOL) \|\| defined(HW_RVL)
	422	static void lightrec_code_inv(void *ptr, uint32_t len)
	423	{
	424	extern void DCFlushRange(void *ptr, u32 len);
	425	extern void ICInvalidateRange(void *ptr, u32 len);
	426
	427	DCFlushRange(ptr, len);
	428	ICInvalidateRange(ptr, len);
	429	}
	430	#elif defined(HW_WUP)
	431	static void lightrec_code_inv(void *ptr, uint32_t len)
	432	{
	433	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
	434	}
	435	#endif
	436
6f1edc3c	437	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	438	.cop2_op = cop2_op,
0733c3ab PC	439	.enable_ram = lightrec_enable_ram,
ba3814c1	440	.hw_direct = lightrec_can_hw_direct,
323bb280 AL	441	#if defined(HW_DOL) \|\| defined(HW_RVL) \|\| defined(HW_WUP)
	442	.code_inv = lightrec_code_inv,
	443	#endif
6f1edc3c PC	444	};
	445
	446	static int lightrec_plugin_init(void)
	447	{
	448	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	449	lightrec_map[PSX_MAP_BIOS].address = psxR;
	450	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	451	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	452	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	453
82183d4c	454	if (!LIGHTREC_CUSTOM_MAP) {
c4f51fd8 PC	455	#if P_HAVE_MMAP
	456	code_buffer = mmap(0, CODE_BUFFER_SIZE,
	457	PROT_EXEC \| PROT_READ \| PROT_WRITE,
	458	MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	459	if (code_buffer == MAP_FAILED)
	460	return -ENOMEM;
	461	#else
82183d4c PC	462	code_buffer = malloc(CODE_BUFFER_SIZE);
	463	if (!code_buffer)
	464	return -ENOMEM;
c4f51fd8	465	#endif
82183d4c PC	466	}
82183d4c PC	467
479d58cf PC	468	if (LIGHTREC_CUSTOM_MAP) {
	469	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	470	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	471	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	472	}
	473
82183d4c PC	474	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
82183d4c PC	475
6f1edc3c	476	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	477
	478	lightrec_state = lightrec_init(name,
	479	lightrec_map, ARRAY_SIZE(lightrec_map),
	480	&lightrec_ops);
	481
9361a5aa EC	482	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	483	// (uintptr_t) psxM,
	484	// (uintptr_t) psxP,
	485	// (uintptr_t) psxR,
	486	// (uintptr_t) psxH);
6f1edc3c PC	487
	488	#ifndef _WIN32
	489	signal(SIGPIPE, exit);
	490	#endif
	491	return 0;
	492	}
	493
ec4baa7d	494	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
	495	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
	496
d0abba5d	497	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	498	{
6c62131f	499	struct lightrec_registers *regs;
c174cf6a	500	u32 flags, cycles_pcsx;
6f1edc3c	501
6c62131f	502	regs = lightrec_get_registers(lightrec_state);
6c62131f	503	gen_interupt((psxCP0Regs *)regs->cp0);
403a6290	504	if (!block_only && stop)
	505	return;
	506
c174cf6a	507	cycles_pcsx = next_interupt - psxRegs.cycle;
c174cf6a	508	assert((s32)cycles_pcsx > 0);
2bf88032	509
ba3814c1	510	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	511	block_stepping = block_only;
d0abba5d	512	if (block_only)
c174cf6a	513	cycles_pcsx = 0;
ba3814c1	514
6b02f240	515	if (use_pcsx_interpreter) {
f2100c3d	516	intExecuteBlock(0);
6b02f240	517	} else {
b45c3e27	518	u32 cycles_lightrec = cycles_pcsx * 1024;
ba3814c1	519	if (unlikely(use_lightrec_interpreter)) {
6b02f240	520	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1	521	psxRegs.pc,
c174cf6a	522	cycles_lightrec);
ba3814c1	523	} else {
2bf88032	524	psxRegs.pc = lightrec_execute(lightrec_state,
c174cf6a	525	psxRegs.pc, cycles_lightrec);
ba3814c1	526	}
6f1edc3c	527
c174cf6a	528	lightrec_tansition_to_pcsx(lightrec_state);
6f1edc3c	529
6b02f240	530	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	531
6b02f240	532	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	533	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	534	psxRegs.cycle);
	535	exit(1);
	536	}
6f1edc3c	537
6b02f240	538	if (flags & LIGHTREC_EXIT_SYSCALL)
ec4baa7d	539	psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
a95fc05a PC	540	if (flags & LIGHTREC_EXIT_BREAK)
a95fc05a PC	541	psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
ec4baa7d	542	else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
	543	u32 op = intFakeFetch(psxRegs.pc);
	544	u32 hlec = op & 0x03ffffff;
	545	if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
	546	lightrec_plugin_sync_regs_to_pcsx(0);
	547	psxHLEt[hlec]();
	548	lightrec_plugin_sync_regs_from_pcsx(0);
	549	}
	550	else
	551	psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
	552	}
2bf88032	553	}
6f1edc3c	554
6c62131f	555	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	556	/* Handle software interrupts */
6c62131f	557	regs->cp0[13] &= ~0x7c;
6c62131f	558	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	559	}
6f1edc3c PC	560	}
	561
	562	static void lightrec_plugin_execute(void)
	563	{
6f1edc3c	564	while (!stop)
d0abba5d	565	lightrec_plugin_execute_internal(false);
d0abba5d	566	}
d0abba5d	567
f3bc907d	568	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	569	{
d0abba5d	570	lightrec_plugin_execute_internal(true);
6f1edc3c PC	571	}
	572
	573	static void lightrec_plugin_clear(u32 addr, u32 size)
	574	{
0e481d53 PC	575	if ((addr == 0 && size == UINT32_MAX)
0e481d53 PC	576	\|\| (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
8c9468f1 ZC	577	lightrec_invalidate_all(lightrec_state);
	578	else
	579	/* size * 4: PCSX uses DMA units */
	580	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	581	}
6f1edc3c PC	582
20196899	583	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	584	{
7a811716	585	switch (note)
7a811716	586	{
20196899	587	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	588	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	589	/* not used, lightrec calls lightrec_enable_ram() instead */
	590	break;
	591	case R3000ACPU_NOTIFY_BEFORE_SAVE:
ec4baa7d	592	/* non-null 'data' means this is HLE related sync */
ec4baa7d	593	lightrec_plugin_sync_regs_to_pcsx(data == NULL);
20196899	594	break;
20196899	595	case R3000ACPU_NOTIFY_AFTER_LOAD:
ec4baa7d	596	lightrec_plugin_sync_regs_from_pcsx(data == NULL);
	597	if (data == NULL)
	598	lightrec_invalidate_all(lightrec_state);
20196899	599	break;
20196899	600	}
7a811716	601	}
630b122b	602
	603	static void lightrec_plugin_apply_config()
	604	{
7cbd2996	605	static u32 cycles_per_op_old;
c174cf6a	606	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
c174cf6a	607	? Config.cycle_multiplier_override : Config.cycle_multiplier;
7cbd2996	608	u32 cycles_per_op = cycle_mult * 1024 / 100;
7cbd2996	609	assert(cycles_per_op);
b45c3e27	610
7cbd2996	611	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
	612	SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
	613	cycles_per_op / 1024.f);
	614	lightrec_plugin_clear_block_caches(lightrec_state);
	615	}
	616	cycles_per_op_old = cycles_per_op;
	617	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
630b122b	618	}
7a811716	619
6f1edc3c PC	620	static void lightrec_plugin_shutdown(void)
	621	{
	622	lightrec_destroy(lightrec_state);
82183d4c	623
c4f51fd8 PC	624	if (!LIGHTREC_CUSTOM_MAP) {
	625	#if P_HAVE_MMAP
	626	munmap(code_buffer, CODE_BUFFER_SIZE);
	627	#else
82183d4c	628	free(code_buffer);
c4f51fd8 PC	629	#endif
c4f51fd8 PC	630	}
6f1edc3c PC	631	}
	632
	633	static void lightrec_plugin_reset(void)
	634	{
0733c3ab PC	635	struct lightrec_registers *regs;
0733c3ab PC	636
0733c3ab PC	637	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	638
03535202 PC	639	/* Invalidate all blocks */
	640	lightrec_invalidate_all(lightrec_state);
	641
	642	/* Reset registers */
	643	memset(regs, 0, sizeof(*regs));
	644
0733c3ab PC	645	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	646	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6c307d2d PC	647
6c307d2d PC	648	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
6f1edc3c PC	649	}
6f1edc3c PC	650
ec4baa7d	651	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
6962f770 PC	652	{
	653	struct lightrec_registers *regs;
	654
	655	regs = lightrec_get_registers(lightrec_state);
6962f770	656	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
ec4baa7d	657	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	658	if (need_cp2)
	659	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	660	}
6962f770 PC	661
ec4baa7d	662	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
6962f770 PC	663	{
	664	struct lightrec_registers *regs;
	665
	666	regs = lightrec_get_registers(lightrec_state);
6962f770	667	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
ec4baa7d	668	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	669	if (need_cp2)
	670	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	671	}
6962f770 PC	672
6f1edc3c PC	673	R3000Acpu psxRec =
	674	{
	675	lightrec_plugin_init,
	676	lightrec_plugin_reset,
	677	lightrec_plugin_execute,
	678	lightrec_plugin_execute_block,
	679	lightrec_plugin_clear,
7a811716	680	lightrec_plugin_notify,
630b122b	681	lightrec_plugin_apply_config,
6f1edc3c PC	682	lightrec_plugin_shutdown,
6f1edc3c PC	683	};