[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>

#if P_HAVE_MMAP
#include <sys/mman.h>
#endif

#include "lightrec.h"
#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../psxhle.h"
#include "../psxevents.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

void* code_buffer;

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

extern u32 lightrec_hacks;

extern void lightrec_code_inv(void *ptr, uint32_t len);

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
{
	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
	lightrec_reset_cycle_count(state, 0);
}

static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
	s32 cycles_left = next_interupt - psxRegs.cycle;

	if (block_stepping || cycles_left <= 0 || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else {
		lightrec_set_target_cycle_count(state, cycles_left * 1024);
	}
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite8(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite16(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite32(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead8(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead16(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead32(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x8000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},

	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	[PSX_MAP_PPORT_MIRROR] = {
		.pc = 0x1fa00000,
		.length = 0x10000,
		.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	},

	/* Code buffer */
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	if (is_write && size != 32) {
		// force32 so must go through handlers
		if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
			return false;
		if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
			return false;
	}

	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
	.code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		code_buffer = mmap(0, CODE_BUFFER_SIZE,
				   PROT_EXEC | PROT_READ | PROT_WRITE,
				   MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
		if (code_buffer == MAP_FAILED)
			return -ENOMEM;
#else
		code_buffer = malloc(CODE_BUFFER_SIZE);
		if (!code_buffer)
			return -ENOMEM;
#endif
	}

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	}

	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags, cycles_pcsx;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);
	if (!block_only && stop)
		return;

	cycles_pcsx = next_interupt - psxRegs.cycle;
	assert((s32)cycles_pcsx > 0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		cycles_pcsx = 0;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		u32 cycles_lightrec = cycles_pcsx * 1024;
		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      cycles_lightrec);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, cycles_lightrec);
		}

		lightrec_tansition_to_pcsx(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
		if (flags & LIGHTREC_EXIT_BREAK)
			psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
		else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
			u32 op = intFakeFetch(psxRegs.pc);
			u32 hlec = op & 0x03ffffff;
			if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
				lightrec_plugin_sync_regs_to_pcsx(0);
				psxHLEt[hlec]();
				lightrec_plugin_sync_regs_from_pcsx(0);
			}
			else
				psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
		}
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if ((addr == 0 && size == UINT32_MAX)
	    || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		/* non-null 'data' means this is HLE related sync */
		lightrec_plugin_sync_regs_to_pcsx(data == NULL);
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx(data == NULL);
		if (data == NULL)
			lightrec_invalidate_all(lightrec_state);
		break;
	}
}

static void lightrec_plugin_apply_config()
{
	static u32 cycles_per_op_old;
	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
		? Config.cycle_multiplier_override : Config.cycle_multiplier;
	u32 cycles_per_op = cycle_mult * 1024 / 100;
	assert(cycles_per_op);

	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
		SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
			cycles_per_op / 1024.f);
	}
	cycles_per_op_old = cycles_per_op;
	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);

	if (!LIGHTREC_CUSTOM_MAP) {
#if P_HAVE_MMAP
		munmap(code_buffer, CODE_BUFFER_SIZE);
#else
		free(code_buffer);
#endif
	}
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A

	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
}

static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	if (need_cp2)
		memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
82183d4c	1	#include <errno.h>
6f1edc3c PC	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
c174cf6a	6	#include <assert.h>
6f1edc3c	7
c4f51fd8 PC	8	#if P_HAVE_MMAP
	9	#include <sys/mman.h>
	10	#endif
	11
7cbd2996	12	#include "lightrec.h"
6f1edc3c PC	13	#include "../cdrom.h"
	14	#include "../gpu.h"
	15	#include "../gte.h"
	16	#include "../mdec.h"
	17	#include "../psxdma.h"
	18	#include "../psxhw.h"
	19	#include "../psxmem.h"
	20	#include "../r3000a.h"
f2100c3d	21	#include "../psxinterpreter.h"
ec4baa7d	22	#include "../psxhle.h"
c6a249e3	23	#include "../psxevents.h"
6f1edc3c PC	24
	25	#include "../frontend/main.h"
	26
f8548105	27	#include "mem.h"
70939d49	28	#include "plugin.h"
f8548105	29
46a38bda	30	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	31	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	32	#endif
	33
6f1edc3c PC	34	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	35
	36	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	37	# define LE32TOH(x) __builtin_bswap32(x)
	38	# define HTOLE32(x) __builtin_bswap32(x)
	39	# define LE16TOH(x) __builtin_bswap16(x)
	40	# define HTOLE16(x) __builtin_bswap16(x)
	41	#else
	42	# define LE32TOH(x) (x)
	43	# define HTOLE32(x) (x)
	44	# define LE16TOH(x) (x)
	45	# define HTOLE16(x) (x)
	46	#endif
	47
	48	#ifdef __GNUC__
	49	# define likely(x) __builtin_expect(!!(x),1)
	50	# define unlikely(x) __builtin_expect(!!(x),0)
	51	#else
	52	# define likely(x) (x)
	53	# define unlikely(x) (x)
	54	#endif
	55
630b122b	56	psxRegisters psxRegs;
	57	Rcnt rcnts[4];
	58
82183d4c PC	59	void* code_buffer;
82183d4c PC	60
6f1edc3c PC	61	static struct lightrec_state *lightrec_state;
	62
	63	static char *name = "retroarch.exe";
	64
	65	static bool use_lightrec_interpreter;
6b02f240	66	static bool use_pcsx_interpreter;
6c62131f	67	static bool block_stepping;
6f1edc3c	68
8bccdd17 PC	69	extern u32 lightrec_hacks;
8bccdd17 PC	70
8ba7993c PC	71	extern void lightrec_code_inv(void *ptr, uint32_t len);
8ba7993c PC	72
6f1edc3c PC	73	enum my_cp2_opcodes {
	74	OP_CP2_RTPS = 0x01,
	75	OP_CP2_NCLIP = 0x06,
	76	OP_CP2_OP = 0x0c,
	77	OP_CP2_DPCS = 0x10,
	78	OP_CP2_INTPL = 0x11,
	79	OP_CP2_MVMVA = 0x12,
	80	OP_CP2_NCDS = 0x13,
	81	OP_CP2_CDP = 0x14,
	82	OP_CP2_NCDT = 0x16,
	83	OP_CP2_NCCS = 0x1b,
	84	OP_CP2_CC = 0x1c,
	85	OP_CP2_NCS = 0x1e,
	86	OP_CP2_NCT = 0x20,
	87	OP_CP2_SQR = 0x28,
	88	OP_CP2_DCPL = 0x29,
	89	OP_CP2_DPCT = 0x2a,
	90	OP_CP2_AVSZ3 = 0x2d,
	91	OP_CP2_AVSZ4 = 0x2e,
	92	OP_CP2_RTPT = 0x30,
	93	OP_CP2_GPF = 0x3d,
	94	OP_CP2_GPL = 0x3e,
	95	OP_CP2_NCCT = 0x3f,
	96	};
	97
	98	static void (cp2_ops[])(struct psxCP2Regs ) = {
	99	[OP_CP2_RTPS] = gteRTPS,
	100	[OP_CP2_RTPS] = gteRTPS,
	101	[OP_CP2_NCLIP] = gteNCLIP,
	102	[OP_CP2_OP] = gteOP,
	103	[OP_CP2_DPCS] = gteDPCS,
	104	[OP_CP2_INTPL] = gteINTPL,
	105	[OP_CP2_MVMVA] = gteMVMVA,
	106	[OP_CP2_NCDS] = gteNCDS,
	107	[OP_CP2_CDP] = gteCDP,
	108	[OP_CP2_NCDT] = gteNCDT,
	109	[OP_CP2_NCCS] = gteNCCS,
	110	[OP_CP2_CC] = gteCC,
	111	[OP_CP2_NCS] = gteNCS,
	112	[OP_CP2_NCT] = gteNCT,
	113	[OP_CP2_SQR] = gteSQR,
	114	[OP_CP2_DCPL] = gteDCPL,
	115	[OP_CP2_DPCT] = gteDPCT,
	116	[OP_CP2_AVSZ3] = gteAVSZ3,
	117	[OP_CP2_AVSZ4] = gteAVSZ4,
	118	[OP_CP2_RTPT] = gteRTPT,
	119	[OP_CP2_GPF] = gteGPF,
	120	[OP_CP2_GPL] = gteGPL,
	121	[OP_CP2_NCCT] = gteNCCT,
	122	};
	123
	124	static char cache_buf[64 * 1024];
	125
0733c3ab	126	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	127	{
0733c3ab	128	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	129
0733c3ab	130	psxRegs.code = func;
6f1edc3c	131
0733c3ab PC	132	if (unlikely(!cp2_ops[func & 0x3f])) {
	133	fprintf(stderr, "Invalid CP2 function %u\n", func);
	134	} else {
	135	/* This works because regs->cp2c comes right after regs->cp2d,
	136	* so it can be cast to a pcsxCP2Regs pointer. */
	137	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	138	}
6f1edc3c PC	139	}
6f1edc3c PC	140
2bf88032 PC	141	static bool has_interrupt(void)
2bf88032 PC	142	{
6ce0b00a PC	143	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	144
2bf88032	145	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	146	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	147	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	148	}
2bf88032 PC	149
c174cf6a	150	static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
c174cf6a	151	{
b45c3e27	152	psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
c174cf6a	153	lightrec_reset_cycle_count(state, 0);
	154	}
	155
	156	static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
	157	{
	158	s32 cycles_left = next_interupt - psxRegs.cycle;
	159
	160	if (block_stepping \|\| cycles_left <= 0 \|\| has_interrupt())
2bf88032	161	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
c174cf6a	162	else {
b45c3e27	163	lightrec_set_target_cycle_count(state, cycles_left * 1024);
c174cf6a	164	}
f4f9f2a4 PC	165	}
f4f9f2a4 PC	166
6b02f240	167	static void hw_write_byte(struct lightrec_state *state,
909bfa63	168	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	169	{
c174cf6a	170	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	171
6f1edc3c PC	172	psxHwWrite8(mem, val);
6f1edc3c	173
c174cf6a	174	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	175	}
6f1edc3c PC	176
6b02f240	177	static void hw_write_half(struct lightrec_state *state,
909bfa63	178	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	179	{
c174cf6a	180	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	181
6f1edc3c PC	182	psxHwWrite16(mem, val);
6f1edc3c	183
c174cf6a	184	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	185	}
6f1edc3c PC	186
6b02f240	187	static void hw_write_word(struct lightrec_state *state,
6b02f240	188	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	189	{
c174cf6a	190	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	191
6f1edc3c PC	192	psxHwWrite32(mem, val);
6f1edc3c	193
c174cf6a	194	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	195	}
6f1edc3c PC	196
6b02f240	197	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	198	{
	199	u8 val;
	200
c174cf6a	201	lightrec_tansition_to_pcsx(state);
6f1edc3c	202
6f1edc3c	203	val = psxHwRead8(mem);
f4f9f2a4	204
c174cf6a	205	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	206
	207	return val;
	208	}
	209
6b02f240	210	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	211	u32 op, void *host, u32 mem)
6f1edc3c PC	212	{
	213	u16 val;
	214
c174cf6a	215	lightrec_tansition_to_pcsx(state);
6f1edc3c	216
6f1edc3c	217	val = psxHwRead16(mem);
f4f9f2a4	218
c174cf6a	219	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	220
	221	return val;
	222	}
	223
6b02f240	224	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	225	u32 op, void *host, u32 mem)
6f1edc3c PC	226	{
	227	u32 val;
	228
c174cf6a	229	lightrec_tansition_to_pcsx(state);
6f1edc3c	230
6f1edc3c	231	val = psxHwRead32(mem);
f4f9f2a4	232
c174cf6a	233	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	234
	235	return val;
	236	}
	237
	238	static struct lightrec_mem_map_ops hw_regs_ops = {
	239	.sb = hw_write_byte,
	240	.sh = hw_write_half,
	241	.sw = hw_write_word,
	242	.lb = hw_read_byte,
	243	.lh = hw_read_half,
	244	.lw = hw_read_word,
	245	};
	246
	247	static u32 cache_ctrl;
	248
6b02f240	249	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	250	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	251	{
	252	cache_ctrl = val;
	253	}
	254
6b02f240	255	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	256	u32 op, void *host, u32 mem)
6f1edc3c PC	257	{
	258	return cache_ctrl;
	259	}
	260
	261	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	262	.sw = cache_ctrl_write_word,
	263	.lw = cache_ctrl_read_word,
	264	};
	265
	266	static struct lightrec_mem_map lightrec_map[] = {
	267	[PSX_MAP_KERNEL_USER_RAM] = {
	268	/* Kernel and user memory */
	269	.pc = 0x00000000,
	270	.length = 0x200000,
	271	},
	272	[PSX_MAP_BIOS] = {
	273	/* BIOS */
	274	.pc = 0x1fc00000,
	275	.length = 0x80000,
	276	},
	277	[PSX_MAP_SCRATCH_PAD] = {
	278	/* Scratch pad */
	279	.pc = 0x1f800000,
	280	.length = 0x400,
	281	},
	282	[PSX_MAP_PARALLEL_PORT] = {
	283	/* Parallel port */
	284	.pc = 0x1f000000,
	285	.length = 0x10000,
	286	},
	287	[PSX_MAP_HW_REGISTERS] = {
	288	/* Hardware registers */
	289	.pc = 0x1f801000,
82d04936	290	.length = 0x8000,
6f1edc3c PC	291	.ops = &hw_regs_ops,
	292	},
	293	[PSX_MAP_CACHE_CONTROL] = {
	294	/* Cache control */
	295	.pc = 0x5ffe0130,
	296	.length = 4,
	297	.ops = &cache_ctrl_ops,
	298	},
	299
	300	/* Mirrors of the kernel/user memory */
	301	[PSX_MAP_MIRROR1] = {
	302	.pc = 0x00200000,
	303	.length = 0x200000,
	304	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	305	},
	306	[PSX_MAP_MIRROR2] = {
	307	.pc = 0x00400000,
	308	.length = 0x200000,
	309	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	310	},
	311	[PSX_MAP_MIRROR3] = {
	312	.pc = 0x00600000,
	313	.length = 0x200000,
	314	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	315	},
6e394614 PC	316
	317	/* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
	318	[PSX_MAP_PPORT_MIRROR] = {
	319	.pc = 0x1fa00000,
	320	.length = 0x10000,
	321	.mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
	322	},
	323
	324	/* Code buffer */
f8548105 PC	325	[PSX_MAP_CODE_BUFFER] = {
	326	.length = CODE_BUFFER_SIZE,
	327	},
6f1edc3c PC	328	};
6f1edc3c PC	329
0733c3ab PC	330	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	331	{
	332	if (enable)
	333	memcpy(psxM, cache_buf, sizeof(cache_buf));
	334	else
	335	memcpy(cache_buf, psxM, sizeof(cache_buf));
	336	}
	337
ba3814c1 PC	338	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
ba3814c1 PC	339	{
ab206b0c	340	if (is_write && size != 32) {
	341	// force32 so must go through handlers
	342	if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
	343	return false;
	344	if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
	345	return false;
	346	}
	347
ba3814c1 PC	348	switch (size) {
	349	case 8:
	350	switch (kaddr) {
	351	case 0x1f801040:
	352	case 0x1f801050:
	353	case 0x1f801800:
	354	case 0x1f801801:
	355	case 0x1f801802:
	356	case 0x1f801803:
	357	return false;
	358	default:
	359	return true;
	360	}
	361	case 16:
	362	switch (kaddr) {
	363	case 0x1f801040:
	364	case 0x1f801044:
	365	case 0x1f801048:
	366	case 0x1f80104a:
	367	case 0x1f80104e:
	368	case 0x1f801050:
	369	case 0x1f801054:
	370	case 0x1f80105a:
	371	case 0x1f80105e:
	372	case 0x1f801100:
	373	case 0x1f801104:
	374	case 0x1f801108:
	375	case 0x1f801110:
	376	case 0x1f801114:
	377	case 0x1f801118:
	378	case 0x1f801120:
	379	case 0x1f801124:
	380	case 0x1f801128:
	381	return false;
	382	case 0x1f801070:
	383	case 0x1f801074:
	384	return !is_write;
	385	default:
cdfa3536	386	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	387	}
	388	default:
	389	switch (kaddr) {
	390	case 0x1f801040:
	391	case 0x1f801050:
	392	case 0x1f801100:
	393	case 0x1f801104:
	394	case 0x1f801108:
	395	case 0x1f801110:
	396	case 0x1f801114:
	397	case 0x1f801118:
	398	case 0x1f801120:
	399	case 0x1f801124:
	400	case 0x1f801128:
	401	case 0x1f801810:
	402	case 0x1f801814:
	403	case 0x1f801820:
	404	case 0x1f801824:
	405	return false;
	406	case 0x1f801070:
	407	case 0x1f801074:
	408	case 0x1f801088:
	409	case 0x1f801098:
	410	case 0x1f8010a8:
	411	case 0x1f8010b8:
	412	case 0x1f8010c8:
	413	case 0x1f8010e8:
	414	case 0x1f8010f4:
	415	return !is_write;
	416	default:
	417	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	418	}
	419	}
	420	}
	421
6f1edc3c	422	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	423	.cop2_op = cop2_op,
0733c3ab PC	424	.enable_ram = lightrec_enable_ram,
ba3814c1	425	.hw_direct = lightrec_can_hw_direct,
8ba7993c	426	.code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
6f1edc3c PC	427	};
	428
	429	static int lightrec_plugin_init(void)
	430	{
	431	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	432	lightrec_map[PSX_MAP_BIOS].address = psxR;
	433	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	434	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	435	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	436
82183d4c	437	if (!LIGHTREC_CUSTOM_MAP) {
c4f51fd8 PC	438	#if P_HAVE_MMAP
	439	code_buffer = mmap(0, CODE_BUFFER_SIZE,
	440	PROT_EXEC \| PROT_READ \| PROT_WRITE,
	441	MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	442	if (code_buffer == MAP_FAILED)
	443	return -ENOMEM;
	444	#else
82183d4c PC	445	code_buffer = malloc(CODE_BUFFER_SIZE);
	446	if (!code_buffer)
	447	return -ENOMEM;
c4f51fd8	448	#endif
82183d4c PC	449	}
82183d4c PC	450
479d58cf PC	451	if (LIGHTREC_CUSTOM_MAP) {
	452	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	453	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	454	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	455	}
	456
82183d4c PC	457	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
82183d4c PC	458
6f1edc3c	459	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	460
	461	lightrec_state = lightrec_init(name,
	462	lightrec_map, ARRAY_SIZE(lightrec_map),
	463	&lightrec_ops);
	464
9361a5aa EC	465	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	466	// (uintptr_t) psxM,
	467	// (uintptr_t) psxP,
	468	// (uintptr_t) psxR,
	469	// (uintptr_t) psxH);
6f1edc3c PC	470
	471	#ifndef _WIN32
	472	signal(SIGPIPE, exit);
	473	#endif
	474	return 0;
	475	}
	476
ec4baa7d	477	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
	478	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
	479
d0abba5d	480	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	481	{
6c62131f	482	struct lightrec_registers *regs;
c174cf6a	483	u32 flags, cycles_pcsx;
6f1edc3c	484
6c62131f	485	regs = lightrec_get_registers(lightrec_state);
6c62131f	486	gen_interupt((psxCP0Regs *)regs->cp0);
403a6290	487	if (!block_only && stop)
	488	return;
	489
c174cf6a	490	cycles_pcsx = next_interupt - psxRegs.cycle;
c174cf6a	491	assert((s32)cycles_pcsx > 0);
2bf88032	492
ba3814c1	493	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	494	block_stepping = block_only;
d0abba5d	495	if (block_only)
c174cf6a	496	cycles_pcsx = 0;
ba3814c1	497
6b02f240	498	if (use_pcsx_interpreter) {
f2100c3d	499	intExecuteBlock(0);
6b02f240	500	} else {
b45c3e27	501	u32 cycles_lightrec = cycles_pcsx * 1024;
ba3814c1	502	if (unlikely(use_lightrec_interpreter)) {
6b02f240	503	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1	504	psxRegs.pc,
c174cf6a	505	cycles_lightrec);
ba3814c1	506	} else {
2bf88032	507	psxRegs.pc = lightrec_execute(lightrec_state,
c174cf6a	508	psxRegs.pc, cycles_lightrec);
ba3814c1	509	}
6f1edc3c	510
c174cf6a	511	lightrec_tansition_to_pcsx(lightrec_state);
6f1edc3c	512
6b02f240	513	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	514
6b02f240	515	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	516	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	517	psxRegs.cycle);
	518	exit(1);
	519	}
6f1edc3c	520
6b02f240	521	if (flags & LIGHTREC_EXIT_SYSCALL)
ec4baa7d	522	psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
a95fc05a PC	523	if (flags & LIGHTREC_EXIT_BREAK)
a95fc05a PC	524	psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
ec4baa7d	525	else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
	526	u32 op = intFakeFetch(psxRegs.pc);
	527	u32 hlec = op & 0x03ffffff;
	528	if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
	529	lightrec_plugin_sync_regs_to_pcsx(0);
	530	psxHLEt[hlec]();
	531	lightrec_plugin_sync_regs_from_pcsx(0);
	532	}
	533	else
	534	psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
	535	}
2bf88032	536	}
6f1edc3c	537
6c62131f	538	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	539	/* Handle software interrupts */
6c62131f	540	regs->cp0[13] &= ~0x7c;
6c62131f	541	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	542	}
6f1edc3c PC	543	}
	544
	545	static void lightrec_plugin_execute(void)
	546	{
6f1edc3c	547	while (!stop)
d0abba5d	548	lightrec_plugin_execute_internal(false);
d0abba5d	549	}
d0abba5d	550
f3bc907d	551	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	552	{
d0abba5d	553	lightrec_plugin_execute_internal(true);
6f1edc3c PC	554	}
	555
	556	static void lightrec_plugin_clear(u32 addr, u32 size)
	557	{
0e481d53 PC	558	if ((addr == 0 && size == UINT32_MAX)
0e481d53 PC	559	\|\| (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
8c9468f1 ZC	560	lightrec_invalidate_all(lightrec_state);
	561	else
	562	/* size * 4: PCSX uses DMA units */
	563	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	564	}
6f1edc3c PC	565
20196899	566	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	567	{
7a811716	568	switch (note)
7a811716	569	{
20196899	570	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	571	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	572	/* not used, lightrec calls lightrec_enable_ram() instead */
	573	break;
	574	case R3000ACPU_NOTIFY_BEFORE_SAVE:
ec4baa7d	575	/* non-null 'data' means this is HLE related sync */
ec4baa7d	576	lightrec_plugin_sync_regs_to_pcsx(data == NULL);
20196899	577	break;
20196899	578	case R3000ACPU_NOTIFY_AFTER_LOAD:
ec4baa7d	579	lightrec_plugin_sync_regs_from_pcsx(data == NULL);
	580	if (data == NULL)
	581	lightrec_invalidate_all(lightrec_state);
20196899	582	break;
20196899	583	}
7a811716	584	}
630b122b	585
	586	static void lightrec_plugin_apply_config()
	587	{
7cbd2996	588	static u32 cycles_per_op_old;
c174cf6a	589	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
c174cf6a	590	? Config.cycle_multiplier_override : Config.cycle_multiplier;
7cbd2996	591	u32 cycles_per_op = cycle_mult * 1024 / 100;
7cbd2996	592	assert(cycles_per_op);
b45c3e27	593
7cbd2996	594	if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
	595	SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
	596	cycles_per_op / 1024.f);
7cbd2996	597	}
	598	cycles_per_op_old = cycles_per_op;
	599	lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
630b122b	600	}
7a811716	601
6f1edc3c PC	602	static void lightrec_plugin_shutdown(void)
	603	{
	604	lightrec_destroy(lightrec_state);
82183d4c	605
c4f51fd8 PC	606	if (!LIGHTREC_CUSTOM_MAP) {
	607	#if P_HAVE_MMAP
	608	munmap(code_buffer, CODE_BUFFER_SIZE);
	609	#else
82183d4c	610	free(code_buffer);
c4f51fd8 PC	611	#endif
c4f51fd8 PC	612	}
6f1edc3c PC	613	}
	614
	615	static void lightrec_plugin_reset(void)
	616	{
0733c3ab PC	617	struct lightrec_registers *regs;
0733c3ab PC	618
0733c3ab PC	619	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	620
03535202 PC	621	/* Invalidate all blocks */
	622	lightrec_invalidate_all(lightrec_state);
	623
	624	/* Reset registers */
	625	memset(regs, 0, sizeof(*regs));
	626
0733c3ab PC	627	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	628	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6c307d2d PC	629
6c307d2d PC	630	lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
6f1edc3c PC	631	}
6f1edc3c PC	632
ec4baa7d	633	static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
6962f770 PC	634	{
	635	struct lightrec_registers *regs;
	636
	637	regs = lightrec_get_registers(lightrec_state);
6962f770	638	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
ec4baa7d	639	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	640	if (need_cp2)
	641	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	642	}
6962f770 PC	643
ec4baa7d	644	static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
6962f770 PC	645	{
	646	struct lightrec_registers *regs;
	647
	648	regs = lightrec_get_registers(lightrec_state);
6962f770	649	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
ec4baa7d	650	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	651	if (need_cp2)
	652	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
6962f770 PC	653	}
6962f770 PC	654
6f1edc3c PC	655	R3000Acpu psxRec =
	656	{
	657	lightrec_plugin_init,
	658	lightrec_plugin_reset,
	659	lightrec_plugin_execute,
	660	lightrec_plugin_execute_block,
	661	lightrec_plugin_clear,
7a811716	662	lightrec_plugin_notify,
630b122b	663	lightrec_plugin_apply_config,
6f1edc3c PC	664	lightrec_plugin_shutdown,
6f1edc3c PC	665	};