[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <lightrec.h>
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>

#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../new_dynarec/events.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

void* code_buffer;

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;
static u32 cycle_mult_to_pcsx; // 22.10 fractional
static u32 cycle_mult_from_pcsx;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static u32 cycles_pcsx_to_lightrec(u32 c)
{
	assert((u64)c * cycle_mult_from_pcsx <= (u32)-1);
	return c * cycle_mult_from_pcsx >> 10;
}

static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
{
	psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10;
	lightrec_reset_cycle_count(state, 0);
}

static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
{
	s32 cycles_left = next_interupt - psxRegs.cycle;

	if (block_stepping || cycles_left <= 0 || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else {
		lightrec_set_target_cycle_count(state,
			cycles_pcsx_to_lightrec(cycles_left));
	}
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u8 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite8(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u16 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite16(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	lightrec_tansition_to_pcsx(state);

	psxHwWrite32(mem, val);

	lightrec_tansition_from_pcsx(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead8(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead16(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	lightrec_tansition_to_pcsx(state);

	val = psxHwRead32(mem);

	lightrec_tansition_from_pcsx(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x2000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

#if defined(HW_DOL) || defined(HW_RVL)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	extern void DCFlushRange(void *ptr, u32 len);
	extern void ICInvalidateRange(void *ptr, u32 len);

	DCFlushRange(ptr, len);
	ICInvalidateRange(ptr, len);
}
#elif defined(HW_WUP)
static void lightrec_code_inv(void *ptr, uint32_t len)
{
	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
}
#endif

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
#if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
	.code_inv = lightrec_code_inv,
#endif
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (!LIGHTREC_CUSTOM_MAP) {
		code_buffer = malloc(CODE_BUFFER_SIZE);
		if (!code_buffer)
			return -ENOMEM;
	}

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	}

	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags, cycles_pcsx;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);
	cycles_pcsx = next_interupt - psxRegs.cycle;
	assert((s32)cycles_pcsx > 0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		cycles_pcsx = 0;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx);
		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      cycles_lightrec);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, cycles_lightrec);
		}

		lightrec_tansition_to_pcsx(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	extern int stop;

	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if (addr == 0 && size == UINT32_MAX)
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_sync_regs_to_pcsx(void);
static void lightrec_plugin_sync_regs_from_pcsx(void);

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		lightrec_plugin_sync_regs_to_pcsx();
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx();
		break;
	}
}

static void lightrec_plugin_apply_config()
{
	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
		? Config.cycle_multiplier_override : Config.cycle_multiplier;
	assert(cycle_mult);
	cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200;
	cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult;
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);

	if (!LIGHTREC_CUSTOM_MAP)
		free(code_buffer);
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
}

static void lightrec_plugin_sync_regs_from_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));

	lightrec_invalidate_all(lightrec_state);
}

static void lightrec_plugin_sync_regs_to_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
6f1edc3c	1	#include <lightrec.h>
82183d4c	2	#include <errno.h>
6f1edc3c PC	3	#include <stdbool.h>
	4	#include <stdio.h>
	5	#include <unistd.h>
	6	#include <signal.h>
c174cf6a	7	#include <assert.h>
6f1edc3c PC	8
	9	#include "../cdrom.h"
	10	#include "../gpu.h"
	11	#include "../gte.h"
	12	#include "../mdec.h"
	13	#include "../psxdma.h"
	14	#include "../psxhw.h"
	15	#include "../psxmem.h"
	16	#include "../r3000a.h"
f2100c3d	17	#include "../psxinterpreter.h"
6c62131f	18	#include "../new_dynarec/events.h"
6f1edc3c PC	19
	20	#include "../frontend/main.h"
	21
f8548105	22	#include "mem.h"
70939d49	23	#include "plugin.h"
f8548105	24
46a38bda	25	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	26	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	27	#endif
	28
6f1edc3c PC	29	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	30
	31	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	32	# define LE32TOH(x) __builtin_bswap32(x)
	33	# define HTOLE32(x) __builtin_bswap32(x)
	34	# define LE16TOH(x) __builtin_bswap16(x)
	35	# define HTOLE16(x) __builtin_bswap16(x)
	36	#else
	37	# define LE32TOH(x) (x)
	38	# define HTOLE32(x) (x)
	39	# define LE16TOH(x) (x)
	40	# define HTOLE16(x) (x)
	41	#endif
	42
	43	#ifdef __GNUC__
	44	# define likely(x) __builtin_expect(!!(x),1)
	45	# define unlikely(x) __builtin_expect(!!(x),0)
	46	#else
	47	# define likely(x) (x)
	48	# define unlikely(x) (x)
	49	#endif
	50
630b122b	51	psxRegisters psxRegs;
	52	Rcnt rcnts[4];
	53
82183d4c PC	54	void* code_buffer;
82183d4c PC	55
6f1edc3c PC	56	static struct lightrec_state *lightrec_state;
	57
	58	static char *name = "retroarch.exe";
	59
	60	static bool use_lightrec_interpreter;
6b02f240	61	static bool use_pcsx_interpreter;
6c62131f	62	static bool block_stepping;
c174cf6a	63	static u32 cycle_mult_to_pcsx; // 22.10 fractional
c174cf6a	64	static u32 cycle_mult_from_pcsx;
6f1edc3c	65
6f1edc3c PC	66	enum my_cp2_opcodes {
	67	OP_CP2_RTPS = 0x01,
	68	OP_CP2_NCLIP = 0x06,
	69	OP_CP2_OP = 0x0c,
	70	OP_CP2_DPCS = 0x10,
	71	OP_CP2_INTPL = 0x11,
	72	OP_CP2_MVMVA = 0x12,
	73	OP_CP2_NCDS = 0x13,
	74	OP_CP2_CDP = 0x14,
	75	OP_CP2_NCDT = 0x16,
	76	OP_CP2_NCCS = 0x1b,
	77	OP_CP2_CC = 0x1c,
	78	OP_CP2_NCS = 0x1e,
	79	OP_CP2_NCT = 0x20,
	80	OP_CP2_SQR = 0x28,
	81	OP_CP2_DCPL = 0x29,
	82	OP_CP2_DPCT = 0x2a,
	83	OP_CP2_AVSZ3 = 0x2d,
	84	OP_CP2_AVSZ4 = 0x2e,
	85	OP_CP2_RTPT = 0x30,
	86	OP_CP2_GPF = 0x3d,
	87	OP_CP2_GPL = 0x3e,
	88	OP_CP2_NCCT = 0x3f,
	89	};
	90
	91	static void (cp2_ops[])(struct psxCP2Regs ) = {
	92	[OP_CP2_RTPS] = gteRTPS,
	93	[OP_CP2_RTPS] = gteRTPS,
	94	[OP_CP2_NCLIP] = gteNCLIP,
	95	[OP_CP2_OP] = gteOP,
	96	[OP_CP2_DPCS] = gteDPCS,
	97	[OP_CP2_INTPL] = gteINTPL,
	98	[OP_CP2_MVMVA] = gteMVMVA,
	99	[OP_CP2_NCDS] = gteNCDS,
	100	[OP_CP2_CDP] = gteCDP,
	101	[OP_CP2_NCDT] = gteNCDT,
	102	[OP_CP2_NCCS] = gteNCCS,
	103	[OP_CP2_CC] = gteCC,
	104	[OP_CP2_NCS] = gteNCS,
	105	[OP_CP2_NCT] = gteNCT,
	106	[OP_CP2_SQR] = gteSQR,
	107	[OP_CP2_DCPL] = gteDCPL,
	108	[OP_CP2_DPCT] = gteDPCT,
	109	[OP_CP2_AVSZ3] = gteAVSZ3,
	110	[OP_CP2_AVSZ4] = gteAVSZ4,
	111	[OP_CP2_RTPT] = gteRTPT,
	112	[OP_CP2_GPF] = gteGPF,
	113	[OP_CP2_GPL] = gteGPL,
	114	[OP_CP2_NCCT] = gteNCCT,
	115	};
	116
	117	static char cache_buf[64 * 1024];
	118
0733c3ab	119	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	120	{
0733c3ab	121	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	122
0733c3ab	123	psxRegs.code = func;
6f1edc3c	124
0733c3ab PC	125	if (unlikely(!cp2_ops[func & 0x3f])) {
	126	fprintf(stderr, "Invalid CP2 function %u\n", func);
	127	} else {
	128	/* This works because regs->cp2c comes right after regs->cp2d,
	129	* so it can be cast to a pcsxCP2Regs pointer. */
	130	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	131	}
6f1edc3c PC	132	}
6f1edc3c PC	133
2bf88032 PC	134	static bool has_interrupt(void)
2bf88032 PC	135	{
6ce0b00a PC	136	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	137
2bf88032	138	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	139	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	140	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	141	}
2bf88032 PC	142
c174cf6a	143	static u32 cycles_pcsx_to_lightrec(u32 c)
f4f9f2a4	144	{
c174cf6a	145	assert((u64)c * cycle_mult_from_pcsx <= (u32)-1);
	146	return c * cycle_mult_from_pcsx >> 10;
	147	}
2bf88032	148
c174cf6a	149	static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
	150	{
	151	psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10;
	152	lightrec_reset_cycle_count(state, 0);
	153	}
	154
	155	static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
	156	{
	157	s32 cycles_left = next_interupt - psxRegs.cycle;
	158
	159	if (block_stepping \|\| cycles_left <= 0 \|\| has_interrupt())
2bf88032	160	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
c174cf6a	161	else {
	162	lightrec_set_target_cycle_count(state,
	163	cycles_pcsx_to_lightrec(cycles_left));
	164	}
f4f9f2a4 PC	165	}
f4f9f2a4 PC	166
6b02f240	167	static void hw_write_byte(struct lightrec_state *state,
6b02f240	168	u32 op, void *host, u32 mem, u8 val)
6f1edc3c	169	{
c174cf6a	170	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	171
6f1edc3c PC	172	psxHwWrite8(mem, val);
6f1edc3c	173
c174cf6a	174	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	175	}
6f1edc3c PC	176
6b02f240	177	static void hw_write_half(struct lightrec_state *state,
6b02f240	178	u32 op, void *host, u32 mem, u16 val)
6f1edc3c	179	{
c174cf6a	180	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	181
6f1edc3c PC	182	psxHwWrite16(mem, val);
6f1edc3c	183
c174cf6a	184	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	185	}
6f1edc3c PC	186
6b02f240	187	static void hw_write_word(struct lightrec_state *state,
6b02f240	188	u32 op, void *host, u32 mem, u32 val)
6f1edc3c	189	{
c174cf6a	190	lightrec_tansition_to_pcsx(state);
6f1edc3c PC	191
6f1edc3c PC	192	psxHwWrite32(mem, val);
6f1edc3c	193
c174cf6a	194	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	195	}
6f1edc3c PC	196
6b02f240	197	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	198	{
	199	u8 val;
	200
c174cf6a	201	lightrec_tansition_to_pcsx(state);
6f1edc3c	202
6f1edc3c	203	val = psxHwRead8(mem);
f4f9f2a4	204
c174cf6a	205	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	206
	207	return val;
	208	}
	209
6b02f240	210	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	211	u32 op, void *host, u32 mem)
6f1edc3c PC	212	{
	213	u16 val;
	214
c174cf6a	215	lightrec_tansition_to_pcsx(state);
6f1edc3c	216
6f1edc3c	217	val = psxHwRead16(mem);
f4f9f2a4	218
c174cf6a	219	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	220
	221	return val;
	222	}
	223
6b02f240	224	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	225	u32 op, void *host, u32 mem)
6f1edc3c PC	226	{
	227	u32 val;
	228
c174cf6a	229	lightrec_tansition_to_pcsx(state);
6f1edc3c	230
6f1edc3c	231	val = psxHwRead32(mem);
f4f9f2a4	232
c174cf6a	233	lightrec_tansition_from_pcsx(state);
6f1edc3c PC	234
	235	return val;
	236	}
	237
	238	static struct lightrec_mem_map_ops hw_regs_ops = {
	239	.sb = hw_write_byte,
	240	.sh = hw_write_half,
	241	.sw = hw_write_word,
	242	.lb = hw_read_byte,
	243	.lh = hw_read_half,
	244	.lw = hw_read_word,
	245	};
	246
	247	static u32 cache_ctrl;
	248
6b02f240	249	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	250	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	251	{
	252	cache_ctrl = val;
	253	}
	254
6b02f240	255	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	256	u32 op, void *host, u32 mem)
6f1edc3c PC	257	{
	258	return cache_ctrl;
	259	}
	260
	261	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	262	.sw = cache_ctrl_write_word,
	263	.lw = cache_ctrl_read_word,
	264	};
	265
	266	static struct lightrec_mem_map lightrec_map[] = {
	267	[PSX_MAP_KERNEL_USER_RAM] = {
	268	/* Kernel and user memory */
	269	.pc = 0x00000000,
	270	.length = 0x200000,
	271	},
	272	[PSX_MAP_BIOS] = {
	273	/* BIOS */
	274	.pc = 0x1fc00000,
	275	.length = 0x80000,
	276	},
	277	[PSX_MAP_SCRATCH_PAD] = {
	278	/* Scratch pad */
	279	.pc = 0x1f800000,
	280	.length = 0x400,
	281	},
	282	[PSX_MAP_PARALLEL_PORT] = {
	283	/* Parallel port */
	284	.pc = 0x1f000000,
	285	.length = 0x10000,
	286	},
	287	[PSX_MAP_HW_REGISTERS] = {
	288	/* Hardware registers */
	289	.pc = 0x1f801000,
	290	.length = 0x2000,
	291	.ops = &hw_regs_ops,
	292	},
	293	[PSX_MAP_CACHE_CONTROL] = {
	294	/* Cache control */
	295	.pc = 0x5ffe0130,
	296	.length = 4,
	297	.ops = &cache_ctrl_ops,
	298	},
	299
	300	/* Mirrors of the kernel/user memory */
	301	[PSX_MAP_MIRROR1] = {
	302	.pc = 0x00200000,
	303	.length = 0x200000,
	304	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	305	},
	306	[PSX_MAP_MIRROR2] = {
	307	.pc = 0x00400000,
	308	.length = 0x200000,
	309	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	310	},
	311	[PSX_MAP_MIRROR3] = {
	312	.pc = 0x00600000,
	313	.length = 0x200000,
	314	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	315	},
f8548105 PC	316	[PSX_MAP_CODE_BUFFER] = {
	317	.length = CODE_BUFFER_SIZE,
	318	},
6f1edc3c PC	319	};
6f1edc3c PC	320
0733c3ab PC	321	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	322	{
	323	if (enable)
	324	memcpy(psxM, cache_buf, sizeof(cache_buf));
	325	else
	326	memcpy(cache_buf, psxM, sizeof(cache_buf));
	327	}
	328
ba3814c1 PC	329	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
	330	{
	331	switch (size) {
	332	case 8:
	333	switch (kaddr) {
	334	case 0x1f801040:
	335	case 0x1f801050:
	336	case 0x1f801800:
	337	case 0x1f801801:
	338	case 0x1f801802:
	339	case 0x1f801803:
	340	return false;
	341	default:
	342	return true;
	343	}
	344	case 16:
	345	switch (kaddr) {
	346	case 0x1f801040:
	347	case 0x1f801044:
	348	case 0x1f801048:
	349	case 0x1f80104a:
	350	case 0x1f80104e:
	351	case 0x1f801050:
	352	case 0x1f801054:
	353	case 0x1f80105a:
	354	case 0x1f80105e:
	355	case 0x1f801100:
	356	case 0x1f801104:
	357	case 0x1f801108:
	358	case 0x1f801110:
	359	case 0x1f801114:
	360	case 0x1f801118:
	361	case 0x1f801120:
	362	case 0x1f801124:
	363	case 0x1f801128:
	364	return false;
	365	case 0x1f801070:
	366	case 0x1f801074:
	367	return !is_write;
	368	default:
cdfa3536	369	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	370	}
	371	default:
	372	switch (kaddr) {
	373	case 0x1f801040:
	374	case 0x1f801050:
	375	case 0x1f801100:
	376	case 0x1f801104:
	377	case 0x1f801108:
	378	case 0x1f801110:
	379	case 0x1f801114:
	380	case 0x1f801118:
	381	case 0x1f801120:
	382	case 0x1f801124:
	383	case 0x1f801128:
	384	case 0x1f801810:
	385	case 0x1f801814:
	386	case 0x1f801820:
	387	case 0x1f801824:
	388	return false;
	389	case 0x1f801070:
	390	case 0x1f801074:
	391	case 0x1f801088:
	392	case 0x1f801098:
	393	case 0x1f8010a8:
	394	case 0x1f8010b8:
	395	case 0x1f8010c8:
	396	case 0x1f8010e8:
	397	case 0x1f8010f4:
	398	return !is_write;
	399	default:
	400	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	401	}
	402	}
	403	}
	404
323bb280 AL	405	#if defined(HW_DOL) \|\| defined(HW_RVL)
	406	static void lightrec_code_inv(void *ptr, uint32_t len)
	407	{
	408	extern void DCFlushRange(void *ptr, u32 len);
	409	extern void ICInvalidateRange(void *ptr, u32 len);
	410
	411	DCFlushRange(ptr, len);
	412	ICInvalidateRange(ptr, len);
	413	}
	414	#elif defined(HW_WUP)
	415	static void lightrec_code_inv(void *ptr, uint32_t len)
	416	{
	417	wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
	418	}
	419	#endif
	420
6f1edc3c	421	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	422	.cop2_op = cop2_op,
0733c3ab PC	423	.enable_ram = lightrec_enable_ram,
ba3814c1	424	.hw_direct = lightrec_can_hw_direct,
323bb280 AL	425	#if defined(HW_DOL) \|\| defined(HW_RVL) \|\| defined(HW_WUP)
	426	.code_inv = lightrec_code_inv,
	427	#endif
6f1edc3c PC	428	};
	429
	430	static int lightrec_plugin_init(void)
	431	{
	432	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	433	lightrec_map[PSX_MAP_BIOS].address = psxR;
	434	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	435	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	436	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	437
82183d4c PC	438	if (!LIGHTREC_CUSTOM_MAP) {
	439	code_buffer = malloc(CODE_BUFFER_SIZE);
	440	if (!code_buffer)
	441	return -ENOMEM;
	442	}
	443
479d58cf PC	444	if (LIGHTREC_CUSTOM_MAP) {
	445	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	446	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	447	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
	448	}
	449
82183d4c PC	450	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
82183d4c PC	451
6f1edc3c	452	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	453
	454	lightrec_state = lightrec_init(name,
	455	lightrec_map, ARRAY_SIZE(lightrec_map),
	456	&lightrec_ops);
	457
9361a5aa EC	458	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	459	// (uintptr_t) psxM,
	460	// (uintptr_t) psxP,
	461	// (uintptr_t) psxR,
	462	// (uintptr_t) psxH);
6f1edc3c PC	463
	464	#ifndef _WIN32
	465	signal(SIGPIPE, exit);
	466	#endif
	467	return 0;
	468	}
	469
d0abba5d	470	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	471	{
6c62131f	472	struct lightrec_registers *regs;
c174cf6a	473	u32 flags, cycles_pcsx;
6f1edc3c	474
6c62131f	475	regs = lightrec_get_registers(lightrec_state);
6c62131f	476	gen_interupt((psxCP0Regs *)regs->cp0);
c174cf6a	477	cycles_pcsx = next_interupt - psxRegs.cycle;
c174cf6a	478	assert((s32)cycles_pcsx > 0);
2bf88032	479
ba3814c1	480	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	481	block_stepping = block_only;
d0abba5d	482	if (block_only)
c174cf6a	483	cycles_pcsx = 0;
ba3814c1	484
6b02f240	485	if (use_pcsx_interpreter) {
f2100c3d	486	intExecuteBlock(0);
6b02f240	487	} else {
c174cf6a	488	u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx);
ba3814c1	489	if (unlikely(use_lightrec_interpreter)) {
6b02f240	490	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1	491	psxRegs.pc,
c174cf6a	492	cycles_lightrec);
ba3814c1	493	} else {
2bf88032	494	psxRegs.pc = lightrec_execute(lightrec_state,
c174cf6a	495	psxRegs.pc, cycles_lightrec);
ba3814c1	496	}
6f1edc3c	497
c174cf6a	498	lightrec_tansition_to_pcsx(lightrec_state);
6f1edc3c	499
6b02f240	500	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	501
6b02f240	502	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	503	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	504	psxRegs.cycle);
	505	exit(1);
	506	}
6f1edc3c	507
6b02f240	508	if (flags & LIGHTREC_EXIT_SYSCALL)
6c62131f	509	psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
2bf88032	510	}
6f1edc3c	511
6c62131f	512	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	513	/* Handle software interrupts */
6c62131f	514	regs->cp0[13] &= ~0x7c;
6c62131f	515	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	516	}
6f1edc3c PC	517	}
	518
	519	static void lightrec_plugin_execute(void)
	520	{
	521	extern int stop;
	522
	523	while (!stop)
d0abba5d	524	lightrec_plugin_execute_internal(false);
d0abba5d	525	}
d0abba5d	526
f3bc907d	527	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	528	{
d0abba5d	529	lightrec_plugin_execute_internal(true);
6f1edc3c PC	530	}
	531
	532	static void lightrec_plugin_clear(u32 addr, u32 size)
	533	{
8c9468f1 ZC	534	if (addr == 0 && size == UINT32_MAX)
	535	lightrec_invalidate_all(lightrec_state);
	536	else
	537	/* size * 4: PCSX uses DMA units */
	538	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	539	}
6f1edc3c PC	540
20196899	541	static void lightrec_plugin_sync_regs_to_pcsx(void);
	542	static void lightrec_plugin_sync_regs_from_pcsx(void);
	543
	544	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	545	{
7a811716	546	switch (note)
7a811716	547	{
20196899	548	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	549	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	550	/* not used, lightrec calls lightrec_enable_ram() instead */
	551	break;
	552	case R3000ACPU_NOTIFY_BEFORE_SAVE:
	553	lightrec_plugin_sync_regs_to_pcsx();
	554	break;
	555	case R3000ACPU_NOTIFY_AFTER_LOAD:
	556	lightrec_plugin_sync_regs_from_pcsx();
	557	break;
	558	}
7a811716	559	}
630b122b	560
	561	static void lightrec_plugin_apply_config()
	562	{
c174cf6a	563	u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
	564	? Config.cycle_multiplier_override : Config.cycle_multiplier;
	565	assert(cycle_mult);
	566	cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200;
	567	cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult;
630b122b	568	}
7a811716	569
6f1edc3c PC	570	static void lightrec_plugin_shutdown(void)
	571	{
	572	lightrec_destroy(lightrec_state);
82183d4c PC	573
	574	if (!LIGHTREC_CUSTOM_MAP)
	575	free(code_buffer);
6f1edc3c PC	576	}
	577
	578	static void lightrec_plugin_reset(void)
	579	{
0733c3ab PC	580	struct lightrec_registers *regs;
0733c3ab PC	581
0733c3ab PC	582	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	583
03535202 PC	584	/* Invalidate all blocks */
	585	lightrec_invalidate_all(lightrec_state);
	586
	587	/* Reset registers */
	588	memset(regs, 0, sizeof(*regs));
	589
0733c3ab PC	590	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	591	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6f1edc3c PC	592	}
6f1edc3c PC	593
20196899	594	static void lightrec_plugin_sync_regs_from_pcsx(void)
6962f770 PC	595	{
	596	struct lightrec_registers *regs;
	597
	598	regs = lightrec_get_registers(lightrec_state);
	599	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	600	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	601	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	602
	603	lightrec_invalidate_all(lightrec_state);
	604	}
	605
20196899	606	static void lightrec_plugin_sync_regs_to_pcsx(void)
6962f770 PC	607	{
	608	struct lightrec_registers *regs;
	609
	610	regs = lightrec_get_registers(lightrec_state);
	611	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	612	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	613	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	614	}
	615
6f1edc3c PC	616	R3000Acpu psxRec =
	617	{
	618	lightrec_plugin_init,
	619	lightrec_plugin_reset,
	620	lightrec_plugin_execute,
	621	lightrec_plugin_execute_block,
	622	lightrec_plugin_clear,
7a811716	623	lightrec_plugin_notify,
630b122b	624	lightrec_plugin_apply_config,
6f1edc3c PC	625	lightrec_plugin_shutdown,
6f1edc3c PC	626	};