[pcsx_rearmed.git] / libpcsxcore / lightrec / plugin.c

#include <lightrec.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <signal.h>

#include "../cdrom.h"
#include "../gpu.h"
#include "../gte.h"
#include "../mdec.h"
#include "../psxdma.h"
#include "../psxhw.h"
#include "../psxmem.h"
#include "../r3000a.h"
#include "../psxinterpreter.h"
#include "../new_dynarec/events.h"

#include "../frontend/main.h"

#include "mem.h"
#include "plugin.h"

#if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
#endif

#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)

#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#	define LE32TOH(x)	__builtin_bswap32(x)
#	define HTOLE32(x)	__builtin_bswap32(x)
#	define LE16TOH(x)	__builtin_bswap16(x)
#	define HTOLE16(x)	__builtin_bswap16(x)
#else
#	define LE32TOH(x)	(x)
#	define HTOLE32(x)	(x)
#	define LE16TOH(x)	(x)
#	define HTOLE16(x)	(x)
#endif

#ifdef __GNUC__
#	define likely(x)       __builtin_expect(!!(x),1)
#	define unlikely(x)     __builtin_expect(!!(x),0)
#else
#	define likely(x)       (x)
#	define unlikely(x)     (x)
#endif

psxRegisters psxRegs;
Rcnt rcnts[4];

static struct lightrec_state *lightrec_state;

static char *name = "retroarch.exe";

static bool use_lightrec_interpreter;
static bool use_pcsx_interpreter;
static bool block_stepping;

enum my_cp2_opcodes {
	OP_CP2_RTPS		= 0x01,
	OP_CP2_NCLIP		= 0x06,
	OP_CP2_OP		= 0x0c,
	OP_CP2_DPCS		= 0x10,
	OP_CP2_INTPL		= 0x11,
	OP_CP2_MVMVA		= 0x12,
	OP_CP2_NCDS		= 0x13,
	OP_CP2_CDP		= 0x14,
	OP_CP2_NCDT		= 0x16,
	OP_CP2_NCCS		= 0x1b,
	OP_CP2_CC		= 0x1c,
	OP_CP2_NCS		= 0x1e,
	OP_CP2_NCT		= 0x20,
	OP_CP2_SQR		= 0x28,
	OP_CP2_DCPL		= 0x29,
	OP_CP2_DPCT		= 0x2a,
	OP_CP2_AVSZ3		= 0x2d,
	OP_CP2_AVSZ4		= 0x2e,
	OP_CP2_RTPT		= 0x30,
	OP_CP2_GPF		= 0x3d,
	OP_CP2_GPL		= 0x3e,
	OP_CP2_NCCT		= 0x3f,
};

static void (*cp2_ops[])(struct psxCP2Regs *) = {
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_RTPS] = gteRTPS,
	[OP_CP2_NCLIP] = gteNCLIP,
	[OP_CP2_OP] = gteOP,
	[OP_CP2_DPCS] = gteDPCS,
	[OP_CP2_INTPL] = gteINTPL,
	[OP_CP2_MVMVA] = gteMVMVA,
	[OP_CP2_NCDS] = gteNCDS,
	[OP_CP2_CDP] = gteCDP,
	[OP_CP2_NCDT] = gteNCDT,
	[OP_CP2_NCCS] = gteNCCS,
	[OP_CP2_CC] = gteCC,
	[OP_CP2_NCS] = gteNCS,
	[OP_CP2_NCT] = gteNCT,
	[OP_CP2_SQR] = gteSQR,
	[OP_CP2_DCPL] = gteDCPL,
	[OP_CP2_DPCT] = gteDPCT,
	[OP_CP2_AVSZ3] = gteAVSZ3,
	[OP_CP2_AVSZ4] = gteAVSZ4,
	[OP_CP2_RTPT] = gteRTPT,
	[OP_CP2_GPF] = gteGPF,
	[OP_CP2_GPL] = gteGPL,
	[OP_CP2_NCCT] = gteNCCT,
};

static char cache_buf[64 * 1024];

static void cop2_op(struct lightrec_state *state, u32 func)
{
	struct lightrec_registers *regs = lightrec_get_registers(state);

	psxRegs.code = func;

	if (unlikely(!cp2_ops[func & 0x3f])) {
		fprintf(stderr, "Invalid CP2 function %u\n", func);
	} else {
		/* This works because regs->cp2c comes right after regs->cp2d,
		 * so it can be cast to a pcsxCP2Regs pointer. */
		cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	}
}

static bool has_interrupt(void)
{
	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);

	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
		(regs->cp0[12] & 0x401) == 0x401) ||
		(regs->cp0[12] & regs->cp0[13] & 0x0300);
}

static void lightrec_restore_state(struct lightrec_state *state)
{
	lightrec_reset_cycle_count(state, psxRegs.cycle);

	if (block_stepping || has_interrupt())
		lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	else
		lightrec_set_target_cycle_count(state, next_interupt);
}

static void hw_write_byte(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u8 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite8(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_half(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u16 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite16(mem, val);

	lightrec_restore_state(state);
}

static void hw_write_word(struct lightrec_state *state,
			  u32 op, void *host, u32 mem, u32 val)
{
	psxRegs.cycle = lightrec_current_cycle_count(state);

	psxHwWrite32(mem, val);

	lightrec_restore_state(state);
}

static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
{
	u8 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead8(mem);

	lightrec_restore_state(state);

	return val;
}

static u16 hw_read_half(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u16 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead16(mem);

	lightrec_restore_state(state);

	return val;
}

static u32 hw_read_word(struct lightrec_state *state,
			u32 op, void *host, u32 mem)
{
	u32 val;

	psxRegs.cycle = lightrec_current_cycle_count(state);

	val = psxHwRead32(mem);

	lightrec_restore_state(state);

	return val;
}

static struct lightrec_mem_map_ops hw_regs_ops = {
	.sb = hw_write_byte,
	.sh = hw_write_half,
	.sw = hw_write_word,
	.lb = hw_read_byte,
	.lh = hw_read_half,
	.lw = hw_read_word,
};

static u32 cache_ctrl;

static void cache_ctrl_write_word(struct lightrec_state *state,
				  u32 op, void *host, u32 mem, u32 val)
{
	cache_ctrl = val;
}

static u32 cache_ctrl_read_word(struct lightrec_state *state,
				u32 op, void *host, u32 mem)
{
	return cache_ctrl;
}

static struct lightrec_mem_map_ops cache_ctrl_ops = {
	.sw = cache_ctrl_write_word,
	.lw = cache_ctrl_read_word,
};

static struct lightrec_mem_map lightrec_map[] = {
	[PSX_MAP_KERNEL_USER_RAM] = {
		/* Kernel and user memory */
		.pc = 0x00000000,
		.length = 0x200000,
	},
	[PSX_MAP_BIOS] = {
		/* BIOS */
		.pc = 0x1fc00000,
		.length = 0x80000,
	},
	[PSX_MAP_SCRATCH_PAD] = {
		/* Scratch pad */
		.pc = 0x1f800000,
		.length = 0x400,
	},
	[PSX_MAP_PARALLEL_PORT] = {
		/* Parallel port */
		.pc = 0x1f000000,
		.length = 0x10000,
	},
	[PSX_MAP_HW_REGISTERS] = {
		/* Hardware registers */
		.pc = 0x1f801000,
		.length = 0x2000,
		.ops = &hw_regs_ops,
	},
	[PSX_MAP_CACHE_CONTROL] = {
		/* Cache control */
		.pc = 0x5ffe0130,
		.length = 4,
		.ops = &cache_ctrl_ops,
	},

	/* Mirrors of the kernel/user memory */
	[PSX_MAP_MIRROR1] = {
		.pc = 0x00200000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR2] = {
		.pc = 0x00400000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_MIRROR3] = {
		.pc = 0x00600000,
		.length = 0x200000,
		.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	},
	[PSX_MAP_CODE_BUFFER] = {
		.length = CODE_BUFFER_SIZE,
	},
};

static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
{
	if (enable)
		memcpy(psxM, cache_buf, sizeof(cache_buf));
	else
		memcpy(cache_buf, psxM, sizeof(cache_buf));
}

static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
{
	switch (size) {
	case 8:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801800:
		case 0x1f801801:
		case 0x1f801802:
		case 0x1f801803:
			return false;
		default:
			return true;
		}
	case 16:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801044:
		case 0x1f801048:
		case 0x1f80104a:
		case 0x1f80104e:
		case 0x1f801050:
		case 0x1f801054:
		case 0x1f80105a:
		case 0x1f80105e:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
			return false;
		case 0x1f801070:
		case 0x1f801074:
			return !is_write;
		default:
			return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	default:
		switch (kaddr) {
		case 0x1f801040:
		case 0x1f801050:
		case 0x1f801100:
		case 0x1f801104:
		case 0x1f801108:
		case 0x1f801110:
		case 0x1f801114:
		case 0x1f801118:
		case 0x1f801120:
		case 0x1f801124:
		case 0x1f801128:
		case 0x1f801810:
		case 0x1f801814:
		case 0x1f801820:
		case 0x1f801824:
			return false;
		case 0x1f801070:
		case 0x1f801074:
		case 0x1f801088:
		case 0x1f801098:
		case 0x1f8010a8:
		case 0x1f8010b8:
		case 0x1f8010c8:
		case 0x1f8010e8:
		case 0x1f8010f4:
			return !is_write;
		default:
			return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
		}
	}
}

static const struct lightrec_ops lightrec_ops = {
	.cop2_op = cop2_op,
	.enable_ram = lightrec_enable_ram,
	.hw_direct = lightrec_can_hw_direct,
};

static int lightrec_plugin_init(void)
{
	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	lightrec_map[PSX_MAP_BIOS].address = psxR;
	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;

	if (LIGHTREC_CUSTOM_MAP) {
		lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
		lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
		lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
		lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
	}

	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");

	lightrec_state = lightrec_init(name,
			lightrec_map, ARRAY_SIZE(lightrec_map),
			&lightrec_ops);

	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	// 		(uintptr_t) psxM,
	// 		(uintptr_t) psxP,
	// 		(uintptr_t) psxR,
	// 		(uintptr_t) psxH);

#ifndef _WIN32
	signal(SIGPIPE, exit);
#endif
	return 0;
}

static void lightrec_plugin_execute_internal(bool block_only)
{
	struct lightrec_registers *regs;
	u32 flags;

	regs = lightrec_get_registers(lightrec_state);
	gen_interupt((psxCP0Regs *)regs->cp0);

	// step during early boot so that 0x80030000 fastboot hack works
	block_stepping = block_only;
	if (block_only)
		next_interupt = psxRegs.cycle;

	if (use_pcsx_interpreter) {
		intExecuteBlock(0);
	} else {
		lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);

		if (unlikely(use_lightrec_interpreter)) {
			psxRegs.pc = lightrec_run_interpreter(lightrec_state,
							      psxRegs.pc,
							      next_interupt);
		} else {
			psxRegs.pc = lightrec_execute(lightrec_state,
						      psxRegs.pc, next_interupt);
		}

		psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);

		flags = lightrec_exit_flags(lightrec_state);

		if (flags & LIGHTREC_EXIT_SEGFAULT) {
			fprintf(stderr, "Exiting at cycle 0x%08x\n",
				psxRegs.cycle);
			exit(1);
		}

		if (flags & LIGHTREC_EXIT_SYSCALL)
			psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
	}

	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
		/* Handle software interrupts */
		regs->cp0[13] &= ~0x7c;
		psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
	}
}

static void lightrec_plugin_execute(void)
{
	extern int stop;

	while (!stop)
		lightrec_plugin_execute_internal(false);
}

static void lightrec_plugin_execute_block(enum blockExecCaller caller)
{
	lightrec_plugin_execute_internal(true);
}

static void lightrec_plugin_clear(u32 addr, u32 size)
{
	if (addr == 0 && size == UINT32_MAX)
		lightrec_invalidate_all(lightrec_state);
	else
		/* size * 4: PCSX uses DMA units */
		lightrec_invalidate(lightrec_state, addr, size * 4);
}

static void lightrec_plugin_sync_regs_to_pcsx(void);
static void lightrec_plugin_sync_regs_from_pcsx(void);

static void lightrec_plugin_notify(enum R3000Anote note, void *data)
{
	switch (note)
	{
	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
		/* not used, lightrec calls lightrec_enable_ram() instead */
		break;
	case R3000ACPU_NOTIFY_BEFORE_SAVE:
		lightrec_plugin_sync_regs_to_pcsx();
		break;
	case R3000ACPU_NOTIFY_AFTER_LOAD:
		lightrec_plugin_sync_regs_from_pcsx();
		break;
	}
}

static void lightrec_plugin_apply_config()
{
}

static void lightrec_plugin_shutdown(void)
{
	lightrec_destroy(lightrec_state);
}

static void lightrec_plugin_reset(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);

	/* Invalidate all blocks */
	lightrec_invalidate_all(lightrec_state);

	/* Reset registers */
	memset(regs, 0, sizeof(*regs));

	regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
}

static void lightrec_plugin_sync_regs_from_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));

	lightrec_invalidate_all(lightrec_state);
}

static void lightrec_plugin_sync_regs_to_pcsx(void)
{
	struct lightrec_registers *regs;

	regs = lightrec_get_registers(lightrec_state);
	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
}

R3000Acpu psxRec =
{
	lightrec_plugin_init,
	lightrec_plugin_reset,
	lightrec_plugin_execute,
	lightrec_plugin_execute_block,
	lightrec_plugin_clear,
	lightrec_plugin_notify,
	lightrec_plugin_apply_config,
	lightrec_plugin_shutdown,
};
Commit	Line	Data
6f1edc3c PC	1	#include <lightrec.h>
	2	#include <stdbool.h>
	3	#include <stdio.h>
	4	#include <unistd.h>
	5	#include <signal.h>
	6
	7	#include "../cdrom.h"
	8	#include "../gpu.h"
	9	#include "../gte.h"
	10	#include "../mdec.h"
	11	#include "../psxdma.h"
	12	#include "../psxhw.h"
	13	#include "../psxmem.h"
	14	#include "../r3000a.h"
f2100c3d	15	#include "../psxinterpreter.h"
6c62131f	16	#include "../new_dynarec/events.h"
6f1edc3c PC	17
	18	#include "../frontend/main.h"
	19
f8548105	20	#include "mem.h"
70939d49	21	#include "plugin.h"
f8548105	22
46a38bda	23	#if (defined(__arm__) \|\| defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
	24	#error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
	25	#endif
	26
6f1edc3c PC	27	#define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
	28
	29	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	30	# define LE32TOH(x) __builtin_bswap32(x)
	31	# define HTOLE32(x) __builtin_bswap32(x)
	32	# define LE16TOH(x) __builtin_bswap16(x)
	33	# define HTOLE16(x) __builtin_bswap16(x)
	34	#else
	35	# define LE32TOH(x) (x)
	36	# define HTOLE32(x) (x)
	37	# define LE16TOH(x) (x)
	38	# define HTOLE16(x) (x)
	39	#endif
	40
	41	#ifdef __GNUC__
	42	# define likely(x) __builtin_expect(!!(x),1)
	43	# define unlikely(x) __builtin_expect(!!(x),0)
	44	#else
	45	# define likely(x) (x)
	46	# define unlikely(x) (x)
	47	#endif
	48
630b122b	49	psxRegisters psxRegs;
	50	Rcnt rcnts[4];
	51
6f1edc3c PC	52	static struct lightrec_state *lightrec_state;
	53
	54	static char *name = "retroarch.exe";
	55
	56	static bool use_lightrec_interpreter;
6b02f240	57	static bool use_pcsx_interpreter;
6c62131f	58	static bool block_stepping;
6f1edc3c	59
6f1edc3c PC	60	enum my_cp2_opcodes {
	61	OP_CP2_RTPS = 0x01,
	62	OP_CP2_NCLIP = 0x06,
	63	OP_CP2_OP = 0x0c,
	64	OP_CP2_DPCS = 0x10,
	65	OP_CP2_INTPL = 0x11,
	66	OP_CP2_MVMVA = 0x12,
	67	OP_CP2_NCDS = 0x13,
	68	OP_CP2_CDP = 0x14,
	69	OP_CP2_NCDT = 0x16,
	70	OP_CP2_NCCS = 0x1b,
	71	OP_CP2_CC = 0x1c,
	72	OP_CP2_NCS = 0x1e,
	73	OP_CP2_NCT = 0x20,
	74	OP_CP2_SQR = 0x28,
	75	OP_CP2_DCPL = 0x29,
	76	OP_CP2_DPCT = 0x2a,
	77	OP_CP2_AVSZ3 = 0x2d,
	78	OP_CP2_AVSZ4 = 0x2e,
	79	OP_CP2_RTPT = 0x30,
	80	OP_CP2_GPF = 0x3d,
	81	OP_CP2_GPL = 0x3e,
	82	OP_CP2_NCCT = 0x3f,
	83	};
	84
	85	static void (cp2_ops[])(struct psxCP2Regs ) = {
	86	[OP_CP2_RTPS] = gteRTPS,
	87	[OP_CP2_RTPS] = gteRTPS,
	88	[OP_CP2_NCLIP] = gteNCLIP,
	89	[OP_CP2_OP] = gteOP,
	90	[OP_CP2_DPCS] = gteDPCS,
	91	[OP_CP2_INTPL] = gteINTPL,
	92	[OP_CP2_MVMVA] = gteMVMVA,
	93	[OP_CP2_NCDS] = gteNCDS,
	94	[OP_CP2_CDP] = gteCDP,
	95	[OP_CP2_NCDT] = gteNCDT,
	96	[OP_CP2_NCCS] = gteNCCS,
	97	[OP_CP2_CC] = gteCC,
	98	[OP_CP2_NCS] = gteNCS,
	99	[OP_CP2_NCT] = gteNCT,
	100	[OP_CP2_SQR] = gteSQR,
	101	[OP_CP2_DCPL] = gteDCPL,
	102	[OP_CP2_DPCT] = gteDPCT,
	103	[OP_CP2_AVSZ3] = gteAVSZ3,
	104	[OP_CP2_AVSZ4] = gteAVSZ4,
	105	[OP_CP2_RTPT] = gteRTPT,
	106	[OP_CP2_GPF] = gteGPF,
	107	[OP_CP2_GPL] = gteGPL,
	108	[OP_CP2_NCCT] = gteNCCT,
	109	};
	110
	111	static char cache_buf[64 * 1024];
	112
0733c3ab	113	static void cop2_op(struct lightrec_state *state, u32 func)
6f1edc3c	114	{
0733c3ab	115	struct lightrec_registers *regs = lightrec_get_registers(state);
6f1edc3c	116
0733c3ab	117	psxRegs.code = func;
6f1edc3c	118
0733c3ab PC	119	if (unlikely(!cp2_ops[func & 0x3f])) {
	120	fprintf(stderr, "Invalid CP2 function %u\n", func);
	121	} else {
	122	/* This works because regs->cp2c comes right after regs->cp2d,
	123	* so it can be cast to a pcsxCP2Regs pointer. */
	124	cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
	125	}
6f1edc3c PC	126	}
6f1edc3c PC	127
2bf88032 PC	128	static bool has_interrupt(void)
2bf88032 PC	129	{
6ce0b00a PC	130	struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
6ce0b00a PC	131
2bf88032	132	return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
6ce0b00a PC	133	(regs->cp0[12] & 0x401) == 0x401) \|\|
6ce0b00a PC	134	(regs->cp0[12] & regs->cp0[13] & 0x0300);
2bf88032 PC	135	}
2bf88032 PC	136
f4f9f2a4 PC	137	static void lightrec_restore_state(struct lightrec_state *state)
	138	{
	139	lightrec_reset_cycle_count(state, psxRegs.cycle);
2bf88032	140
6c62131f	141	if (block_stepping \|\| has_interrupt())
2bf88032 PC	142	lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
	143	else
	144	lightrec_set_target_cycle_count(state, next_interupt);
f4f9f2a4 PC	145	}
f4f9f2a4 PC	146
6b02f240	147	static void hw_write_byte(struct lightrec_state *state,
6b02f240	148	u32 op, void *host, u32 mem, u8 val)
6f1edc3c PC	149	{
	150	psxRegs.cycle = lightrec_current_cycle_count(state);
	151
	152	psxHwWrite8(mem, val);
6f1edc3c	153
f4f9f2a4	154	lightrec_restore_state(state);
6f1edc3c PC	155	}
6f1edc3c PC	156
6b02f240	157	static void hw_write_half(struct lightrec_state *state,
6b02f240	158	u32 op, void *host, u32 mem, u16 val)
6f1edc3c PC	159	{
	160	psxRegs.cycle = lightrec_current_cycle_count(state);
	161
	162	psxHwWrite16(mem, val);
6f1edc3c	163
f4f9f2a4	164	lightrec_restore_state(state);
6f1edc3c PC	165	}
6f1edc3c PC	166
6b02f240	167	static void hw_write_word(struct lightrec_state *state,
6b02f240	168	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	169	{
	170	psxRegs.cycle = lightrec_current_cycle_count(state);
	171
	172	psxHwWrite32(mem, val);
6f1edc3c	173
f4f9f2a4	174	lightrec_restore_state(state);
6f1edc3c PC	175	}
6f1edc3c PC	176
6b02f240	177	static u8 hw_read_byte(struct lightrec_state state, u32 op, void host, u32 mem)
6f1edc3c PC	178	{
	179	u8 val;
	180
	181	psxRegs.cycle = lightrec_current_cycle_count(state);
	182
6f1edc3c	183	val = psxHwRead8(mem);
f4f9f2a4 PC	184
f4f9f2a4 PC	185	lightrec_restore_state(state);
6f1edc3c PC	186
	187	return val;
	188	}
	189
6b02f240	190	static u16 hw_read_half(struct lightrec_state *state,
6b02f240	191	u32 op, void *host, u32 mem)
6f1edc3c PC	192	{
	193	u16 val;
	194
	195	psxRegs.cycle = lightrec_current_cycle_count(state);
	196
6f1edc3c	197	val = psxHwRead16(mem);
f4f9f2a4 PC	198
f4f9f2a4 PC	199	lightrec_restore_state(state);
6f1edc3c PC	200
	201	return val;
	202	}
	203
6b02f240	204	static u32 hw_read_word(struct lightrec_state *state,
6b02f240	205	u32 op, void *host, u32 mem)
6f1edc3c PC	206	{
	207	u32 val;
	208
	209	psxRegs.cycle = lightrec_current_cycle_count(state);
	210
6f1edc3c	211	val = psxHwRead32(mem);
f4f9f2a4 PC	212
f4f9f2a4 PC	213	lightrec_restore_state(state);
6f1edc3c PC	214
	215	return val;
	216	}
	217
	218	static struct lightrec_mem_map_ops hw_regs_ops = {
	219	.sb = hw_write_byte,
	220	.sh = hw_write_half,
	221	.sw = hw_write_word,
	222	.lb = hw_read_byte,
	223	.lh = hw_read_half,
	224	.lw = hw_read_word,
	225	};
	226
	227	static u32 cache_ctrl;
	228
6b02f240	229	static void cache_ctrl_write_word(struct lightrec_state *state,
6b02f240	230	u32 op, void *host, u32 mem, u32 val)
6f1edc3c PC	231	{
	232	cache_ctrl = val;
	233	}
	234
6b02f240	235	static u32 cache_ctrl_read_word(struct lightrec_state *state,
6b02f240	236	u32 op, void *host, u32 mem)
6f1edc3c PC	237	{
	238	return cache_ctrl;
	239	}
	240
	241	static struct lightrec_mem_map_ops cache_ctrl_ops = {
	242	.sw = cache_ctrl_write_word,
	243	.lw = cache_ctrl_read_word,
	244	};
	245
	246	static struct lightrec_mem_map lightrec_map[] = {
	247	[PSX_MAP_KERNEL_USER_RAM] = {
	248	/* Kernel and user memory */
	249	.pc = 0x00000000,
	250	.length = 0x200000,
	251	},
	252	[PSX_MAP_BIOS] = {
	253	/* BIOS */
	254	.pc = 0x1fc00000,
	255	.length = 0x80000,
	256	},
	257	[PSX_MAP_SCRATCH_PAD] = {
	258	/* Scratch pad */
	259	.pc = 0x1f800000,
	260	.length = 0x400,
	261	},
	262	[PSX_MAP_PARALLEL_PORT] = {
	263	/* Parallel port */
	264	.pc = 0x1f000000,
	265	.length = 0x10000,
	266	},
	267	[PSX_MAP_HW_REGISTERS] = {
	268	/* Hardware registers */
	269	.pc = 0x1f801000,
	270	.length = 0x2000,
	271	.ops = &hw_regs_ops,
	272	},
	273	[PSX_MAP_CACHE_CONTROL] = {
	274	/* Cache control */
	275	.pc = 0x5ffe0130,
	276	.length = 4,
	277	.ops = &cache_ctrl_ops,
	278	},
	279
	280	/* Mirrors of the kernel/user memory */
	281	[PSX_MAP_MIRROR1] = {
	282	.pc = 0x00200000,
	283	.length = 0x200000,
	284	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	285	},
	286	[PSX_MAP_MIRROR2] = {
	287	.pc = 0x00400000,
	288	.length = 0x200000,
	289	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	290	},
	291	[PSX_MAP_MIRROR3] = {
	292	.pc = 0x00600000,
	293	.length = 0x200000,
	294	.mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
	295	},
f8548105 PC	296	[PSX_MAP_CODE_BUFFER] = {
	297	.length = CODE_BUFFER_SIZE,
	298	},
6f1edc3c PC	299	};
6f1edc3c PC	300
0733c3ab PC	301	static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
	302	{
	303	if (enable)
	304	memcpy(psxM, cache_buf, sizeof(cache_buf));
	305	else
	306	memcpy(cache_buf, psxM, sizeof(cache_buf));
	307	}
	308
ba3814c1 PC	309	static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
	310	{
	311	switch (size) {
	312	case 8:
	313	switch (kaddr) {
	314	case 0x1f801040:
	315	case 0x1f801050:
	316	case 0x1f801800:
	317	case 0x1f801801:
	318	case 0x1f801802:
	319	case 0x1f801803:
	320	return false;
	321	default:
	322	return true;
	323	}
	324	case 16:
	325	switch (kaddr) {
	326	case 0x1f801040:
	327	case 0x1f801044:
	328	case 0x1f801048:
	329	case 0x1f80104a:
	330	case 0x1f80104e:
	331	case 0x1f801050:
	332	case 0x1f801054:
	333	case 0x1f80105a:
	334	case 0x1f80105e:
	335	case 0x1f801100:
	336	case 0x1f801104:
	337	case 0x1f801108:
	338	case 0x1f801110:
	339	case 0x1f801114:
	340	case 0x1f801118:
	341	case 0x1f801120:
	342	case 0x1f801124:
	343	case 0x1f801128:
	344	return false;
	345	case 0x1f801070:
	346	case 0x1f801074:
	347	return !is_write;
	348	default:
cdfa3536	349	return kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
ba3814c1 PC	350	}
	351	default:
	352	switch (kaddr) {
	353	case 0x1f801040:
	354	case 0x1f801050:
	355	case 0x1f801100:
	356	case 0x1f801104:
	357	case 0x1f801108:
	358	case 0x1f801110:
	359	case 0x1f801114:
	360	case 0x1f801118:
	361	case 0x1f801120:
	362	case 0x1f801124:
	363	case 0x1f801128:
	364	case 0x1f801810:
	365	case 0x1f801814:
	366	case 0x1f801820:
	367	case 0x1f801824:
	368	return false;
	369	case 0x1f801070:
	370	case 0x1f801074:
	371	case 0x1f801088:
	372	case 0x1f801098:
	373	case 0x1f8010a8:
	374	case 0x1f8010b8:
	375	case 0x1f8010c8:
	376	case 0x1f8010e8:
	377	case 0x1f8010f4:
	378	return !is_write;
	379	default:
	380	return !is_write \|\| kaddr < 0x1f801c00 \|\| kaddr >= 0x1f801e00;
	381	}
	382	}
	383	}
	384
6f1edc3c	385	static const struct lightrec_ops lightrec_ops = {
0733c3ab PC	386	.cop2_op = cop2_op,
0733c3ab PC	387	.enable_ram = lightrec_enable_ram,
ba3814c1	388	.hw_direct = lightrec_can_hw_direct,
6f1edc3c PC	389	};
	390
	391	static int lightrec_plugin_init(void)
	392	{
	393	lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
	394	lightrec_map[PSX_MAP_BIOS].address = psxR;
	395	lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
6ce0b00a	396	lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
6f1edc3c PC	397	lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
6f1edc3c PC	398
479d58cf PC	399	if (LIGHTREC_CUSTOM_MAP) {
	400	lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
	401	lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
	402	lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
f8548105	403	lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
479d58cf PC	404	}
479d58cf PC	405
6f1edc3c	406	use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
6f1edc3c PC	407
	408	lightrec_state = lightrec_init(name,
	409	lightrec_map, ARRAY_SIZE(lightrec_map),
	410	&lightrec_ops);
	411
9361a5aa EC	412	// fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
	413	// (uintptr_t) psxM,
	414	// (uintptr_t) psxP,
	415	// (uintptr_t) psxR,
	416	// (uintptr_t) psxH);
6f1edc3c PC	417
	418	#ifndef _WIN32
	419	signal(SIGPIPE, exit);
	420	#endif
	421	return 0;
	422	}
	423
d0abba5d	424	static void lightrec_plugin_execute_internal(bool block_only)
6f1edc3c	425	{
6c62131f	426	struct lightrec_registers *regs;
6f1edc3c PC	427	u32 flags;
6f1edc3c PC	428
6c62131f	429	regs = lightrec_get_registers(lightrec_state);
6c62131f	430	gen_interupt((psxCP0Regs *)regs->cp0);
2bf88032	431
ba3814c1	432	// step during early boot so that 0x80030000 fastboot hack works
6c62131f	433	block_stepping = block_only;
d0abba5d	434	if (block_only)
ba3814c1 PC	435	next_interupt = psxRegs.cycle;
ba3814c1 PC	436
6b02f240	437	if (use_pcsx_interpreter) {
f2100c3d	438	intExecuteBlock(0);
6b02f240	439	} else {
6b02f240	440	lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
6f1edc3c	441
ba3814c1	442	if (unlikely(use_lightrec_interpreter)) {
6b02f240	443	psxRegs.pc = lightrec_run_interpreter(lightrec_state,
ba3814c1 PC	444	psxRegs.pc,
	445	next_interupt);
	446	} else {
2bf88032 PC	447	psxRegs.pc = lightrec_execute(lightrec_state,
2bf88032 PC	448	psxRegs.pc, next_interupt);
ba3814c1	449	}
6f1edc3c	450
6b02f240	451	psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
6f1edc3c	452
6b02f240	453	flags = lightrec_exit_flags(lightrec_state);
6f1edc3c	454
6b02f240	455	if (flags & LIGHTREC_EXIT_SEGFAULT) {
	456	fprintf(stderr, "Exiting at cycle 0x%08x\n",
	457	psxRegs.cycle);
	458	exit(1);
	459	}
6f1edc3c	460
6b02f240	461	if (flags & LIGHTREC_EXIT_SYSCALL)
6c62131f	462	psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
2bf88032	463	}
6f1edc3c	464
6c62131f	465	if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
6f1edc3c	466	/* Handle software interrupts */
6c62131f	467	regs->cp0[13] &= ~0x7c;
6c62131f	468	psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
6f1edc3c	469	}
6f1edc3c PC	470	}
	471
	472	static void lightrec_plugin_execute(void)
	473	{
	474	extern int stop;
	475
	476	while (!stop)
d0abba5d	477	lightrec_plugin_execute_internal(false);
d0abba5d	478	}
d0abba5d	479
f3bc907d	480	static void lightrec_plugin_execute_block(enum blockExecCaller caller)
d0abba5d	481	{
d0abba5d	482	lightrec_plugin_execute_internal(true);
6f1edc3c PC	483	}
	484
	485	static void lightrec_plugin_clear(u32 addr, u32 size)
	486	{
8c9468f1 ZC	487	if (addr == 0 && size == UINT32_MAX)
	488	lightrec_invalidate_all(lightrec_state);
	489	else
	490	/* size * 4: PCSX uses DMA units */
	491	lightrec_invalidate(lightrec_state, addr, size * 4);
6f1edc3c PC	492	}
6f1edc3c PC	493
20196899	494	static void lightrec_plugin_sync_regs_to_pcsx(void);
	495	static void lightrec_plugin_sync_regs_from_pcsx(void);
	496
	497	static void lightrec_plugin_notify(enum R3000Anote note, void *data)
7a811716	498	{
7a811716	499	switch (note)
7a811716	500	{
20196899	501	case R3000ACPU_NOTIFY_CACHE_ISOLATED:
	502	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
	503	/* not used, lightrec calls lightrec_enable_ram() instead */
	504	break;
	505	case R3000ACPU_NOTIFY_BEFORE_SAVE:
	506	lightrec_plugin_sync_regs_to_pcsx();
	507	break;
	508	case R3000ACPU_NOTIFY_AFTER_LOAD:
	509	lightrec_plugin_sync_regs_from_pcsx();
	510	break;
	511	}
7a811716	512	}
630b122b	513
	514	static void lightrec_plugin_apply_config()
	515	{
	516	}
7a811716	517
6f1edc3c PC	518	static void lightrec_plugin_shutdown(void)
	519	{
	520	lightrec_destroy(lightrec_state);
	521	}
	522
	523	static void lightrec_plugin_reset(void)
	524	{
0733c3ab PC	525	struct lightrec_registers *regs;
0733c3ab PC	526
0733c3ab PC	527	regs = lightrec_get_registers(lightrec_state);
0733c3ab PC	528
03535202 PC	529	/* Invalidate all blocks */
	530	lightrec_invalidate_all(lightrec_state);
	531
	532	/* Reset registers */
	533	memset(regs, 0, sizeof(*regs));
	534
0733c3ab PC	535	regs->cp0[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
0733c3ab PC	536	regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
6f1edc3c PC	537	}
6f1edc3c PC	538
20196899	539	static void lightrec_plugin_sync_regs_from_pcsx(void)
6962f770 PC	540	{
	541	struct lightrec_registers *regs;
	542
	543	regs = lightrec_get_registers(lightrec_state);
	544	memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	545	memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
	546	memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
	547
	548	lightrec_invalidate_all(lightrec_state);
	549	}
	550
20196899	551	static void lightrec_plugin_sync_regs_to_pcsx(void)
6962f770 PC	552	{
	553	struct lightrec_registers *regs;
	554
	555	regs = lightrec_get_registers(lightrec_state);
	556	memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
	557	memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
	558	memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
	559	}
	560
6f1edc3c PC	561	R3000Acpu psxRec =
	562	{
	563	lightrec_plugin_init,
	564	lightrec_plugin_reset,
	565	lightrec_plugin_execute,
	566	lightrec_plugin_execute_block,
	567	lightrec_plugin_clear,
7a811716	568	lightrec_plugin_notify,
630b122b	569	lightrec_plugin_apply_config,
6f1edc3c PC	570	lightrec_plugin_shutdown,
6f1edc3c PC	571	};