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1 | #define HOST_REGS 13 |
2 | #define HOST_CCREG 10 |
3 | #define HOST_BTREG 8 |
4 | #define EXCLUDE_REG 11 |
5 | |
6 | #define HOST_IMM8 1 |
7 | #define HAVE_CMOV_IMM 1 |
8 | #define CORTEX_A8_BRANCH_PREDICTION_HACK 1 |
9 | #define USE_MINI_HT 1 |
10 | //#define REG_PREFETCH 1 |
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11 | #define HAVE_CONDITIONAL_CALL 1 |
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12 | #define RAM_SIZE 0x200000 |
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13 | |
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14 | #ifndef __ARM_ARCH_7A__ |
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15 | //#undef CORTEX_A8_BRANCH_PREDICTION_HACK |
16 | //#undef USE_MINI_HT |
17 | #endif |
18 | |
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19 | #ifndef BASE_ADDR_FIXED |
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20 | #define BASE_ADDR_FIXED 0 |
21 | #endif |
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22 | |
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23 | #define REG_SHIFT 2 |
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24 | |
25 | /* ARM calling convention: |
26 | r0-r3, r12: caller-save |
27 | r4-r11: callee-save */ |
28 | |
29 | #define ARG1_REG 0 |
30 | #define ARG2_REG 1 |
31 | #define ARG3_REG 2 |
32 | #define ARG4_REG 3 |
33 | |
34 | /* GCC register naming convention: |
35 | r10 = sl (base) |
36 | r11 = fp (frame pointer) |
37 | r12 = ip (scratch) |
38 | r13 = sp (stack pointer) |
39 | r14 = lr (link register) |
40 | r15 = pc (program counter) */ |
41 | |
42 | #define FP 11 |
43 | #define LR 14 |
44 | #define HOST_TEMPREG 14 |
45 | |
46 | // Note: FP is set to &dynarec_local when executing generated code. |
47 | // Thus the local variables are actually global and not on the stack. |
48 | |
49 | extern char *invc_ptr; |
50 | |
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51 | #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes |
52 | |
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53 | // Code generator target address |
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54 | #if BASE_ADDR_FIXED |
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55 | // "round" address helpful for debug |
56 | #define BASE_ADDR 0x1000000 |
57 | #else |
58 | extern char translation_cache[1 << TARGET_SIZE_2]; |
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59 | #define BASE_ADDR (u_int)translation_cache |
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60 | #endif |