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1 | #define HOST_REGS 13 |
2 | #define HOST_CCREG 10 |
3 | #define HOST_BTREG 8 |
4 | #define EXCLUDE_REG 11 |
5 | |
6 | #define HOST_IMM8 1 |
7 | #define HAVE_CMOV_IMM 1 |
8 | #define CORTEX_A8_BRANCH_PREDICTION_HACK 1 |
9 | #define USE_MINI_HT 1 |
10 | //#define REG_PREFETCH 1 |
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11 | #define HAVE_CONDITIONAL_CALL 1 |
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12 | #define DISABLE_TLB 1 |
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13 | //#define MUPEN64 |
14 | #define FORCE32 1 |
15 | #define DISABLE_COP1 1 |
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16 | #define PCSX 1 |
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17 | #define RAM_SIZE 0x200000 |
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18 | |
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19 | #ifndef __ARM_ARCH_7A__ |
20 | #define ARMv5_ONLY |
21 | //#undef CORTEX_A8_BRANCH_PREDICTION_HACK |
22 | //#undef USE_MINI_HT |
23 | #endif |
24 | |
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25 | #ifdef FORCE32 |
26 | #define REG_SHIFT 2 |
27 | #else |
28 | #define REG_SHIFT 3 |
29 | #endif |
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30 | |
31 | /* ARM calling convention: |
32 | r0-r3, r12: caller-save |
33 | r4-r11: callee-save */ |
34 | |
35 | #define ARG1_REG 0 |
36 | #define ARG2_REG 1 |
37 | #define ARG3_REG 2 |
38 | #define ARG4_REG 3 |
39 | |
40 | /* GCC register naming convention: |
41 | r10 = sl (base) |
42 | r11 = fp (frame pointer) |
43 | r12 = ip (scratch) |
44 | r13 = sp (stack pointer) |
45 | r14 = lr (link register) |
46 | r15 = pc (program counter) */ |
47 | |
48 | #define FP 11 |
49 | #define LR 14 |
50 | #define HOST_TEMPREG 14 |
51 | |
52 | // Note: FP is set to &dynarec_local when executing generated code. |
53 | // Thus the local variables are actually global and not on the stack. |
54 | |
55 | extern char *invc_ptr; |
56 | |
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57 | #define BASE_ADDR 0x1000000 // Code generator target address |
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58 | #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes |
59 | |
60 | // This is defined in linkage_arm.s, but gcc -O3 likes this better |
61 | #define rdram ((unsigned int *)0x80000000) |