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1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
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2 | * linkage_arm.s for PCSX * |
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3 | * Copyright (C) 2009-2011 Ari64 * |
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4 | * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas * |
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5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
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21 | |
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22 | .global dynarec_local |
23 | .global reg |
24 | .global hi |
25 | .global lo |
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26 | .global reg_cop0 |
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27 | .global reg_cop2d |
28 | .global reg_cop2c |
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29 | .global FCR0 |
30 | .global FCR31 |
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31 | .global next_interupt |
32 | .global cycle_count |
33 | .global last_count |
34 | .global pending_exception |
35 | .global pcaddr |
36 | .global stop |
37 | .global invc_ptr |
38 | .global address |
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39 | .global branch_target |
40 | .global PC |
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41 | .global mini_ht |
42 | .global restore_candidate |
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43 | /* psx */ |
44 | .global psxRegs |
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45 | .global mem_rtab |
46 | .global mem_wtab |
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47 | .global psxH_ptr |
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48 | .global zeromem_ptr |
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49 | .global inv_code_start |
50 | .global inv_code_end |
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51 | .global rcnts |
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52 | |
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53 | .bss |
54 | .align 4 |
55 | .type dynarec_local, %object |
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56 | .size dynarec_local, dynarec_local_end-dynarec_local |
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57 | dynarec_local: |
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58 | .space dynarec_local_end-dynarec_local |
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59 | next_interupt = dynarec_local + 64 |
60 | .type next_interupt, %object |
61 | .size next_interupt, 4 |
62 | cycle_count = next_interupt + 4 |
63 | .type cycle_count, %object |
64 | .size cycle_count, 4 |
65 | last_count = cycle_count + 4 |
66 | .type last_count, %object |
67 | .size last_count, 4 |
68 | pending_exception = last_count + 4 |
69 | .type pending_exception, %object |
70 | .size pending_exception, 4 |
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71 | stop = pending_exception + 4 |
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72 | .type stop, %object |
73 | .size stop, 4 |
74 | invc_ptr = stop + 4 |
75 | .type invc_ptr, %object |
76 | .size invc_ptr, 4 |
77 | address = invc_ptr + 4 |
78 | .type address, %object |
79 | .size address, 4 |
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80 | psxRegs = address + 4 |
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81 | |
82 | /* psxRegs */ |
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83 | .type psxRegs, %object |
84 | .size psxRegs, psxRegs_end-psxRegs |
85 | reg = psxRegs |
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86 | .type reg, %object |
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87 | .size reg, 128 |
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88 | lo = reg + 128 |
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89 | .type lo, %object |
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90 | .size lo, 4 |
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91 | hi = lo + 4 |
92 | .type hi, %object |
93 | .size hi, 4 |
94 | reg_cop0 = hi + 4 |
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95 | .type reg_cop0, %object |
96 | .size reg_cop0, 128 |
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97 | reg_cop2d = reg_cop0 + 128 |
98 | .type reg_cop2d, %object |
99 | .size reg_cop2d, 128 |
100 | reg_cop2c = reg_cop2d + 128 |
101 | .type reg_cop2c, %object |
102 | .size reg_cop2c, 128 |
103 | PC = reg_cop2c + 128 |
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104 | pcaddr = PC |
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105 | .type PC, %object |
106 | .size PC, 4 |
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107 | code = PC + 4 |
108 | .type code, %object |
109 | .size code, 4 |
110 | cycle = code + 4 |
111 | .type cycle, %object |
112 | .size cycle, 4 |
113 | interrupt = cycle + 4 |
114 | .type interrupt, %object |
115 | .size interrupt, 4 |
116 | intCycle = interrupt + 4 |
117 | .type intCycle, %object |
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118 | .size intCycle, 256 |
119 | psxRegs_end = intCycle + 256 |
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120 | |
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121 | rcnts = psxRegs_end |
122 | .type rcnts, %object |
123 | .size rcnts, 7*4*4 |
124 | rcnts_end = rcnts + 7*4*4 |
125 | |
126 | mem_rtab = rcnts_end |
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127 | .type mem_rtab, %object |
128 | .size mem_rtab, 4 |
129 | mem_wtab = mem_rtab + 4 |
130 | .type mem_wtab, %object |
131 | .size mem_wtab, 4 |
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132 | psxH_ptr = mem_wtab + 4 |
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133 | .type psxH_ptr, %object |
134 | .size psxH_ptr, 4 |
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135 | zeromem_ptr = psxH_ptr + 4 |
136 | .type zeromem_ptr, %object |
137 | .size zeromem_ptr, 4 |
138 | inv_code_start = zeromem_ptr + 4 |
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139 | .type inv_code_start, %object |
140 | .size inv_code_start, 4 |
141 | inv_code_end = inv_code_start + 4 |
142 | .type inv_code_end, %object |
143 | .size inv_code_end, 4 |
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144 | branch_target = inv_code_end + 4 |
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145 | .type branch_target, %object |
146 | .size branch_target, 4 |
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147 | align0 = branch_target + 4 /* unused/alignment */ |
148 | .type align0, %object |
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149 | .size align0, 16 |
150 | mini_ht = align0 + 16 |
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151 | .type mini_ht, %object |
152 | .size mini_ht, 256 |
153 | restore_candidate = mini_ht + 256 |
154 | .type restore_candidate, %object |
155 | .size restore_candidate, 512 |
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156 | dynarec_local_end = restore_candidate + 512 |
157 | |
158 | /* unused */ |
159 | FCR0 = align0 |
160 | .type FCR0, %object |
161 | .size FCR0, 4 |
162 | FCR31 = align0 |
163 | .type FCR31, %object |
164 | .size FCR31, 4 |
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165 | |
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166 | .macro load_varadr reg var |
167 | #if defined(__ARM_ARCH_7A__) && !defined(__PIC__) |
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168 | movw \reg, #:lower16:\var |
169 | movt \reg, #:upper16:\var |
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170 | #else |
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171 | ldr \reg, =\var |
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172 | #endif |
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173 | .endm |
174 | |
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175 | .macro mov_16 reg imm |
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176 | #ifdef __ARM_ARCH_7A__ |
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177 | movw \reg, #\imm |
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178 | #else |
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179 | mov \reg, #(\imm & 0x00ff) |
180 | orr \reg, #(\imm & 0xff00) |
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181 | #endif |
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182 | .endm |
183 | |
184 | .macro mov_24 reg imm |
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185 | #ifdef __ARM_ARCH_7A__ |
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186 | movw \reg, #(\imm & 0xffff) |
187 | movt \reg, #(\imm >> 16) |
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188 | #else |
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189 | mov \reg, #(\imm & 0x0000ff) |
190 | orr \reg, #(\imm & 0x00ff00) |
191 | orr \reg, #(\imm & 0xff0000) |
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192 | #endif |
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193 | .endm |
194 | |
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195 | .macro dyna_linker_main |
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196 | /* r0 = virtual target address */ |
197 | /* r1 = instruction to patch */ |
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198 | ldr r3, .jiptr |
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199 | /* get_page */ |
200 | lsr r2, r0, #12 |
201 | mov r6, #4096 |
202 | bic r2, r2, #0xe0000 |
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203 | sub r6, r6, #1 |
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204 | cmp r2, #0x1000 |
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205 | ldr r7, [r1] |
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206 | biclt r2, #0x0e00 |
207 | and r6, r6, r2 |
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208 | cmp r2, #2048 |
209 | add r12, r7, #2 |
210 | orrcs r2, r6, #2048 |
211 | ldr r5, [r3, r2, lsl #2] |
212 | lsl r12, r12, #8 |
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213 | add r6, r1, r12, asr #6 |
214 | mov r8, #0 |
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215 | /* jump_in lookup */ |
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216 | 1: |
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217 | movs r4, r5 |
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218 | beq 2f |
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219 | ldr r3, [r5] |
220 | ldr r5, [r4, #12] |
221 | teq r3, r0 |
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222 | bne 1b |
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223 | ldr r3, [r4, #4] |
224 | ldr r4, [r4, #8] |
225 | tst r3, r3 |
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226 | bne 1b |
227 | teq r4, r6 |
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228 | moveq pc, r4 /* Stale i-cache */ |
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229 | mov r8, r4 |
230 | b 1b /* jump_in may have dupes, continue search */ |
231 | 2: |
232 | tst r8, r8 |
233 | beq 3f /* r0 not in jump_in */ |
234 | |
235 | mov r5, r1 |
236 | mov r1, r6 |
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237 | bl add_link |
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238 | sub r2, r8, r5 |
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239 | and r1, r7, #0xff000000 |
240 | lsl r2, r2, #6 |
241 | sub r1, r1, #2 |
242 | add r1, r1, r2, lsr #8 |
243 | str r1, [r5] |
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244 | mov pc, r8 |
245 | 3: |
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246 | /* hash_table lookup */ |
247 | cmp r2, #2048 |
248 | ldr r3, .jdptr |
249 | eor r4, r0, r0, lsl #16 |
250 | lslcc r2, r0, #9 |
251 | ldr r6, .htptr |
252 | lsr r4, r4, #12 |
253 | lsrcc r2, r2, #21 |
254 | bic r4, r4, #15 |
255 | ldr r5, [r3, r2, lsl #2] |
256 | ldr r7, [r6, r4]! |
257 | teq r7, r0 |
258 | ldreq pc, [r6, #4] |
259 | ldr r7, [r6, #8] |
260 | teq r7, r0 |
261 | ldreq pc, [r6, #12] |
262 | /* jump_dirty lookup */ |
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263 | 6: |
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264 | movs r4, r5 |
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265 | beq 8f |
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266 | ldr r3, [r5] |
267 | ldr r5, [r4, #12] |
268 | teq r3, r0 |
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269 | bne 6b |
270 | 7: |
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271 | ldr r1, [r4, #8] |
272 | /* hash_table insert */ |
273 | ldr r2, [r6] |
274 | ldr r3, [r6, #4] |
275 | str r0, [r6] |
276 | str r1, [r6, #4] |
277 | str r2, [r6, #8] |
278 | str r3, [r6, #12] |
279 | mov pc, r1 |
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280 | 8: |
281 | .endm |
282 | |
283 | .text |
284 | .align 2 |
285 | .global dyna_linker |
286 | .type dyna_linker, %function |
287 | dyna_linker: |
288 | /* r0 = virtual target address */ |
289 | /* r1 = instruction to patch */ |
290 | dyna_linker_main |
291 | |
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292 | mov r4, r0 |
293 | mov r5, r1 |
294 | bl new_recompile_block |
295 | tst r0, r0 |
296 | mov r0, r4 |
297 | mov r1, r5 |
298 | beq dyna_linker |
299 | /* pagefault */ |
300 | mov r1, r0 |
301 | mov r2, #8 |
302 | .size dyna_linker, .-dyna_linker |
303 | .global exec_pagefault |
304 | .type exec_pagefault, %function |
305 | exec_pagefault: |
306 | /* r0 = instruction pointer */ |
307 | /* r1 = fault address */ |
308 | /* r2 = cause */ |
309 | ldr r3, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
310 | mvn r6, #0xF000000F |
311 | ldr r4, [fp, #reg_cop0+16-dynarec_local] /* Context */ |
312 | bic r6, r6, #0x0F800000 |
313 | str r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */ |
314 | orr r3, r3, #2 |
315 | str r1, [fp, #reg_cop0+32-dynarec_local] /* BadVAddr */ |
316 | bic r4, r4, r6 |
317 | str r3, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
318 | and r5, r6, r1, lsr #9 |
319 | str r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */ |
320 | and r1, r1, r6, lsl #9 |
321 | str r1, [fp, #reg_cop0+40-dynarec_local] /* EntryHi */ |
322 | orr r4, r4, r5 |
323 | str r4, [fp, #reg_cop0+16-dynarec_local] /* Context */ |
324 | mov r0, #0x80000000 |
325 | bl get_addr_ht |
326 | mov pc, r0 |
327 | .size exec_pagefault, .-exec_pagefault |
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328 | |
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329 | /* Special dynamic linker for the case where a page fault |
330 | may occur in a branch delay slot */ |
331 | .global dyna_linker_ds |
332 | .type dyna_linker_ds, %function |
333 | dyna_linker_ds: |
334 | /* r0 = virtual target address */ |
335 | /* r1 = instruction to patch */ |
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336 | dyna_linker_main |
337 | |
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338 | mov r4, r0 |
339 | bic r0, r0, #7 |
340 | mov r5, r1 |
341 | orr r0, r0, #1 |
342 | bl new_recompile_block |
343 | tst r0, r0 |
344 | mov r0, r4 |
345 | mov r1, r5 |
346 | beq dyna_linker_ds |
347 | /* pagefault */ |
348 | bic r1, r0, #7 |
349 | mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */ |
350 | sub r0, r1, #4 |
351 | b exec_pagefault |
352 | .size dyna_linker_ds, .-dyna_linker_ds |
353 | .jiptr: |
354 | .word jump_in |
355 | .jdptr: |
356 | .word jump_dirty |
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357 | .htptr: |
358 | .word hash_table |
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359 | |
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360 | .align 2 |
361 | .global jump_vaddr_r0 |
362 | .type jump_vaddr_r0, %function |
363 | jump_vaddr_r0: |
364 | eor r2, r0, r0, lsl #16 |
365 | b jump_vaddr |
366 | .size jump_vaddr_r0, .-jump_vaddr_r0 |
367 | .global jump_vaddr_r1 |
368 | .type jump_vaddr_r1, %function |
369 | jump_vaddr_r1: |
370 | eor r2, r1, r1, lsl #16 |
371 | mov r0, r1 |
372 | b jump_vaddr |
373 | .size jump_vaddr_r1, .-jump_vaddr_r1 |
374 | .global jump_vaddr_r2 |
375 | .type jump_vaddr_r2, %function |
376 | jump_vaddr_r2: |
377 | mov r0, r2 |
378 | eor r2, r2, r2, lsl #16 |
379 | b jump_vaddr |
380 | .size jump_vaddr_r2, .-jump_vaddr_r2 |
381 | .global jump_vaddr_r3 |
382 | .type jump_vaddr_r3, %function |
383 | jump_vaddr_r3: |
384 | eor r2, r3, r3, lsl #16 |
385 | mov r0, r3 |
386 | b jump_vaddr |
387 | .size jump_vaddr_r3, .-jump_vaddr_r3 |
388 | .global jump_vaddr_r4 |
389 | .type jump_vaddr_r4, %function |
390 | jump_vaddr_r4: |
391 | eor r2, r4, r4, lsl #16 |
392 | mov r0, r4 |
393 | b jump_vaddr |
394 | .size jump_vaddr_r4, .-jump_vaddr_r4 |
395 | .global jump_vaddr_r5 |
396 | .type jump_vaddr_r5, %function |
397 | jump_vaddr_r5: |
398 | eor r2, r5, r5, lsl #16 |
399 | mov r0, r5 |
400 | b jump_vaddr |
401 | .size jump_vaddr_r5, .-jump_vaddr_r5 |
402 | .global jump_vaddr_r6 |
403 | .type jump_vaddr_r6, %function |
404 | jump_vaddr_r6: |
405 | eor r2, r6, r6, lsl #16 |
406 | mov r0, r6 |
407 | b jump_vaddr |
408 | .size jump_vaddr_r6, .-jump_vaddr_r6 |
409 | .global jump_vaddr_r8 |
410 | .type jump_vaddr_r8, %function |
411 | jump_vaddr_r8: |
412 | eor r2, r8, r8, lsl #16 |
413 | mov r0, r8 |
414 | b jump_vaddr |
415 | .size jump_vaddr_r8, .-jump_vaddr_r8 |
416 | .global jump_vaddr_r9 |
417 | .type jump_vaddr_r9, %function |
418 | jump_vaddr_r9: |
419 | eor r2, r9, r9, lsl #16 |
420 | mov r0, r9 |
421 | b jump_vaddr |
422 | .size jump_vaddr_r9, .-jump_vaddr_r9 |
423 | .global jump_vaddr_r10 |
424 | .type jump_vaddr_r10, %function |
425 | jump_vaddr_r10: |
426 | eor r2, r10, r10, lsl #16 |
427 | mov r0, r10 |
428 | b jump_vaddr |
429 | .size jump_vaddr_r10, .-jump_vaddr_r10 |
430 | .global jump_vaddr_r12 |
431 | .type jump_vaddr_r12, %function |
432 | jump_vaddr_r12: |
433 | eor r2, r12, r12, lsl #16 |
434 | mov r0, r12 |
435 | b jump_vaddr |
436 | .size jump_vaddr_r12, .-jump_vaddr_r12 |
437 | .global jump_vaddr_r7 |
438 | .type jump_vaddr_r7, %function |
439 | jump_vaddr_r7: |
440 | eor r2, r7, r7, lsl #16 |
441 | add r0, r7, #0 |
442 | .size jump_vaddr_r7, .-jump_vaddr_r7 |
443 | .global jump_vaddr |
444 | .type jump_vaddr, %function |
445 | jump_vaddr: |
446 | ldr r1, .htptr |
447 | mvn r3, #15 |
448 | and r2, r3, r2, lsr #12 |
449 | ldr r2, [r1, r2]! |
450 | teq r2, r0 |
451 | ldreq pc, [r1, #4] |
452 | ldr r2, [r1, #8] |
453 | teq r2, r0 |
454 | ldreq pc, [r1, #12] |
455 | str r10, [fp, #cycle_count-dynarec_local] |
456 | bl get_addr |
457 | ldr r10, [fp, #cycle_count-dynarec_local] |
458 | mov pc, r0 |
459 | .size jump_vaddr, .-jump_vaddr |
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460 | |
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461 | .align 2 |
462 | .global verify_code_ds |
463 | .type verify_code_ds, %function |
464 | verify_code_ds: |
465 | str r8, [fp, #branch_target-dynarec_local] |
466 | .size verify_code_ds, .-verify_code_ds |
467 | .global verify_code_vm |
468 | .type verify_code_vm, %function |
469 | verify_code_vm: |
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470 | .global verify_code |
471 | .type verify_code, %function |
472 | verify_code: |
473 | /* r1 = source */ |
474 | /* r2 = target */ |
475 | /* r3 = length */ |
476 | tst r3, #4 |
477 | mov r4, #0 |
478 | add r3, r1, r3 |
479 | mov r5, #0 |
480 | ldrne r4, [r1], #4 |
481 | mov r12, #0 |
482 | ldrne r5, [r2], #4 |
483 | teq r1, r3 |
484 | beq .D3 |
485 | .D2: |
486 | ldr r7, [r1], #4 |
487 | eor r9, r4, r5 |
488 | ldr r8, [r2], #4 |
489 | orrs r9, r9, r12 |
490 | bne .D4 |
491 | ldr r4, [r1], #4 |
492 | eor r12, r7, r8 |
493 | ldr r5, [r2], #4 |
494 | cmp r1, r3 |
495 | bcc .D2 |
496 | teq r7, r8 |
497 | .D3: |
498 | teqeq r4, r5 |
499 | .D4: |
500 | ldr r8, [fp, #branch_target-dynarec_local] |
501 | moveq pc, lr |
502 | .D5: |
503 | bl get_addr |
504 | mov pc, r0 |
505 | .size verify_code, .-verify_code |
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506 | .size verify_code_vm, .-verify_code_vm |
507 | |
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508 | .align 2 |
509 | .global cc_interrupt |
510 | .type cc_interrupt, %function |
511 | cc_interrupt: |
512 | ldr r0, [fp, #last_count-dynarec_local] |
513 | mov r1, #0 |
514 | mov r2, #0x1fc |
515 | add r10, r0, r10 |
516 | str r1, [fp, #pending_exception-dynarec_local] |
517 | and r2, r2, r10, lsr #17 |
518 | add r3, fp, #restore_candidate-dynarec_local |
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519 | str r10, [fp, #cycle-dynarec_local] /* PCSX cycles */ |
520 | @@ str r10, [fp, #reg_cop0+36-dynarec_local] /* Count */ |
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521 | ldr r4, [r2, r3] |
522 | mov r10, lr |
523 | tst r4, r4 |
524 | bne .E4 |
525 | .E1: |
526 | bl gen_interupt |
527 | mov lr, r10 |
822b27d1 |
528 | ldr r10, [fp, #cycle-dynarec_local] |
57871462 |
529 | ldr r0, [fp, #next_interupt-dynarec_local] |
530 | ldr r1, [fp, #pending_exception-dynarec_local] |
531 | ldr r2, [fp, #stop-dynarec_local] |
532 | str r0, [fp, #last_count-dynarec_local] |
533 | sub r10, r10, r0 |
534 | tst r2, r2 |
b021ee75 |
535 | ldmnefd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
57871462 |
536 | tst r1, r1 |
537 | moveq pc, lr |
538 | .E2: |
539 | ldr r0, [fp, #pcaddr-dynarec_local] |
540 | bl get_addr_ht |
541 | mov pc, r0 |
57871462 |
542 | .E4: |
543 | /* Move 'dirty' blocks to the 'clean' list */ |
544 | lsl r5, r2, #3 |
545 | str r1, [r2, r3] |
546 | .E5: |
547 | lsrs r4, r4, #1 |
548 | mov r0, r5 |
549 | add r5, r5, #1 |
550 | blcs clean_blocks |
551 | tst r5, #31 |
552 | bne .E5 |
553 | b .E1 |
57871462 |
554 | .size cc_interrupt, .-cc_interrupt |
7139f3c8 |
555 | |
57871462 |
556 | .align 2 |
557 | .global do_interrupt |
558 | .type do_interrupt, %function |
559 | do_interrupt: |
560 | ldr r0, [fp, #pcaddr-dynarec_local] |
561 | bl get_addr_ht |
57871462 |
562 | add r10, r10, #2 |
563 | mov pc, r0 |
564 | .size do_interrupt, .-do_interrupt |
fca1aef2 |
565 | |
57871462 |
566 | .align 2 |
567 | .global fp_exception |
568 | .type fp_exception, %function |
569 | fp_exception: |
570 | mov r2, #0x10000000 |
571 | .E7: |
572 | ldr r1, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
573 | mov r3, #0x80000000 |
574 | str r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */ |
575 | orr r1, #2 |
576 | add r2, r2, #0x2c |
577 | str r1, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
578 | str r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */ |
7139f3c8 |
579 | add r0, r3, #0x80 |
57871462 |
580 | bl get_addr_ht |
581 | mov pc, r0 |
582 | .size fp_exception, .-fp_exception |
583 | .align 2 |
584 | .global fp_exception_ds |
585 | .type fp_exception_ds, %function |
586 | fp_exception_ds: |
587 | mov r2, #0x90000000 /* Set high bit if delay slot */ |
588 | b .E7 |
589 | .size fp_exception_ds, .-fp_exception_ds |
7139f3c8 |
590 | |
57871462 |
591 | .align 2 |
592 | .global jump_syscall |
593 | .type jump_syscall, %function |
594 | jump_syscall: |
595 | ldr r1, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
596 | mov r3, #0x80000000 |
597 | str r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */ |
598 | orr r1, #2 |
599 | mov r2, #0x20 |
600 | str r1, [fp, #reg_cop0+48-dynarec_local] /* Status */ |
601 | str r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */ |
7139f3c8 |
602 | add r0, r3, #0x80 |
57871462 |
603 | bl get_addr_ht |
604 | mov pc, r0 |
605 | .size jump_syscall, .-jump_syscall |
7139f3c8 |
606 | .align 2 |
607 | |
608 | .align 2 |
609 | .global jump_syscall_hle |
610 | .type jump_syscall_hle, %function |
611 | jump_syscall_hle: |
612 | str r0, [fp, #pcaddr-dynarec_local] /* PC must be set to EPC for psxException */ |
613 | ldr r2, [fp, #last_count-dynarec_local] |
614 | mov r1, #0 /* in delay slot */ |
615 | add r2, r2, r10 |
616 | mov r0, #0x20 /* cause */ |
617 | str r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */ |
7139f3c8 |
618 | bl psxException |
619 | |
620 | /* note: psxException might do recorsive recompiler call from it's HLE code, |
621 | * so be ready for this */ |
822b27d1 |
622 | pcsx_return: |
623 | ldr r1, [fp, #next_interupt-dynarec_local] |
624 | ldr r10, [fp, #cycle-dynarec_local] |
7139f3c8 |
625 | ldr r0, [fp, #pcaddr-dynarec_local] |
822b27d1 |
626 | sub r10, r10, r1 |
627 | str r1, [fp, #last_count-dynarec_local] |
7139f3c8 |
628 | bl get_addr_ht |
629 | mov pc, r0 |
630 | .size jump_syscall_hle, .-jump_syscall_hle |
631 | |
632 | .align 2 |
633 | .global jump_hlecall |
634 | .type jump_hlecall, %function |
635 | jump_hlecall: |
636 | ldr r2, [fp, #last_count-dynarec_local] |
637 | str r0, [fp, #pcaddr-dynarec_local] |
7139f3c8 |
638 | add r2, r2, r10 |
822b27d1 |
639 | adr lr, pcsx_return |
0d16cda2 |
640 | str r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */ |
67ba0fb4 |
641 | bx r1 |
7139f3c8 |
642 | .size jump_hlecall, .-jump_hlecall |
643 | |
0d16cda2 |
644 | .align 2 |
645 | .global jump_intcall |
646 | .type jump_intcall, %function |
647 | jump_intcall: |
648 | ldr r2, [fp, #last_count-dynarec_local] |
649 | str r0, [fp, #pcaddr-dynarec_local] |
650 | add r2, r2, r10 |
651 | adr lr, pcsx_return |
652 | str r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */ |
653 | b execI |
654 | .size jump_hlecall, .-jump_hlecall |
655 | |
7139f3c8 |
656 | new_dyna_leave: |
657 | .align 2 |
658 | .global new_dyna_leave |
659 | .type new_dyna_leave, %function |
660 | ldr r0, [fp, #last_count-dynarec_local] |
661 | add r12, fp, #28 |
662 | add r10, r0, r10 |
822b27d1 |
663 | str r10, [fp, #cycle-dynarec_local] |
b021ee75 |
664 | ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
7139f3c8 |
665 | .size new_dyna_leave, .-new_dyna_leave |
666 | |
0bbd1454 |
667 | .align 2 |
668 | .global invalidate_addr_r0 |
669 | .type invalidate_addr_r0, %function |
670 | invalidate_addr_r0: |
671 | stmia fp, {r0, r1, r2, r3, r12, lr} |
0bbd1454 |
672 | b invalidate_addr_call |
673 | .size invalidate_addr_r0, .-invalidate_addr_r0 |
674 | .align 2 |
675 | .global invalidate_addr_r1 |
676 | .type invalidate_addr_r1, %function |
677 | invalidate_addr_r1: |
678 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
679 | mov r0, r1 |
0bbd1454 |
680 | b invalidate_addr_call |
681 | .size invalidate_addr_r1, .-invalidate_addr_r1 |
682 | .align 2 |
683 | .global invalidate_addr_r2 |
684 | .type invalidate_addr_r2, %function |
685 | invalidate_addr_r2: |
686 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
687 | mov r0, r2 |
0bbd1454 |
688 | b invalidate_addr_call |
689 | .size invalidate_addr_r2, .-invalidate_addr_r2 |
690 | .align 2 |
691 | .global invalidate_addr_r3 |
692 | .type invalidate_addr_r3, %function |
693 | invalidate_addr_r3: |
694 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
695 | mov r0, r3 |
0bbd1454 |
696 | b invalidate_addr_call |
697 | .size invalidate_addr_r3, .-invalidate_addr_r3 |
698 | .align 2 |
699 | .global invalidate_addr_r4 |
700 | .type invalidate_addr_r4, %function |
701 | invalidate_addr_r4: |
702 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
703 | mov r0, r4 |
0bbd1454 |
704 | b invalidate_addr_call |
705 | .size invalidate_addr_r4, .-invalidate_addr_r4 |
706 | .align 2 |
707 | .global invalidate_addr_r5 |
708 | .type invalidate_addr_r5, %function |
709 | invalidate_addr_r5: |
710 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
711 | mov r0, r5 |
0bbd1454 |
712 | b invalidate_addr_call |
713 | .size invalidate_addr_r5, .-invalidate_addr_r5 |
714 | .align 2 |
715 | .global invalidate_addr_r6 |
716 | .type invalidate_addr_r6, %function |
717 | invalidate_addr_r6: |
718 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
719 | mov r0, r6 |
0bbd1454 |
720 | b invalidate_addr_call |
721 | .size invalidate_addr_r6, .-invalidate_addr_r6 |
722 | .align 2 |
723 | .global invalidate_addr_r7 |
724 | .type invalidate_addr_r7, %function |
725 | invalidate_addr_r7: |
726 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
727 | mov r0, r7 |
0bbd1454 |
728 | b invalidate_addr_call |
729 | .size invalidate_addr_r7, .-invalidate_addr_r7 |
730 | .align 2 |
731 | .global invalidate_addr_r8 |
732 | .type invalidate_addr_r8, %function |
733 | invalidate_addr_r8: |
734 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
735 | mov r0, r8 |
0bbd1454 |
736 | b invalidate_addr_call |
737 | .size invalidate_addr_r8, .-invalidate_addr_r8 |
738 | .align 2 |
739 | .global invalidate_addr_r9 |
740 | .type invalidate_addr_r9, %function |
741 | invalidate_addr_r9: |
742 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
743 | mov r0, r9 |
0bbd1454 |
744 | b invalidate_addr_call |
745 | .size invalidate_addr_r9, .-invalidate_addr_r9 |
746 | .align 2 |
747 | .global invalidate_addr_r10 |
748 | .type invalidate_addr_r10, %function |
749 | invalidate_addr_r10: |
750 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
751 | mov r0, r10 |
0bbd1454 |
752 | b invalidate_addr_call |
753 | .size invalidate_addr_r10, .-invalidate_addr_r10 |
754 | .align 2 |
755 | .global invalidate_addr_r12 |
756 | .type invalidate_addr_r12, %function |
757 | invalidate_addr_r12: |
758 | stmia fp, {r0, r1, r2, r3, r12, lr} |
9be4ba64 |
759 | mov r0, r12 |
0bbd1454 |
760 | .size invalidate_addr_r12, .-invalidate_addr_r12 |
761 | .align 2 |
762 | .global invalidate_addr_call |
763 | .type invalidate_addr_call, %function |
764 | invalidate_addr_call: |
9be4ba64 |
765 | ldr r12, [fp, #inv_code_start-dynarec_local] |
766 | ldr lr, [fp, #inv_code_end-dynarec_local] |
767 | cmp r0, r12 |
768 | cmpcs lr, r0 |
769 | blcc invalidate_addr |
0bbd1454 |
770 | ldmia fp, {r0, r1, r2, r3, r12, pc} |
771 | .size invalidate_addr_call, .-invalidate_addr_call |
772 | |
57871462 |
773 | .align 2 |
774 | .global new_dyna_start |
775 | .type new_dyna_start, %function |
776 | new_dyna_start: |
b021ee75 |
777 | /* ip is stored to conform EABI alignment */ |
778 | stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
c67af2ac |
779 | load_varadr fp, dynarec_local |
7139f3c8 |
780 | ldr r0, [fp, #pcaddr-dynarec_local] |
7139f3c8 |
781 | bl get_addr_ht |
782 | ldr r1, [fp, #next_interupt-dynarec_local] |
822b27d1 |
783 | ldr r10, [fp, #cycle-dynarec_local] |
7139f3c8 |
784 | str r1, [fp, #last_count-dynarec_local] |
785 | sub r10, r10, r1 |
786 | mov pc, r0 |
57871462 |
787 | .size new_dyna_start, .-new_dyna_start |
7139f3c8 |
788 | |
7e605697 |
789 | /* --------------------------------------- */ |
7139f3c8 |
790 | |
7e605697 |
791 | .align 2 |
c6c3b1b3 |
792 | .global jump_handler_read8 |
793 | .global jump_handler_read16 |
794 | .global jump_handler_read32 |
b96d3df7 |
795 | .global jump_handler_write8 |
796 | .global jump_handler_write16 |
797 | .global jump_handler_write32 |
798 | .global jump_handler_write_h |
799 | .global jump_handle_swl |
800 | .global jump_handle_swr |
b1be1eee |
801 | .global rcnt0_read_count_m0 |
802 | .global rcnt0_read_count_m1 |
803 | .global rcnt1_read_count_m0 |
804 | .global rcnt1_read_count_m1 |
805 | .global rcnt2_read_count_m0 |
806 | .global rcnt2_read_count_m1 |
7139f3c8 |
807 | |
c6c3b1b3 |
808 | |
809 | .macro pcsx_read_mem readop tab_shift |
810 | /* r0 = address, r1 = handler_tab, r2 = cycles */ |
811 | lsl r3, r0, #20 |
812 | lsr r3, #(20+\tab_shift) |
813 | ldr r12, [fp, #last_count-dynarec_local] |
814 | ldr r1, [r1, r3, lsl #2] |
815 | add r2, r2, r12 |
816 | lsls r1, #1 |
817 | .if \tab_shift == 1 |
818 | lsl r3, #1 |
819 | \readop r0, [r1, r3] |
820 | .else |
821 | \readop r0, [r1, r3, lsl #\tab_shift] |
822 | .endif |
823 | movcc pc, lr |
824 | str r2, [fp, #cycle-dynarec_local] |
825 | bx r1 |
826 | .endm |
827 | |
828 | jump_handler_read8: |
829 | add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
830 | pcsx_read_mem ldrccb, 0 |
831 | |
832 | jump_handler_read16: |
833 | add r1, #0x1000/4*4 @ shift to r16 part |
834 | pcsx_read_mem ldrcch, 1 |
835 | |
836 | jump_handler_read32: |
837 | pcsx_read_mem ldrcc, 2 |
838 | |
b96d3df7 |
839 | |
840 | .macro pcsx_write_mem wrtop tab_shift |
841 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */ |
842 | lsl r12,r0, #20 |
843 | lsr r12, #(20+\tab_shift) |
844 | ldr r3, [r3, r12, lsl #2] |
845 | str r0, [fp, #address-dynarec_local] @ some handlers still need it.. |
846 | lsls r3, #1 |
847 | mov r0, r2 @ cycle return in case of direct store |
848 | .if \tab_shift == 1 |
849 | lsl r12, #1 |
850 | \wrtop r1, [r3, r12] |
851 | .else |
852 | \wrtop r1, [r3, r12, lsl #\tab_shift] |
853 | .endif |
854 | movcc pc, lr |
855 | ldr r12, [fp, #last_count-dynarec_local] |
856 | mov r0, r1 |
857 | add r2, r2, r12 |
858 | push {r2, lr} |
859 | str r2, [fp, #cycle-dynarec_local] |
860 | blx r3 |
861 | |
862 | ldr r0, [fp, #next_interupt-dynarec_local] |
863 | pop {r2, r3} |
864 | str r0, [fp, #last_count-dynarec_local] |
865 | sub r0, r2, r0 |
866 | bx r3 |
867 | .endm |
868 | |
869 | jump_handler_write8: |
870 | add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
871 | pcsx_write_mem strccb, 0 |
872 | |
873 | jump_handler_write16: |
874 | add r3, #0x1000/4*4 @ shift to r16 part |
875 | pcsx_write_mem strcch, 1 |
876 | |
877 | jump_handler_write32: |
878 | pcsx_write_mem strcc, 2 |
879 | |
880 | jump_handler_write_h: |
881 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler */ |
882 | ldr r12, [fp, #last_count-dynarec_local] |
883 | str r0, [fp, #address-dynarec_local] @ some handlers still need it.. |
884 | add r2, r2, r12 |
885 | mov r0, r1 |
886 | push {r2, lr} |
887 | str r2, [fp, #cycle-dynarec_local] |
888 | blx r3 |
889 | |
890 | ldr r0, [fp, #next_interupt-dynarec_local] |
891 | pop {r2, r3} |
892 | str r0, [fp, #last_count-dynarec_local] |
893 | sub r0, r2, r0 |
894 | bx r3 |
895 | |
896 | jump_handle_swl: |
897 | /* r0 = address, r1 = data, r2 = cycles */ |
898 | ldr r3, [fp, #mem_wtab-dynarec_local] |
899 | mov r12,r0,lsr #12 |
900 | ldr r3, [r3, r12, lsl #2] |
901 | lsls r3, #1 |
902 | bcs 4f |
903 | add r3, r0, r3 |
904 | mov r0, r2 |
905 | tst r3, #2 |
906 | beq 101f |
907 | tst r3, #1 |
908 | beq 2f |
909 | 3: |
910 | str r1, [r3, #-3] |
911 | bx lr |
912 | 2: |
913 | lsr r2, r1, #8 |
914 | lsr r1, #24 |
915 | strh r2, [r3, #-2] |
916 | strb r1, [r3] |
917 | bx lr |
918 | 101: |
919 | tst r3, #1 |
920 | lsrne r1, #16 @ 1 |
921 | lsreq r12, r1, #24 @ 0 |
922 | strneh r1, [r3, #-1] |
923 | streqb r12, [r3] |
924 | bx lr |
925 | 4: |
926 | mov r0, r2 |
63cb0298 |
927 | @ b abort |
b96d3df7 |
928 | bx lr @ TODO? |
929 | |
930 | |
931 | jump_handle_swr: |
932 | /* r0 = address, r1 = data, r2 = cycles */ |
933 | ldr r3, [fp, #mem_wtab-dynarec_local] |
934 | mov r12,r0,lsr #12 |
935 | ldr r3, [r3, r12, lsl #2] |
936 | lsls r3, #1 |
937 | bcs 4f |
938 | add r3, r0, r3 |
939 | and r12,r3, #3 |
940 | mov r0, r2 |
941 | cmp r12,#2 |
942 | strgtb r1, [r3] @ 3 |
943 | streqh r1, [r3] @ 2 |
944 | cmp r12,#1 |
945 | strlt r1, [r3] @ 0 |
946 | bxne lr |
947 | lsr r2, r1, #8 @ 1 |
948 | strb r1, [r3] |
949 | strh r2, [r3, #1] |
950 | bx lr |
951 | 4: |
952 | mov r0, r2 |
63cb0298 |
953 | @ b abort |
b96d3df7 |
954 | bx lr @ TODO? |
955 | |
956 | |
b1be1eee |
957 | .macro rcntx_read_mode0 num |
958 | /* r0 = address, r2 = cycles */ |
959 | ldr r3, [fp, #rcnts-dynarec_local+6*4+7*4*\num] @ cycleStart |
960 | mov r0, r2, lsl #16 |
961 | sub r0, r3, lsl #16 |
962 | lsr r0, #16 |
963 | bx lr |
964 | .endm |
965 | |
966 | rcnt0_read_count_m0: |
967 | rcntx_read_mode0 0 |
968 | |
969 | rcnt1_read_count_m0: |
970 | rcntx_read_mode0 1 |
971 | |
972 | rcnt2_read_count_m0: |
973 | rcntx_read_mode0 2 |
974 | |
975 | rcnt0_read_count_m1: |
976 | /* r0 = address, r2 = cycles */ |
977 | ldr r3, [fp, #rcnts-dynarec_local+6*4+7*4*0] @ cycleStart |
978 | mov_16 r1, 0x3334 |
979 | sub r2, r2, r3 |
980 | mul r0, r1, r2 @ /= 5 |
981 | lsr r0, #16 |
982 | bx lr |
983 | |
984 | rcnt1_read_count_m1: |
985 | /* r0 = address, r2 = cycles */ |
986 | ldr r3, [fp, #rcnts-dynarec_local+6*4+7*4*1] |
987 | mov_24 r1, 0x1e6cde |
988 | sub r2, r2, r3 |
989 | umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd |
990 | bx lr |
991 | |
992 | rcnt2_read_count_m1: |
993 | /* r0 = address, r2 = cycles */ |
994 | ldr r3, [fp, #rcnts-dynarec_local+6*4+7*4*2] |
995 | mov r0, r2, lsl #16-3 |
996 | sub r0, r3, lsl #16-3 |
997 | lsr r0, #16 @ /= 8 |
998 | bx lr |
999 | |
7e605697 |
1000 | @ vim:filetype=armasm |