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1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
7e605697 |
2 | * linkage_arm.s for PCSX * |
0bbd1454 |
3 | * Copyright (C) 2009-2011 Ari64 * |
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4 | * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas * |
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5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
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21 | |
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22 | #include "arm_features.h" |
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23 | #include "new_dynarec_config.h" |
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24 | #include "linkage_offsets.h" |
25 | |
26 | |
27 | #ifdef __MACH__ |
28 | #define dynarec_local ESYM(dynarec_local) |
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29 | #define add_jump_out ESYM(add_jump_out) |
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30 | #define new_recompile_block ESYM(new_recompile_block) |
31 | #define get_addr ESYM(get_addr) |
32 | #define get_addr_ht ESYM(get_addr_ht) |
33 | #define clean_blocks ESYM(clean_blocks) |
34 | #define gen_interupt ESYM(gen_interupt) |
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35 | #define invalidate_addr ESYM(invalidate_addr) |
81dbbf4c |
36 | #define gteCheckStallRaw ESYM(gteCheckStallRaw) |
d1150cd6 |
37 | #define psxException ESYM(psxException) |
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38 | #endif |
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39 | |
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40 | .bss |
41 | .align 4 |
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42 | .global dynarec_local |
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43 | .type dynarec_local, %object |
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44 | .size dynarec_local, LO_dynarec_local_size |
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45 | dynarec_local: |
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46 | .space LO_dynarec_local_size |
47 | |
48 | #define DRC_VAR_(name, vname, size_) \ |
49 | vname = dynarec_local + LO_##name; \ |
50 | .global vname; \ |
51 | .type vname, %object; \ |
52 | .size vname, size_ |
53 | |
54 | #define DRC_VAR(name, size_) \ |
55 | DRC_VAR_(name, ESYM(name), size_) |
56 | |
57 | DRC_VAR(next_interupt, 4) |
58 | DRC_VAR(cycle_count, 4) |
59 | DRC_VAR(last_count, 4) |
60 | DRC_VAR(pending_exception, 4) |
61 | DRC_VAR(stop, 4) |
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62 | DRC_VAR(branch_target, 4) |
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63 | DRC_VAR(address, 4) |
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64 | DRC_VAR(hack_addr, 4) |
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65 | DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs) |
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66 | |
67 | /* psxRegs */ |
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68 | @DRC_VAR(reg, 128) |
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69 | DRC_VAR(lo, 4) |
70 | DRC_VAR(hi, 4) |
71 | DRC_VAR(reg_cop0, 128) |
72 | DRC_VAR(reg_cop2d, 128) |
73 | DRC_VAR(reg_cop2c, 128) |
74 | DRC_VAR(pcaddr, 4) |
75 | @DRC_VAR(code, 4) |
76 | @DRC_VAR(cycle, 4) |
77 | @DRC_VAR(interrupt, 4) |
78 | @DRC_VAR(intCycle, 256) |
79 | |
80 | DRC_VAR(rcnts, 7*4*4) |
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81 | DRC_VAR(inv_code_start, 4) |
82 | DRC_VAR(inv_code_end, 4) |
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83 | DRC_VAR(mem_rtab, 4) |
84 | DRC_VAR(mem_wtab, 4) |
85 | DRC_VAR(psxH_ptr, 4) |
86 | DRC_VAR(zeromem_ptr, 4) |
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87 | DRC_VAR(invc_ptr, 4) |
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88 | DRC_VAR(scratch_buf_ptr, 4) |
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89 | DRC_VAR(ram_offset, 4) |
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90 | DRC_VAR(mini_ht, 256) |
91 | DRC_VAR(restore_candidate, 512) |
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92 | |
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93 | |
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94 | #ifdef TEXRELS_FORBIDDEN |
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95 | .data |
96 | .align 2 |
97 | ptr_jump_in: |
98 | .word ESYM(jump_in) |
99 | ptr_jump_dirty: |
100 | .word ESYM(jump_dirty) |
101 | ptr_hash_table: |
102 | .word ESYM(hash_table) |
103 | #endif |
104 | |
105 | |
106 | .syntax unified |
107 | .text |
108 | .align 2 |
109 | |
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110 | #ifndef HAVE_ARMV5 |
111 | .macro blx rd |
112 | mov lr, pc |
113 | bx \rd |
114 | .endm |
115 | #endif |
116 | |
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117 | .macro load_varadr reg var |
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118 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
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119 | movw \reg, #:lower16:(\var-(1678f+8)) |
120 | movt \reg, #:upper16:(\var-(1678f+8)) |
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121 | 1678: |
122 | add \reg, pc |
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123 | #elif defined(HAVE_ARMV7) && !defined(__PIC__) |
124 | movw \reg, #:lower16:\var |
125 | movt \reg, #:upper16:\var |
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126 | #else |
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127 | ldr \reg, =\var |
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128 | #endif |
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129 | .endm |
130 | |
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131 | .macro load_varadr_ext reg var |
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132 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
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133 | movw \reg, #:lower16:(ptr_\var-(1678f+8)) |
134 | movt \reg, #:upper16:(ptr_\var-(1678f+8)) |
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135 | 1678: |
136 | ldr \reg, [pc, \reg] |
137 | #else |
138 | load_varadr \reg \var |
139 | #endif |
140 | .endm |
141 | |
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142 | .macro mov_16 reg imm |
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143 | #ifdef HAVE_ARMV7 |
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144 | movw \reg, #\imm |
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145 | #else |
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146 | mov \reg, #(\imm & 0x00ff) |
147 | orr \reg, #(\imm & 0xff00) |
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148 | #endif |
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149 | .endm |
150 | |
151 | .macro mov_24 reg imm |
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152 | #ifdef HAVE_ARMV7 |
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153 | movw \reg, #(\imm & 0xffff) |
154 | movt \reg, #(\imm >> 16) |
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155 | #else |
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156 | mov \reg, #(\imm & 0x0000ff) |
157 | orr \reg, #(\imm & 0x00ff00) |
158 | orr \reg, #(\imm & 0xff0000) |
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159 | #endif |
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160 | .endm |
161 | |
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162 | /* r0 = virtual target address */ |
163 | /* r1 = instruction to patch */ |
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164 | .macro dyna_linker_main |
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165 | #ifndef NO_WRITE_EXEC |
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166 | load_varadr_ext r3, jump_in |
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167 | /* get_page */ |
168 | lsr r2, r0, #12 |
169 | mov r6, #4096 |
170 | bic r2, r2, #0xe0000 |
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171 | sub r6, r6, #1 |
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172 | cmp r2, #0x1000 |
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173 | ldr r7, [r1] |
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174 | biclt r2, #0x0e00 |
175 | and r6, r6, r2 |
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176 | cmp r2, #2048 |
177 | add r12, r7, #2 |
178 | orrcs r2, r6, #2048 |
179 | ldr r5, [r3, r2, lsl #2] |
180 | lsl r12, r12, #8 |
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181 | add r6, r1, r12, asr #6 /* old target */ |
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182 | mov r8, #0 |
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183 | /* jump_in lookup */ |
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184 | 1: |
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185 | movs r4, r5 |
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186 | beq 2f |
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187 | ldr r3, [r5] /* ll_entry .vaddr */ |
188 | ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */ |
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189 | teq r3, r0 |
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190 | bne 1b |
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191 | teq r4, r6 |
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192 | moveq pc, r4 /* Stale i-cache */ |
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193 | mov r8, r4 |
194 | b 1b /* jump_in may have dupes, continue search */ |
195 | 2: |
196 | tst r8, r8 |
197 | beq 3f /* r0 not in jump_in */ |
198 | |
199 | mov r5, r1 |
200 | mov r1, r6 |
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201 | bl add_jump_out |
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202 | sub r2, r8, r5 |
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203 | and r1, r7, #0xff000000 |
204 | lsl r2, r2, #6 |
205 | sub r1, r1, #2 |
206 | add r1, r1, r2, lsr #8 |
207 | str r1, [r5] |
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208 | mov pc, r8 |
209 | 3: |
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210 | /* hash_table lookup */ |
211 | cmp r2, #2048 |
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212 | load_varadr_ext r3, jump_dirty |
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213 | eor r4, r0, r0, lsl #16 |
214 | lslcc r2, r0, #9 |
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215 | load_varadr_ext r6, hash_table |
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216 | lsr r4, r4, #12 |
217 | lsrcc r2, r2, #21 |
218 | bic r4, r4, #15 |
219 | ldr r5, [r3, r2, lsl #2] |
220 | ldr r7, [r6, r4]! |
221 | teq r7, r0 |
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222 | ldreq pc, [r6, #8] |
223 | ldr r7, [r6, #4] |
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224 | teq r7, r0 |
225 | ldreq pc, [r6, #12] |
226 | /* jump_dirty lookup */ |
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227 | 6: |
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228 | movs r4, r5 |
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229 | beq 8f |
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230 | ldr r3, [r5] |
231 | ldr r5, [r4, #12] |
232 | teq r3, r0 |
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233 | bne 6b |
234 | 7: |
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235 | ldr r1, [r4, #8] |
236 | /* hash_table insert */ |
237 | ldr r2, [r6] |
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238 | ldr r3, [r6, #8] |
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239 | str r0, [r6] |
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240 | str r1, [r6, #8] |
241 | str r2, [r6, #4] |
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242 | str r3, [r6, #12] |
243 | mov pc, r1 |
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244 | 8: |
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245 | #else |
246 | /* XXX: should be able to do better than this... */ |
247 | bl get_addr_ht |
248 | mov pc, r0 |
249 | #endif |
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250 | .endm |
251 | |
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252 | |
253 | FUNCTION(dyna_linker): |
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254 | /* r0 = virtual target address */ |
255 | /* r1 = instruction to patch */ |
256 | dyna_linker_main |
257 | |
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258 | mov r4, r0 |
259 | mov r5, r1 |
260 | bl new_recompile_block |
261 | tst r0, r0 |
262 | mov r0, r4 |
263 | mov r1, r5 |
264 | beq dyna_linker |
265 | /* pagefault */ |
266 | mov r1, r0 |
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267 | mov r2, #(4<<2) /* Address error (fetch) */ |
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268 | .size dyna_linker, .-dyna_linker |
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269 | |
270 | FUNCTION(exec_pagefault): |
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271 | /* r0 = instruction pointer */ |
272 | /* r1 = fault address */ |
273 | /* r2 = cause */ |
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274 | ldr r3, [fp, #LO_reg_cop0+48] /* Status */ |
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275 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
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276 | orr r3, r3, #2 |
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277 | str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */ |
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278 | str r3, [fp, #LO_reg_cop0+48] /* Status */ |
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279 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
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280 | mov r0, #0x80000000 |
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281 | orr r0, r0, #0x80 |
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282 | bl get_addr_ht |
283 | mov pc, r0 |
284 | .size exec_pagefault, .-exec_pagefault |
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285 | |
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286 | /* Special dynamic linker for the case where a page fault |
287 | may occur in a branch delay slot */ |
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288 | FUNCTION(dyna_linker_ds): |
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289 | /* r0 = virtual target address */ |
290 | /* r1 = instruction to patch */ |
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291 | dyna_linker_main |
292 | |
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293 | mov r4, r0 |
294 | bic r0, r0, #7 |
295 | mov r5, r1 |
296 | orr r0, r0, #1 |
297 | bl new_recompile_block |
298 | tst r0, r0 |
299 | mov r0, r4 |
300 | mov r1, r5 |
301 | beq dyna_linker_ds |
302 | /* pagefault */ |
303 | bic r1, r0, #7 |
304 | mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */ |
305 | sub r0, r1, #4 |
306 | b exec_pagefault |
307 | .size dyna_linker_ds, .-dyna_linker_ds |
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308 | |
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309 | .align 2 |
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310 | |
311 | FUNCTION(jump_vaddr_r0): |
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312 | eor r2, r0, r0, lsl #16 |
313 | b jump_vaddr |
314 | .size jump_vaddr_r0, .-jump_vaddr_r0 |
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315 | FUNCTION(jump_vaddr_r1): |
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316 | eor r2, r1, r1, lsl #16 |
317 | mov r0, r1 |
318 | b jump_vaddr |
319 | .size jump_vaddr_r1, .-jump_vaddr_r1 |
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320 | FUNCTION(jump_vaddr_r2): |
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321 | mov r0, r2 |
322 | eor r2, r2, r2, lsl #16 |
323 | b jump_vaddr |
324 | .size jump_vaddr_r2, .-jump_vaddr_r2 |
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325 | FUNCTION(jump_vaddr_r3): |
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326 | eor r2, r3, r3, lsl #16 |
327 | mov r0, r3 |
328 | b jump_vaddr |
329 | .size jump_vaddr_r3, .-jump_vaddr_r3 |
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330 | FUNCTION(jump_vaddr_r4): |
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331 | eor r2, r4, r4, lsl #16 |
332 | mov r0, r4 |
333 | b jump_vaddr |
334 | .size jump_vaddr_r4, .-jump_vaddr_r4 |
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335 | FUNCTION(jump_vaddr_r5): |
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336 | eor r2, r5, r5, lsl #16 |
337 | mov r0, r5 |
338 | b jump_vaddr |
339 | .size jump_vaddr_r5, .-jump_vaddr_r5 |
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340 | FUNCTION(jump_vaddr_r6): |
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341 | eor r2, r6, r6, lsl #16 |
342 | mov r0, r6 |
343 | b jump_vaddr |
344 | .size jump_vaddr_r6, .-jump_vaddr_r6 |
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345 | FUNCTION(jump_vaddr_r8): |
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346 | eor r2, r8, r8, lsl #16 |
347 | mov r0, r8 |
348 | b jump_vaddr |
349 | .size jump_vaddr_r8, .-jump_vaddr_r8 |
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350 | FUNCTION(jump_vaddr_r9): |
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351 | eor r2, r9, r9, lsl #16 |
352 | mov r0, r9 |
353 | b jump_vaddr |
354 | .size jump_vaddr_r9, .-jump_vaddr_r9 |
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355 | FUNCTION(jump_vaddr_r10): |
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356 | eor r2, r10, r10, lsl #16 |
357 | mov r0, r10 |
358 | b jump_vaddr |
359 | .size jump_vaddr_r10, .-jump_vaddr_r10 |
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360 | FUNCTION(jump_vaddr_r12): |
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361 | eor r2, r12, r12, lsl #16 |
362 | mov r0, r12 |
363 | b jump_vaddr |
364 | .size jump_vaddr_r12, .-jump_vaddr_r12 |
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365 | FUNCTION(jump_vaddr_r7): |
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366 | eor r2, r7, r7, lsl #16 |
367 | add r0, r7, #0 |
368 | .size jump_vaddr_r7, .-jump_vaddr_r7 |
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369 | FUNCTION(jump_vaddr): |
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370 | load_varadr_ext r1, hash_table |
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371 | mvn r3, #15 |
372 | and r2, r3, r2, lsr #12 |
373 | ldr r2, [r1, r2]! |
374 | teq r2, r0 |
df4dc2b1 |
375 | ldreq pc, [r1, #8] |
376 | ldr r2, [r1, #4] |
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377 | teq r2, r0 |
378 | ldreq pc, [r1, #12] |
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379 | str r10, [fp, #LO_cycle_count] |
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380 | bl get_addr |
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381 | ldr r10, [fp, #LO_cycle_count] |
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382 | mov pc, r0 |
383 | .size jump_vaddr, .-jump_vaddr |
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384 | |
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385 | .align 2 |
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386 | |
387 | FUNCTION(verify_code_ds): |
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388 | str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG? |
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389 | FUNCTION(verify_code): |
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390 | /* r1 = source */ |
391 | /* r2 = target */ |
392 | /* r3 = length */ |
393 | tst r3, #4 |
394 | mov r4, #0 |
395 | add r3, r1, r3 |
396 | mov r5, #0 |
397 | ldrne r4, [r1], #4 |
398 | mov r12, #0 |
399 | ldrne r5, [r2], #4 |
400 | teq r1, r3 |
401 | beq .D3 |
402 | .D2: |
403 | ldr r7, [r1], #4 |
404 | eor r9, r4, r5 |
405 | ldr r8, [r2], #4 |
406 | orrs r9, r9, r12 |
407 | bne .D4 |
408 | ldr r4, [r1], #4 |
409 | eor r12, r7, r8 |
410 | ldr r5, [r2], #4 |
411 | cmp r1, r3 |
412 | bcc .D2 |
413 | teq r7, r8 |
414 | .D3: |
415 | teqeq r4, r5 |
416 | .D4: |
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417 | ldr r8, [fp, #LO_branch_target] |
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418 | moveq pc, lr |
419 | .D5: |
420 | bl get_addr |
421 | mov pc, r0 |
422 | .size verify_code, .-verify_code |
7c3a5182 |
423 | .size verify_code_ds, .-verify_code_ds |
7139f3c8 |
424 | |
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425 | .align 2 |
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426 | FUNCTION(cc_interrupt): |
b1f89e6f |
427 | ldr r0, [fp, #LO_last_count] |
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428 | mov r1, #0 |
429 | mov r2, #0x1fc |
430 | add r10, r0, r10 |
b1f89e6f |
431 | str r1, [fp, #LO_pending_exception] |
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432 | and r2, r2, r10, lsr #17 |
b1f89e6f |
433 | add r3, fp, #LO_restore_candidate |
434 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
b4ab351d |
435 | @@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */ |
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436 | ldr r4, [r2, r3] |
437 | mov r10, lr |
438 | tst r4, r4 |
439 | bne .E4 |
440 | .E1: |
441 | bl gen_interupt |
442 | mov lr, r10 |
b1f89e6f |
443 | ldr r10, [fp, #LO_cycle] |
444 | ldr r0, [fp, #LO_next_interupt] |
445 | ldr r1, [fp, #LO_pending_exception] |
446 | ldr r2, [fp, #LO_stop] |
447 | str r0, [fp, #LO_last_count] |
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448 | sub r10, r10, r0 |
449 | tst r2, r2 |
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450 | ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
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451 | tst r1, r1 |
452 | moveq pc, lr |
453 | .E2: |
b1f89e6f |
454 | ldr r0, [fp, #LO_pcaddr] |
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455 | bl get_addr_ht |
456 | mov pc, r0 |
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457 | .E4: |
458 | /* Move 'dirty' blocks to the 'clean' list */ |
459 | lsl r5, r2, #3 |
460 | str r1, [r2, r3] |
461 | .E5: |
462 | lsrs r4, r4, #1 |
463 | mov r0, r5 |
464 | add r5, r5, #1 |
465 | blcs clean_blocks |
466 | tst r5, #31 |
467 | bne .E5 |
468 | b .E1 |
57871462 |
469 | .size cc_interrupt, .-cc_interrupt |
7139f3c8 |
470 | |
57871462 |
471 | .align 2 |
5c6457c3 |
472 | FUNCTION(fp_exception): |
57871462 |
473 | mov r2, #0x10000000 |
474 | .E7: |
b1f89e6f |
475 | ldr r1, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
476 | mov r3, #0x80000000 |
b1f89e6f |
477 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
57871462 |
478 | orr r1, #2 |
479 | add r2, r2, #0x2c |
b1f89e6f |
480 | str r1, [fp, #LO_reg_cop0+48] /* Status */ |
481 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
7139f3c8 |
482 | add r0, r3, #0x80 |
57871462 |
483 | bl get_addr_ht |
484 | mov pc, r0 |
485 | .size fp_exception, .-fp_exception |
486 | .align 2 |
5c6457c3 |
487 | FUNCTION(fp_exception_ds): |
57871462 |
488 | mov r2, #0x90000000 /* Set high bit if delay slot */ |
489 | b .E7 |
490 | .size fp_exception_ds, .-fp_exception_ds |
7139f3c8 |
491 | |
57871462 |
492 | .align 2 |
d1150cd6 |
493 | FUNCTION(jump_break_ds): |
494 | mov r0, #0x24 |
495 | mov r1, #1 |
496 | b call_psxException |
497 | FUNCTION(jump_break): |
498 | mov r0, #0x24 |
499 | mov r1, #0 |
500 | b call_psxException |
501 | FUNCTION(jump_syscall_ds): |
502 | mov r0, #0x20 |
503 | mov r1, #1 |
504 | b call_psxException |
5c6457c3 |
505 | FUNCTION(jump_syscall): |
d1150cd6 |
506 | mov r0, #0x20 |
507 | mov r1, #0 |
508 | |
509 | call_psxException: |
510 | ldr r3, [fp, #LO_last_count] |
511 | str r2, [fp, #LO_pcaddr] |
512 | add r10, r3, r10 |
513 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
514 | bl psxException |
7139f3c8 |
515 | |
b1f89e6f |
516 | /* note: psxException might do recursive recompiler call from it's HLE code, |
7139f3c8 |
517 | * so be ready for this */ |
3968e69e |
518 | FUNCTION(jump_to_new_pc): |
b1f89e6f |
519 | ldr r1, [fp, #LO_next_interupt] |
520 | ldr r10, [fp, #LO_cycle] |
521 | ldr r0, [fp, #LO_pcaddr] |
822b27d1 |
522 | sub r10, r10, r1 |
b1f89e6f |
523 | str r1, [fp, #LO_last_count] |
7139f3c8 |
524 | bl get_addr_ht |
525 | mov pc, r0 |
3968e69e |
526 | .size jump_to_new_pc, .-jump_to_new_pc |
0d16cda2 |
527 | |
7139f3c8 |
528 | .align 2 |
5c6457c3 |
529 | FUNCTION(new_dyna_leave): |
b1f89e6f |
530 | ldr r0, [fp, #LO_last_count] |
7139f3c8 |
531 | add r12, fp, #28 |
532 | add r10, r0, r10 |
b1f89e6f |
533 | str r10, [fp, #LO_cycle] |
b021ee75 |
534 | ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
7139f3c8 |
535 | .size new_dyna_leave, .-new_dyna_leave |
536 | |
0bbd1454 |
537 | .align 2 |
5c6457c3 |
538 | FUNCTION(invalidate_addr_r0): |
5df0e313 |
539 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
0bbd1454 |
540 | b invalidate_addr_call |
541 | .size invalidate_addr_r0, .-invalidate_addr_r0 |
542 | .align 2 |
5c6457c3 |
543 | FUNCTION(invalidate_addr_r1): |
5df0e313 |
544 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
545 | mov r0, r1 |
0bbd1454 |
546 | b invalidate_addr_call |
547 | .size invalidate_addr_r1, .-invalidate_addr_r1 |
548 | .align 2 |
5c6457c3 |
549 | FUNCTION(invalidate_addr_r2): |
5df0e313 |
550 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
551 | mov r0, r2 |
0bbd1454 |
552 | b invalidate_addr_call |
553 | .size invalidate_addr_r2, .-invalidate_addr_r2 |
554 | .align 2 |
5c6457c3 |
555 | FUNCTION(invalidate_addr_r3): |
5df0e313 |
556 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
557 | mov r0, r3 |
0bbd1454 |
558 | b invalidate_addr_call |
559 | .size invalidate_addr_r3, .-invalidate_addr_r3 |
560 | .align 2 |
5c6457c3 |
561 | FUNCTION(invalidate_addr_r4): |
5df0e313 |
562 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
563 | mov r0, r4 |
0bbd1454 |
564 | b invalidate_addr_call |
565 | .size invalidate_addr_r4, .-invalidate_addr_r4 |
566 | .align 2 |
5c6457c3 |
567 | FUNCTION(invalidate_addr_r5): |
5df0e313 |
568 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
569 | mov r0, r5 |
0bbd1454 |
570 | b invalidate_addr_call |
571 | .size invalidate_addr_r5, .-invalidate_addr_r5 |
572 | .align 2 |
5c6457c3 |
573 | FUNCTION(invalidate_addr_r6): |
5df0e313 |
574 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
575 | mov r0, r6 |
0bbd1454 |
576 | b invalidate_addr_call |
577 | .size invalidate_addr_r6, .-invalidate_addr_r6 |
578 | .align 2 |
5c6457c3 |
579 | FUNCTION(invalidate_addr_r7): |
5df0e313 |
580 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
581 | mov r0, r7 |
0bbd1454 |
582 | b invalidate_addr_call |
583 | .size invalidate_addr_r7, .-invalidate_addr_r7 |
584 | .align 2 |
5c6457c3 |
585 | FUNCTION(invalidate_addr_r8): |
5df0e313 |
586 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
587 | mov r0, r8 |
0bbd1454 |
588 | b invalidate_addr_call |
589 | .size invalidate_addr_r8, .-invalidate_addr_r8 |
590 | .align 2 |
5c6457c3 |
591 | FUNCTION(invalidate_addr_r9): |
5df0e313 |
592 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
593 | mov r0, r9 |
0bbd1454 |
594 | b invalidate_addr_call |
595 | .size invalidate_addr_r9, .-invalidate_addr_r9 |
596 | .align 2 |
5c6457c3 |
597 | FUNCTION(invalidate_addr_r10): |
5df0e313 |
598 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
599 | mov r0, r10 |
0bbd1454 |
600 | b invalidate_addr_call |
601 | .size invalidate_addr_r10, .-invalidate_addr_r10 |
602 | .align 2 |
5c6457c3 |
603 | FUNCTION(invalidate_addr_r12): |
5df0e313 |
604 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
605 | mov r0, r12 |
0bbd1454 |
606 | .size invalidate_addr_r12, .-invalidate_addr_r12 |
607 | .align 2 |
b1f89e6f |
608 | invalidate_addr_call: |
609 | ldr r12, [fp, #LO_inv_code_start] |
610 | ldr lr, [fp, #LO_inv_code_end] |
9be4ba64 |
611 | cmp r0, r12 |
612 | cmpcs lr, r0 |
613 | blcc invalidate_addr |
5df0e313 |
614 | ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc} |
0bbd1454 |
615 | .size invalidate_addr_call, .-invalidate_addr_call |
616 | |
57871462 |
617 | .align 2 |
5c6457c3 |
618 | FUNCTION(new_dyna_start): |
b021ee75 |
619 | /* ip is stored to conform EABI alignment */ |
620 | stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
be516ebe |
621 | mov fp, r0 /* dynarec_local */ |
b1f89e6f |
622 | ldr r0, [fp, #LO_pcaddr] |
7139f3c8 |
623 | bl get_addr_ht |
b1f89e6f |
624 | ldr r1, [fp, #LO_next_interupt] |
625 | ldr r10, [fp, #LO_cycle] |
626 | str r1, [fp, #LO_last_count] |
7139f3c8 |
627 | sub r10, r10, r1 |
628 | mov pc, r0 |
57871462 |
629 | .size new_dyna_start, .-new_dyna_start |
7139f3c8 |
630 | |
7e605697 |
631 | /* --------------------------------------- */ |
7139f3c8 |
632 | |
7e605697 |
633 | .align 2 |
c6c3b1b3 |
634 | |
635 | .macro pcsx_read_mem readop tab_shift |
636 | /* r0 = address, r1 = handler_tab, r2 = cycles */ |
637 | lsl r3, r0, #20 |
638 | lsr r3, #(20+\tab_shift) |
b1f89e6f |
639 | ldr r12, [fp, #LO_last_count] |
c6c3b1b3 |
640 | ldr r1, [r1, r3, lsl #2] |
641 | add r2, r2, r12 |
642 | lsls r1, #1 |
643 | .if \tab_shift == 1 |
644 | lsl r3, #1 |
645 | \readop r0, [r1, r3] |
646 | .else |
647 | \readop r0, [r1, r3, lsl #\tab_shift] |
648 | .endif |
649 | movcc pc, lr |
b1f89e6f |
650 | str r2, [fp, #LO_cycle] |
c6c3b1b3 |
651 | bx r1 |
652 | .endm |
653 | |
5c6457c3 |
654 | FUNCTION(jump_handler_read8): |
c6c3b1b3 |
655 | add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
656 | pcsx_read_mem ldrbcc, 0 |
c6c3b1b3 |
657 | |
5c6457c3 |
658 | FUNCTION(jump_handler_read16): |
c6c3b1b3 |
659 | add r1, #0x1000/4*4 @ shift to r16 part |
10858959 |
660 | pcsx_read_mem ldrhcc, 1 |
c6c3b1b3 |
661 | |
5c6457c3 |
662 | FUNCTION(jump_handler_read32): |
c6c3b1b3 |
663 | pcsx_read_mem ldrcc, 2 |
664 | |
b96d3df7 |
665 | |
9b9af0d1 |
666 | .macro memhandler_post |
667 | ldr r0, [fp, #LO_next_interupt] |
668 | ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma |
669 | str r0, [fp, #LO_last_count] |
670 | sub r0, r2, r0 |
671 | .endm |
672 | |
b96d3df7 |
673 | .macro pcsx_write_mem wrtop tab_shift |
674 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */ |
675 | lsl r12,r0, #20 |
676 | lsr r12, #(20+\tab_shift) |
677 | ldr r3, [r3, r12, lsl #2] |
b1f89e6f |
678 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
679 | lsls r3, #1 |
9b9af0d1 |
680 | mov r0, r2 @ cycle return in case of direct store |
b96d3df7 |
681 | .if \tab_shift == 1 |
682 | lsl r12, #1 |
683 | \wrtop r1, [r3, r12] |
684 | .else |
685 | \wrtop r1, [r3, r12, lsl #\tab_shift] |
686 | .endif |
687 | movcc pc, lr |
b1f89e6f |
688 | ldr r12, [fp, #LO_last_count] |
b96d3df7 |
689 | mov r0, r1 |
690 | add r2, r2, r12 |
b1f89e6f |
691 | str r2, [fp, #LO_cycle] |
9b9af0d1 |
692 | |
693 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
694 | blx r3 |
9b9af0d1 |
695 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
696 | |
9b9af0d1 |
697 | memhandler_post |
687b4580 |
698 | bx lr |
b96d3df7 |
699 | .endm |
700 | |
5c6457c3 |
701 | FUNCTION(jump_handler_write8): |
b96d3df7 |
702 | add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
703 | pcsx_write_mem strbcc, 0 |
b96d3df7 |
704 | |
5c6457c3 |
705 | FUNCTION(jump_handler_write16): |
b96d3df7 |
706 | add r3, #0x1000/4*4 @ shift to r16 part |
b861c0a9 |
707 | pcsx_write_mem strhcc, 1 |
b96d3df7 |
708 | |
5c6457c3 |
709 | FUNCTION(jump_handler_write32): |
b96d3df7 |
710 | pcsx_write_mem strcc, 2 |
711 | |
5c6457c3 |
712 | FUNCTION(jump_handler_write_h): |
b96d3df7 |
713 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler */ |
b1f89e6f |
714 | ldr r12, [fp, #LO_last_count] |
715 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
716 | add r2, r2, r12 |
717 | mov r0, r1 |
b1f89e6f |
718 | str r2, [fp, #LO_cycle] |
9b9af0d1 |
719 | |
720 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
721 | blx r3 |
9b9af0d1 |
722 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
723 | |
9b9af0d1 |
724 | memhandler_post |
687b4580 |
725 | bx lr |
b96d3df7 |
726 | |
5c6457c3 |
727 | FUNCTION(jump_handle_swl): |
b96d3df7 |
728 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
729 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
730 | mov r12,r0,lsr #12 |
731 | ldr r3, [r3, r12, lsl #2] |
732 | lsls r3, #1 |
733 | bcs 4f |
734 | add r3, r0, r3 |
735 | mov r0, r2 |
736 | tst r3, #2 |
737 | beq 101f |
738 | tst r3, #1 |
739 | beq 2f |
740 | 3: |
741 | str r1, [r3, #-3] |
742 | bx lr |
743 | 2: |
744 | lsr r2, r1, #8 |
745 | lsr r1, #24 |
746 | strh r2, [r3, #-2] |
747 | strb r1, [r3] |
748 | bx lr |
749 | 101: |
750 | tst r3, #1 |
751 | lsrne r1, #16 @ 1 |
752 | lsreq r12, r1, #24 @ 0 |
b861c0a9 |
753 | strhne r1, [r3, #-1] |
754 | strbeq r12, [r3] |
b96d3df7 |
755 | bx lr |
756 | 4: |
757 | mov r0, r2 |
63cb0298 |
758 | @ b abort |
b96d3df7 |
759 | bx lr @ TODO? |
760 | |
761 | |
5c6457c3 |
762 | FUNCTION(jump_handle_swr): |
b96d3df7 |
763 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
764 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
765 | mov r12,r0,lsr #12 |
766 | ldr r3, [r3, r12, lsl #2] |
767 | lsls r3, #1 |
768 | bcs 4f |
769 | add r3, r0, r3 |
770 | and r12,r3, #3 |
771 | mov r0, r2 |
772 | cmp r12,#2 |
b861c0a9 |
773 | strbgt r1, [r3] @ 3 |
774 | strheq r1, [r3] @ 2 |
b96d3df7 |
775 | cmp r12,#1 |
776 | strlt r1, [r3] @ 0 |
777 | bxne lr |
778 | lsr r2, r1, #8 @ 1 |
779 | strb r1, [r3] |
780 | strh r2, [r3, #1] |
781 | bx lr |
782 | 4: |
783 | mov r0, r2 |
63cb0298 |
784 | @ b abort |
b96d3df7 |
785 | bx lr @ TODO? |
786 | |
787 | |
b1be1eee |
788 | .macro rcntx_read_mode0 num |
789 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
790 | ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart |
b1be1eee |
791 | mov r0, r2, lsl #16 |
b861c0a9 |
792 | sub r0, r0, r3, lsl #16 |
b1be1eee |
793 | lsr r0, #16 |
794 | bx lr |
795 | .endm |
796 | |
5c6457c3 |
797 | FUNCTION(rcnt0_read_count_m0): |
b1be1eee |
798 | rcntx_read_mode0 0 |
799 | |
5c6457c3 |
800 | FUNCTION(rcnt1_read_count_m0): |
b1be1eee |
801 | rcntx_read_mode0 1 |
802 | |
5c6457c3 |
803 | FUNCTION(rcnt2_read_count_m0): |
b1be1eee |
804 | rcntx_read_mode0 2 |
805 | |
5c6457c3 |
806 | FUNCTION(rcnt0_read_count_m1): |
b1be1eee |
807 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
808 | ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart |
b1be1eee |
809 | mov_16 r1, 0x3334 |
810 | sub r2, r2, r3 |
811 | mul r0, r1, r2 @ /= 5 |
812 | lsr r0, #16 |
813 | bx lr |
814 | |
5c6457c3 |
815 | FUNCTION(rcnt1_read_count_m1): |
b1be1eee |
816 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
817 | ldr r3, [fp, #LO_rcnts+6*4+7*4*1] |
b1be1eee |
818 | mov_24 r1, 0x1e6cde |
819 | sub r2, r2, r3 |
820 | umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd |
821 | bx lr |
822 | |
5c6457c3 |
823 | FUNCTION(rcnt2_read_count_m1): |
b1be1eee |
824 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
825 | ldr r3, [fp, #LO_rcnts+6*4+7*4*2] |
b1be1eee |
826 | mov r0, r2, lsl #16-3 |
b861c0a9 |
827 | sub r0, r0, r3, lsl #16-3 |
b1be1eee |
828 | lsr r0, #16 @ /= 8 |
829 | bx lr |
830 | |
81dbbf4c |
831 | FUNCTION(call_gteStall): |
832 | /* r0 = op_cycles, r1 = cycles */ |
833 | ldr r2, [fp, #LO_last_count] |
834 | str lr, [fp, #LO_saved_lr] |
835 | add r1, r1, r2 |
836 | str r1, [fp, #LO_cycle] |
837 | add r1, fp, #LO_psxRegs |
838 | bl gteCheckStallRaw |
839 | ldr lr, [fp, #LO_saved_lr] |
840 | add r10, r10, r0 |
841 | bx lr |
842 | |
7e605697 |
843 | @ vim:filetype=armasm |