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1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
7e605697 |
2 | * linkage_arm.s for PCSX * |
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3 | * Copyright (C) 2009-2011 Ari64 * |
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4 | * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas * |
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5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
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21 | |
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22 | #include "arm_features.h" |
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23 | #include "new_dynarec_config.h" |
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24 | #include "linkage_offsets.h" |
25 | |
26 | |
27 | #ifdef __MACH__ |
28 | #define dynarec_local ESYM(dynarec_local) |
29 | #define add_link ESYM(add_link) |
30 | #define new_recompile_block ESYM(new_recompile_block) |
31 | #define get_addr ESYM(get_addr) |
32 | #define get_addr_ht ESYM(get_addr_ht) |
33 | #define clean_blocks ESYM(clean_blocks) |
34 | #define gen_interupt ESYM(gen_interupt) |
35 | #define psxException ESYM(psxException) |
36 | #define execI ESYM(execI) |
37 | #define invalidate_addr ESYM(invalidate_addr) |
38 | #endif |
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39 | |
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40 | .bss |
41 | .align 4 |
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42 | .global dynarec_local |
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43 | .type dynarec_local, %object |
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44 | .size dynarec_local, LO_dynarec_local_size |
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45 | dynarec_local: |
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46 | .space LO_dynarec_local_size |
47 | |
48 | #define DRC_VAR_(name, vname, size_) \ |
49 | vname = dynarec_local + LO_##name; \ |
50 | .global vname; \ |
51 | .type vname, %object; \ |
52 | .size vname, size_ |
53 | |
54 | #define DRC_VAR(name, size_) \ |
55 | DRC_VAR_(name, ESYM(name), size_) |
56 | |
57 | DRC_VAR(next_interupt, 4) |
58 | DRC_VAR(cycle_count, 4) |
59 | DRC_VAR(last_count, 4) |
60 | DRC_VAR(pending_exception, 4) |
61 | DRC_VAR(stop, 4) |
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62 | DRC_VAR(branch_target, 4) |
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63 | DRC_VAR(address, 4) |
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64 | @DRC_VAR(align0, 4) /* unused/alignment */ |
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65 | DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs) |
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66 | |
67 | /* psxRegs */ |
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68 | @DRC_VAR(reg, 128) |
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69 | DRC_VAR(lo, 4) |
70 | DRC_VAR(hi, 4) |
71 | DRC_VAR(reg_cop0, 128) |
72 | DRC_VAR(reg_cop2d, 128) |
73 | DRC_VAR(reg_cop2c, 128) |
74 | DRC_VAR(pcaddr, 4) |
75 | @DRC_VAR(code, 4) |
76 | @DRC_VAR(cycle, 4) |
77 | @DRC_VAR(interrupt, 4) |
78 | @DRC_VAR(intCycle, 256) |
79 | |
80 | DRC_VAR(rcnts, 7*4*4) |
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81 | DRC_VAR(inv_code_start, 4) |
82 | DRC_VAR(inv_code_end, 4) |
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83 | DRC_VAR(mem_rtab, 4) |
84 | DRC_VAR(mem_wtab, 4) |
85 | DRC_VAR(psxH_ptr, 4) |
86 | DRC_VAR(zeromem_ptr, 4) |
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87 | DRC_VAR(invc_ptr, 4) |
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88 | DRC_VAR(scratch_buf_ptr, 4) |
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89 | @DRC_VAR(align1, 8) /* unused/alignment */ |
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90 | DRC_VAR(mini_ht, 256) |
91 | DRC_VAR(restore_candidate, 512) |
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92 | |
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93 | |
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94 | #ifdef TEXRELS_FORBIDDEN |
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95 | .data |
96 | .align 2 |
97 | ptr_jump_in: |
98 | .word ESYM(jump_in) |
99 | ptr_jump_dirty: |
100 | .word ESYM(jump_dirty) |
101 | ptr_hash_table: |
102 | .word ESYM(hash_table) |
103 | #endif |
104 | |
105 | |
106 | .syntax unified |
107 | .text |
108 | .align 2 |
109 | |
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110 | #ifndef HAVE_ARMV5 |
111 | .macro blx rd |
112 | mov lr, pc |
113 | bx \rd |
114 | .endm |
115 | #endif |
116 | |
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117 | .macro load_varadr reg var |
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118 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
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119 | movw \reg, #:lower16:(\var-(1678f+8)) |
120 | movt \reg, #:upper16:(\var-(1678f+8)) |
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121 | 1678: |
122 | add \reg, pc |
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123 | #elif defined(HAVE_ARMV7) && !defined(__PIC__) |
124 | movw \reg, #:lower16:\var |
125 | movt \reg, #:upper16:\var |
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126 | #else |
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127 | ldr \reg, =\var |
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128 | #endif |
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129 | .endm |
130 | |
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131 | .macro load_varadr_ext reg var |
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132 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
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133 | movw \reg, #:lower16:(ptr_\var-(1678f+8)) |
134 | movt \reg, #:upper16:(ptr_\var-(1678f+8)) |
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135 | 1678: |
136 | ldr \reg, [pc, \reg] |
137 | #else |
138 | load_varadr \reg \var |
139 | #endif |
140 | .endm |
141 | |
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142 | .macro mov_16 reg imm |
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143 | #ifdef HAVE_ARMV7 |
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144 | movw \reg, #\imm |
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145 | #else |
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146 | mov \reg, #(\imm & 0x00ff) |
147 | orr \reg, #(\imm & 0xff00) |
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148 | #endif |
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149 | .endm |
150 | |
151 | .macro mov_24 reg imm |
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152 | #ifdef HAVE_ARMV7 |
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153 | movw \reg, #(\imm & 0xffff) |
154 | movt \reg, #(\imm >> 16) |
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155 | #else |
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156 | mov \reg, #(\imm & 0x0000ff) |
157 | orr \reg, #(\imm & 0x00ff00) |
158 | orr \reg, #(\imm & 0xff0000) |
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159 | #endif |
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160 | .endm |
161 | |
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162 | /* r0 = virtual target address */ |
163 | /* r1 = instruction to patch */ |
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164 | .macro dyna_linker_main |
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165 | #ifndef NO_WRITE_EXEC |
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166 | load_varadr_ext r3, jump_in |
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167 | /* get_page */ |
168 | lsr r2, r0, #12 |
169 | mov r6, #4096 |
170 | bic r2, r2, #0xe0000 |
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171 | sub r6, r6, #1 |
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172 | cmp r2, #0x1000 |
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173 | ldr r7, [r1] |
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174 | biclt r2, #0x0e00 |
175 | and r6, r6, r2 |
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176 | cmp r2, #2048 |
177 | add r12, r7, #2 |
178 | orrcs r2, r6, #2048 |
179 | ldr r5, [r3, r2, lsl #2] |
180 | lsl r12, r12, #8 |
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181 | add r6, r1, r12, asr #6 |
182 | mov r8, #0 |
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183 | /* jump_in lookup */ |
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184 | 1: |
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185 | movs r4, r5 |
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186 | beq 2f |
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187 | ldr r3, [r5] /* ll_entry .vaddr */ |
188 | ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */ |
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189 | teq r3, r0 |
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190 | bne 1b |
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191 | teq r4, r6 |
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192 | moveq pc, r4 /* Stale i-cache */ |
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193 | mov r8, r4 |
194 | b 1b /* jump_in may have dupes, continue search */ |
195 | 2: |
196 | tst r8, r8 |
197 | beq 3f /* r0 not in jump_in */ |
198 | |
199 | mov r5, r1 |
200 | mov r1, r6 |
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201 | bl add_link |
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202 | sub r2, r8, r5 |
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203 | and r1, r7, #0xff000000 |
204 | lsl r2, r2, #6 |
205 | sub r1, r1, #2 |
206 | add r1, r1, r2, lsr #8 |
207 | str r1, [r5] |
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208 | mov pc, r8 |
209 | 3: |
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210 | /* hash_table lookup */ |
211 | cmp r2, #2048 |
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212 | load_varadr_ext r3, jump_dirty |
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213 | eor r4, r0, r0, lsl #16 |
214 | lslcc r2, r0, #9 |
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215 | load_varadr_ext r6, hash_table |
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216 | lsr r4, r4, #12 |
217 | lsrcc r2, r2, #21 |
218 | bic r4, r4, #15 |
219 | ldr r5, [r3, r2, lsl #2] |
220 | ldr r7, [r6, r4]! |
221 | teq r7, r0 |
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222 | ldreq pc, [r6, #8] |
223 | ldr r7, [r6, #4] |
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224 | teq r7, r0 |
225 | ldreq pc, [r6, #12] |
226 | /* jump_dirty lookup */ |
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227 | 6: |
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228 | movs r4, r5 |
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229 | beq 8f |
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230 | ldr r3, [r5] |
231 | ldr r5, [r4, #12] |
232 | teq r3, r0 |
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233 | bne 6b |
234 | 7: |
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235 | ldr r1, [r4, #8] |
236 | /* hash_table insert */ |
237 | ldr r2, [r6] |
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238 | ldr r3, [r6, #8] |
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239 | str r0, [r6] |
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240 | str r1, [r6, #8] |
241 | str r2, [r6, #4] |
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242 | str r3, [r6, #12] |
243 | mov pc, r1 |
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244 | 8: |
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245 | #else |
246 | /* XXX: should be able to do better than this... */ |
247 | bl get_addr_ht |
248 | mov pc, r0 |
249 | #endif |
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250 | .endm |
251 | |
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252 | |
253 | FUNCTION(dyna_linker): |
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254 | /* r0 = virtual target address */ |
255 | /* r1 = instruction to patch */ |
256 | dyna_linker_main |
257 | |
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258 | mov r4, r0 |
259 | mov r5, r1 |
260 | bl new_recompile_block |
261 | tst r0, r0 |
262 | mov r0, r4 |
263 | mov r1, r5 |
264 | beq dyna_linker |
265 | /* pagefault */ |
266 | mov r1, r0 |
267 | mov r2, #8 |
268 | .size dyna_linker, .-dyna_linker |
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269 | |
270 | FUNCTION(exec_pagefault): |
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271 | /* r0 = instruction pointer */ |
272 | /* r1 = fault address */ |
273 | /* r2 = cause */ |
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274 | ldr r3, [fp, #LO_reg_cop0+48] /* Status */ |
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275 | mvn r6, #0xF000000F |
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276 | ldr r4, [fp, #LO_reg_cop0+16] /* Context */ |
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277 | bic r6, r6, #0x0F800000 |
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278 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
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279 | orr r3, r3, #2 |
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280 | str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */ |
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281 | bic r4, r4, r6 |
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282 | str r3, [fp, #LO_reg_cop0+48] /* Status */ |
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283 | and r5, r6, r1, lsr #9 |
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284 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
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285 | and r1, r1, r6, lsl #9 |
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286 | str r1, [fp, #LO_reg_cop0+40] /* EntryHi */ |
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287 | orr r4, r4, r5 |
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288 | str r4, [fp, #LO_reg_cop0+16] /* Context */ |
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289 | mov r0, #0x80000000 |
290 | bl get_addr_ht |
291 | mov pc, r0 |
292 | .size exec_pagefault, .-exec_pagefault |
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293 | |
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294 | /* Special dynamic linker for the case where a page fault |
295 | may occur in a branch delay slot */ |
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296 | FUNCTION(dyna_linker_ds): |
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297 | /* r0 = virtual target address */ |
298 | /* r1 = instruction to patch */ |
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299 | dyna_linker_main |
300 | |
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301 | mov r4, r0 |
302 | bic r0, r0, #7 |
303 | mov r5, r1 |
304 | orr r0, r0, #1 |
305 | bl new_recompile_block |
306 | tst r0, r0 |
307 | mov r0, r4 |
308 | mov r1, r5 |
309 | beq dyna_linker_ds |
310 | /* pagefault */ |
311 | bic r1, r0, #7 |
312 | mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */ |
313 | sub r0, r1, #4 |
314 | b exec_pagefault |
315 | .size dyna_linker_ds, .-dyna_linker_ds |
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316 | |
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317 | .align 2 |
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318 | |
319 | FUNCTION(jump_vaddr_r0): |
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320 | eor r2, r0, r0, lsl #16 |
321 | b jump_vaddr |
322 | .size jump_vaddr_r0, .-jump_vaddr_r0 |
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323 | FUNCTION(jump_vaddr_r1): |
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324 | eor r2, r1, r1, lsl #16 |
325 | mov r0, r1 |
326 | b jump_vaddr |
327 | .size jump_vaddr_r1, .-jump_vaddr_r1 |
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328 | FUNCTION(jump_vaddr_r2): |
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329 | mov r0, r2 |
330 | eor r2, r2, r2, lsl #16 |
331 | b jump_vaddr |
332 | .size jump_vaddr_r2, .-jump_vaddr_r2 |
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333 | FUNCTION(jump_vaddr_r3): |
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334 | eor r2, r3, r3, lsl #16 |
335 | mov r0, r3 |
336 | b jump_vaddr |
337 | .size jump_vaddr_r3, .-jump_vaddr_r3 |
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338 | FUNCTION(jump_vaddr_r4): |
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339 | eor r2, r4, r4, lsl #16 |
340 | mov r0, r4 |
341 | b jump_vaddr |
342 | .size jump_vaddr_r4, .-jump_vaddr_r4 |
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343 | FUNCTION(jump_vaddr_r5): |
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344 | eor r2, r5, r5, lsl #16 |
345 | mov r0, r5 |
346 | b jump_vaddr |
347 | .size jump_vaddr_r5, .-jump_vaddr_r5 |
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348 | FUNCTION(jump_vaddr_r6): |
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349 | eor r2, r6, r6, lsl #16 |
350 | mov r0, r6 |
351 | b jump_vaddr |
352 | .size jump_vaddr_r6, .-jump_vaddr_r6 |
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353 | FUNCTION(jump_vaddr_r8): |
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354 | eor r2, r8, r8, lsl #16 |
355 | mov r0, r8 |
356 | b jump_vaddr |
357 | .size jump_vaddr_r8, .-jump_vaddr_r8 |
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358 | FUNCTION(jump_vaddr_r9): |
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359 | eor r2, r9, r9, lsl #16 |
360 | mov r0, r9 |
361 | b jump_vaddr |
362 | .size jump_vaddr_r9, .-jump_vaddr_r9 |
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363 | FUNCTION(jump_vaddr_r10): |
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364 | eor r2, r10, r10, lsl #16 |
365 | mov r0, r10 |
366 | b jump_vaddr |
367 | .size jump_vaddr_r10, .-jump_vaddr_r10 |
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368 | FUNCTION(jump_vaddr_r12): |
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369 | eor r2, r12, r12, lsl #16 |
370 | mov r0, r12 |
371 | b jump_vaddr |
372 | .size jump_vaddr_r12, .-jump_vaddr_r12 |
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373 | FUNCTION(jump_vaddr_r7): |
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374 | eor r2, r7, r7, lsl #16 |
375 | add r0, r7, #0 |
376 | .size jump_vaddr_r7, .-jump_vaddr_r7 |
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377 | FUNCTION(jump_vaddr): |
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378 | load_varadr_ext r1, hash_table |
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379 | mvn r3, #15 |
380 | and r2, r3, r2, lsr #12 |
381 | ldr r2, [r1, r2]! |
382 | teq r2, r0 |
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383 | ldreq pc, [r1, #8] |
384 | ldr r2, [r1, #4] |
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385 | teq r2, r0 |
386 | ldreq pc, [r1, #12] |
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387 | str r10, [fp, #LO_cycle_count] |
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388 | bl get_addr |
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389 | ldr r10, [fp, #LO_cycle_count] |
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390 | mov pc, r0 |
391 | .size jump_vaddr, .-jump_vaddr |
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392 | |
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393 | .align 2 |
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394 | |
395 | FUNCTION(verify_code_ds): |
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396 | str r8, [fp, #LO_branch_target] |
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397 | FUNCTION(verify_code): |
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398 | /* r1 = source */ |
399 | /* r2 = target */ |
400 | /* r3 = length */ |
401 | tst r3, #4 |
402 | mov r4, #0 |
403 | add r3, r1, r3 |
404 | mov r5, #0 |
405 | ldrne r4, [r1], #4 |
406 | mov r12, #0 |
407 | ldrne r5, [r2], #4 |
408 | teq r1, r3 |
409 | beq .D3 |
410 | .D2: |
411 | ldr r7, [r1], #4 |
412 | eor r9, r4, r5 |
413 | ldr r8, [r2], #4 |
414 | orrs r9, r9, r12 |
415 | bne .D4 |
416 | ldr r4, [r1], #4 |
417 | eor r12, r7, r8 |
418 | ldr r5, [r2], #4 |
419 | cmp r1, r3 |
420 | bcc .D2 |
421 | teq r7, r8 |
422 | .D3: |
423 | teqeq r4, r5 |
424 | .D4: |
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425 | ldr r8, [fp, #LO_branch_target] |
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426 | moveq pc, lr |
427 | .D5: |
428 | bl get_addr |
429 | mov pc, r0 |
430 | .size verify_code, .-verify_code |
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431 | .size verify_code_ds, .-verify_code_ds |
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432 | |
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433 | .align 2 |
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434 | FUNCTION(cc_interrupt): |
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435 | ldr r0, [fp, #LO_last_count] |
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436 | mov r1, #0 |
437 | mov r2, #0x1fc |
438 | add r10, r0, r10 |
b1f89e6f |
439 | str r1, [fp, #LO_pending_exception] |
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440 | and r2, r2, r10, lsr #17 |
b1f89e6f |
441 | add r3, fp, #LO_restore_candidate |
442 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
443 | @@ str r10, [fp, #LO_reg_cop0+36] /* Count */ |
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444 | ldr r4, [r2, r3] |
445 | mov r10, lr |
446 | tst r4, r4 |
447 | bne .E4 |
448 | .E1: |
449 | bl gen_interupt |
450 | mov lr, r10 |
b1f89e6f |
451 | ldr r10, [fp, #LO_cycle] |
452 | ldr r0, [fp, #LO_next_interupt] |
453 | ldr r1, [fp, #LO_pending_exception] |
454 | ldr r2, [fp, #LO_stop] |
455 | str r0, [fp, #LO_last_count] |
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456 | sub r10, r10, r0 |
457 | tst r2, r2 |
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458 | ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
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459 | tst r1, r1 |
460 | moveq pc, lr |
461 | .E2: |
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462 | ldr r0, [fp, #LO_pcaddr] |
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463 | bl get_addr_ht |
464 | mov pc, r0 |
57871462 |
465 | .E4: |
466 | /* Move 'dirty' blocks to the 'clean' list */ |
467 | lsl r5, r2, #3 |
468 | str r1, [r2, r3] |
469 | .E5: |
470 | lsrs r4, r4, #1 |
471 | mov r0, r5 |
472 | add r5, r5, #1 |
473 | blcs clean_blocks |
474 | tst r5, #31 |
475 | bne .E5 |
476 | b .E1 |
57871462 |
477 | .size cc_interrupt, .-cc_interrupt |
7139f3c8 |
478 | |
57871462 |
479 | .align 2 |
5c6457c3 |
480 | FUNCTION(fp_exception): |
57871462 |
481 | mov r2, #0x10000000 |
482 | .E7: |
b1f89e6f |
483 | ldr r1, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
484 | mov r3, #0x80000000 |
b1f89e6f |
485 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
57871462 |
486 | orr r1, #2 |
487 | add r2, r2, #0x2c |
b1f89e6f |
488 | str r1, [fp, #LO_reg_cop0+48] /* Status */ |
489 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
7139f3c8 |
490 | add r0, r3, #0x80 |
57871462 |
491 | bl get_addr_ht |
492 | mov pc, r0 |
493 | .size fp_exception, .-fp_exception |
494 | .align 2 |
5c6457c3 |
495 | FUNCTION(fp_exception_ds): |
57871462 |
496 | mov r2, #0x90000000 /* Set high bit if delay slot */ |
497 | b .E7 |
498 | .size fp_exception_ds, .-fp_exception_ds |
7139f3c8 |
499 | |
57871462 |
500 | .align 2 |
5c6457c3 |
501 | FUNCTION(jump_syscall): |
b1f89e6f |
502 | ldr r1, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
503 | mov r3, #0x80000000 |
b1f89e6f |
504 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
57871462 |
505 | orr r1, #2 |
506 | mov r2, #0x20 |
b1f89e6f |
507 | str r1, [fp, #LO_reg_cop0+48] /* Status */ |
508 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
7139f3c8 |
509 | add r0, r3, #0x80 |
57871462 |
510 | bl get_addr_ht |
511 | mov pc, r0 |
512 | .size jump_syscall, .-jump_syscall |
7139f3c8 |
513 | .align 2 |
514 | |
515 | .align 2 |
5c6457c3 |
516 | FUNCTION(jump_syscall_hle): |
b1f89e6f |
517 | str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */ |
518 | ldr r2, [fp, #LO_last_count] |
7139f3c8 |
519 | mov r1, #0 /* in delay slot */ |
520 | add r2, r2, r10 |
521 | mov r0, #0x20 /* cause */ |
b1f89e6f |
522 | str r2, [fp, #LO_cycle] /* PCSX cycle counter */ |
7139f3c8 |
523 | bl psxException |
524 | |
b1f89e6f |
525 | /* note: psxException might do recursive recompiler call from it's HLE code, |
7139f3c8 |
526 | * so be ready for this */ |
822b27d1 |
527 | pcsx_return: |
b1f89e6f |
528 | ldr r1, [fp, #LO_next_interupt] |
529 | ldr r10, [fp, #LO_cycle] |
530 | ldr r0, [fp, #LO_pcaddr] |
822b27d1 |
531 | sub r10, r10, r1 |
b1f89e6f |
532 | str r1, [fp, #LO_last_count] |
7139f3c8 |
533 | bl get_addr_ht |
534 | mov pc, r0 |
535 | .size jump_syscall_hle, .-jump_syscall_hle |
536 | |
537 | .align 2 |
5c6457c3 |
538 | FUNCTION(jump_hlecall): |
b1f89e6f |
539 | ldr r2, [fp, #LO_last_count] |
540 | str r0, [fp, #LO_pcaddr] |
7139f3c8 |
541 | add r2, r2, r10 |
822b27d1 |
542 | adr lr, pcsx_return |
b1f89e6f |
543 | str r2, [fp, #LO_cycle] /* PCSX cycle counter */ |
67ba0fb4 |
544 | bx r1 |
7139f3c8 |
545 | .size jump_hlecall, .-jump_hlecall |
546 | |
0d16cda2 |
547 | .align 2 |
5c6457c3 |
548 | FUNCTION(jump_intcall): |
b1f89e6f |
549 | ldr r2, [fp, #LO_last_count] |
550 | str r0, [fp, #LO_pcaddr] |
0d16cda2 |
551 | add r2, r2, r10 |
552 | adr lr, pcsx_return |
b1f89e6f |
553 | str r2, [fp, #LO_cycle] /* PCSX cycle counter */ |
0d16cda2 |
554 | b execI |
555 | .size jump_hlecall, .-jump_hlecall |
556 | |
7139f3c8 |
557 | .align 2 |
5c6457c3 |
558 | FUNCTION(new_dyna_leave): |
b1f89e6f |
559 | ldr r0, [fp, #LO_last_count] |
7139f3c8 |
560 | add r12, fp, #28 |
561 | add r10, r0, r10 |
b1f89e6f |
562 | str r10, [fp, #LO_cycle] |
b021ee75 |
563 | ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
7139f3c8 |
564 | .size new_dyna_leave, .-new_dyna_leave |
565 | |
0bbd1454 |
566 | .align 2 |
5c6457c3 |
567 | FUNCTION(invalidate_addr_r0): |
5df0e313 |
568 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
0bbd1454 |
569 | b invalidate_addr_call |
570 | .size invalidate_addr_r0, .-invalidate_addr_r0 |
571 | .align 2 |
5c6457c3 |
572 | FUNCTION(invalidate_addr_r1): |
5df0e313 |
573 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
574 | mov r0, r1 |
0bbd1454 |
575 | b invalidate_addr_call |
576 | .size invalidate_addr_r1, .-invalidate_addr_r1 |
577 | .align 2 |
5c6457c3 |
578 | FUNCTION(invalidate_addr_r2): |
5df0e313 |
579 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
580 | mov r0, r2 |
0bbd1454 |
581 | b invalidate_addr_call |
582 | .size invalidate_addr_r2, .-invalidate_addr_r2 |
583 | .align 2 |
5c6457c3 |
584 | FUNCTION(invalidate_addr_r3): |
5df0e313 |
585 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
586 | mov r0, r3 |
0bbd1454 |
587 | b invalidate_addr_call |
588 | .size invalidate_addr_r3, .-invalidate_addr_r3 |
589 | .align 2 |
5c6457c3 |
590 | FUNCTION(invalidate_addr_r4): |
5df0e313 |
591 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
592 | mov r0, r4 |
0bbd1454 |
593 | b invalidate_addr_call |
594 | .size invalidate_addr_r4, .-invalidate_addr_r4 |
595 | .align 2 |
5c6457c3 |
596 | FUNCTION(invalidate_addr_r5): |
5df0e313 |
597 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
598 | mov r0, r5 |
0bbd1454 |
599 | b invalidate_addr_call |
600 | .size invalidate_addr_r5, .-invalidate_addr_r5 |
601 | .align 2 |
5c6457c3 |
602 | FUNCTION(invalidate_addr_r6): |
5df0e313 |
603 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
604 | mov r0, r6 |
0bbd1454 |
605 | b invalidate_addr_call |
606 | .size invalidate_addr_r6, .-invalidate_addr_r6 |
607 | .align 2 |
5c6457c3 |
608 | FUNCTION(invalidate_addr_r7): |
5df0e313 |
609 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
610 | mov r0, r7 |
0bbd1454 |
611 | b invalidate_addr_call |
612 | .size invalidate_addr_r7, .-invalidate_addr_r7 |
613 | .align 2 |
5c6457c3 |
614 | FUNCTION(invalidate_addr_r8): |
5df0e313 |
615 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
616 | mov r0, r8 |
0bbd1454 |
617 | b invalidate_addr_call |
618 | .size invalidate_addr_r8, .-invalidate_addr_r8 |
619 | .align 2 |
5c6457c3 |
620 | FUNCTION(invalidate_addr_r9): |
5df0e313 |
621 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
622 | mov r0, r9 |
0bbd1454 |
623 | b invalidate_addr_call |
624 | .size invalidate_addr_r9, .-invalidate_addr_r9 |
625 | .align 2 |
5c6457c3 |
626 | FUNCTION(invalidate_addr_r10): |
5df0e313 |
627 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
628 | mov r0, r10 |
0bbd1454 |
629 | b invalidate_addr_call |
630 | .size invalidate_addr_r10, .-invalidate_addr_r10 |
631 | .align 2 |
5c6457c3 |
632 | FUNCTION(invalidate_addr_r12): |
5df0e313 |
633 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
634 | mov r0, r12 |
0bbd1454 |
635 | .size invalidate_addr_r12, .-invalidate_addr_r12 |
636 | .align 2 |
b1f89e6f |
637 | invalidate_addr_call: |
638 | ldr r12, [fp, #LO_inv_code_start] |
639 | ldr lr, [fp, #LO_inv_code_end] |
9be4ba64 |
640 | cmp r0, r12 |
641 | cmpcs lr, r0 |
642 | blcc invalidate_addr |
5df0e313 |
643 | ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc} |
0bbd1454 |
644 | .size invalidate_addr_call, .-invalidate_addr_call |
645 | |
57871462 |
646 | .align 2 |
5c6457c3 |
647 | FUNCTION(new_dyna_start): |
b021ee75 |
648 | /* ip is stored to conform EABI alignment */ |
649 | stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
be516ebe |
650 | mov fp, r0 /* dynarec_local */ |
b1f89e6f |
651 | ldr r0, [fp, #LO_pcaddr] |
7139f3c8 |
652 | bl get_addr_ht |
b1f89e6f |
653 | ldr r1, [fp, #LO_next_interupt] |
654 | ldr r10, [fp, #LO_cycle] |
655 | str r1, [fp, #LO_last_count] |
7139f3c8 |
656 | sub r10, r10, r1 |
657 | mov pc, r0 |
57871462 |
658 | .size new_dyna_start, .-new_dyna_start |
7139f3c8 |
659 | |
7e605697 |
660 | /* --------------------------------------- */ |
7139f3c8 |
661 | |
7e605697 |
662 | .align 2 |
c6c3b1b3 |
663 | |
664 | .macro pcsx_read_mem readop tab_shift |
665 | /* r0 = address, r1 = handler_tab, r2 = cycles */ |
666 | lsl r3, r0, #20 |
667 | lsr r3, #(20+\tab_shift) |
b1f89e6f |
668 | ldr r12, [fp, #LO_last_count] |
c6c3b1b3 |
669 | ldr r1, [r1, r3, lsl #2] |
670 | add r2, r2, r12 |
671 | lsls r1, #1 |
672 | .if \tab_shift == 1 |
673 | lsl r3, #1 |
674 | \readop r0, [r1, r3] |
675 | .else |
676 | \readop r0, [r1, r3, lsl #\tab_shift] |
677 | .endif |
678 | movcc pc, lr |
b1f89e6f |
679 | str r2, [fp, #LO_cycle] |
c6c3b1b3 |
680 | bx r1 |
681 | .endm |
682 | |
5c6457c3 |
683 | FUNCTION(jump_handler_read8): |
c6c3b1b3 |
684 | add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
685 | pcsx_read_mem ldrbcc, 0 |
c6c3b1b3 |
686 | |
5c6457c3 |
687 | FUNCTION(jump_handler_read16): |
c6c3b1b3 |
688 | add r1, #0x1000/4*4 @ shift to r16 part |
10858959 |
689 | pcsx_read_mem ldrhcc, 1 |
c6c3b1b3 |
690 | |
5c6457c3 |
691 | FUNCTION(jump_handler_read32): |
c6c3b1b3 |
692 | pcsx_read_mem ldrcc, 2 |
693 | |
b96d3df7 |
694 | |
695 | .macro pcsx_write_mem wrtop tab_shift |
696 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */ |
697 | lsl r12,r0, #20 |
698 | lsr r12, #(20+\tab_shift) |
699 | ldr r3, [r3, r12, lsl #2] |
b1f89e6f |
700 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
701 | lsls r3, #1 |
702 | mov r0, r2 @ cycle return in case of direct store |
703 | .if \tab_shift == 1 |
704 | lsl r12, #1 |
705 | \wrtop r1, [r3, r12] |
706 | .else |
707 | \wrtop r1, [r3, r12, lsl #\tab_shift] |
708 | .endif |
709 | movcc pc, lr |
b1f89e6f |
710 | ldr r12, [fp, #LO_last_count] |
b96d3df7 |
711 | mov r0, r1 |
712 | add r2, r2, r12 |
713 | push {r2, lr} |
b1f89e6f |
714 | str r2, [fp, #LO_cycle] |
b96d3df7 |
715 | blx r3 |
716 | |
b1f89e6f |
717 | ldr r0, [fp, #LO_next_interupt] |
687b4580 |
718 | pop {r2, lr} |
b1f89e6f |
719 | str r0, [fp, #LO_last_count] |
b96d3df7 |
720 | sub r0, r2, r0 |
687b4580 |
721 | bx lr |
b96d3df7 |
722 | .endm |
723 | |
5c6457c3 |
724 | FUNCTION(jump_handler_write8): |
b96d3df7 |
725 | add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
726 | pcsx_write_mem strbcc, 0 |
b96d3df7 |
727 | |
5c6457c3 |
728 | FUNCTION(jump_handler_write16): |
b96d3df7 |
729 | add r3, #0x1000/4*4 @ shift to r16 part |
b861c0a9 |
730 | pcsx_write_mem strhcc, 1 |
b96d3df7 |
731 | |
5c6457c3 |
732 | FUNCTION(jump_handler_write32): |
b96d3df7 |
733 | pcsx_write_mem strcc, 2 |
734 | |
5c6457c3 |
735 | FUNCTION(jump_handler_write_h): |
b96d3df7 |
736 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler */ |
b1f89e6f |
737 | ldr r12, [fp, #LO_last_count] |
738 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
739 | add r2, r2, r12 |
740 | mov r0, r1 |
741 | push {r2, lr} |
b1f89e6f |
742 | str r2, [fp, #LO_cycle] |
b96d3df7 |
743 | blx r3 |
744 | |
b1f89e6f |
745 | ldr r0, [fp, #LO_next_interupt] |
687b4580 |
746 | pop {r2, lr} |
b1f89e6f |
747 | str r0, [fp, #LO_last_count] |
b96d3df7 |
748 | sub r0, r2, r0 |
687b4580 |
749 | bx lr |
b96d3df7 |
750 | |
5c6457c3 |
751 | FUNCTION(jump_handle_swl): |
b96d3df7 |
752 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
753 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
754 | mov r12,r0,lsr #12 |
755 | ldr r3, [r3, r12, lsl #2] |
756 | lsls r3, #1 |
757 | bcs 4f |
758 | add r3, r0, r3 |
759 | mov r0, r2 |
760 | tst r3, #2 |
761 | beq 101f |
762 | tst r3, #1 |
763 | beq 2f |
764 | 3: |
765 | str r1, [r3, #-3] |
766 | bx lr |
767 | 2: |
768 | lsr r2, r1, #8 |
769 | lsr r1, #24 |
770 | strh r2, [r3, #-2] |
771 | strb r1, [r3] |
772 | bx lr |
773 | 101: |
774 | tst r3, #1 |
775 | lsrne r1, #16 @ 1 |
776 | lsreq r12, r1, #24 @ 0 |
b861c0a9 |
777 | strhne r1, [r3, #-1] |
778 | strbeq r12, [r3] |
b96d3df7 |
779 | bx lr |
780 | 4: |
781 | mov r0, r2 |
63cb0298 |
782 | @ b abort |
b96d3df7 |
783 | bx lr @ TODO? |
784 | |
785 | |
5c6457c3 |
786 | FUNCTION(jump_handle_swr): |
b96d3df7 |
787 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
788 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
789 | mov r12,r0,lsr #12 |
790 | ldr r3, [r3, r12, lsl #2] |
791 | lsls r3, #1 |
792 | bcs 4f |
793 | add r3, r0, r3 |
794 | and r12,r3, #3 |
795 | mov r0, r2 |
796 | cmp r12,#2 |
b861c0a9 |
797 | strbgt r1, [r3] @ 3 |
798 | strheq r1, [r3] @ 2 |
b96d3df7 |
799 | cmp r12,#1 |
800 | strlt r1, [r3] @ 0 |
801 | bxne lr |
802 | lsr r2, r1, #8 @ 1 |
803 | strb r1, [r3] |
804 | strh r2, [r3, #1] |
805 | bx lr |
806 | 4: |
807 | mov r0, r2 |
63cb0298 |
808 | @ b abort |
b96d3df7 |
809 | bx lr @ TODO? |
810 | |
811 | |
b1be1eee |
812 | .macro rcntx_read_mode0 num |
813 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
814 | ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart |
b1be1eee |
815 | mov r0, r2, lsl #16 |
b861c0a9 |
816 | sub r0, r0, r3, lsl #16 |
b1be1eee |
817 | lsr r0, #16 |
818 | bx lr |
819 | .endm |
820 | |
5c6457c3 |
821 | FUNCTION(rcnt0_read_count_m0): |
b1be1eee |
822 | rcntx_read_mode0 0 |
823 | |
5c6457c3 |
824 | FUNCTION(rcnt1_read_count_m0): |
b1be1eee |
825 | rcntx_read_mode0 1 |
826 | |
5c6457c3 |
827 | FUNCTION(rcnt2_read_count_m0): |
b1be1eee |
828 | rcntx_read_mode0 2 |
829 | |
5c6457c3 |
830 | FUNCTION(rcnt0_read_count_m1): |
b1be1eee |
831 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
832 | ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart |
b1be1eee |
833 | mov_16 r1, 0x3334 |
834 | sub r2, r2, r3 |
835 | mul r0, r1, r2 @ /= 5 |
836 | lsr r0, #16 |
837 | bx lr |
838 | |
5c6457c3 |
839 | FUNCTION(rcnt1_read_count_m1): |
b1be1eee |
840 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
841 | ldr r3, [fp, #LO_rcnts+6*4+7*4*1] |
b1be1eee |
842 | mov_24 r1, 0x1e6cde |
843 | sub r2, r2, r3 |
844 | umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd |
845 | bx lr |
846 | |
5c6457c3 |
847 | FUNCTION(rcnt2_read_count_m1): |
b1be1eee |
848 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
849 | ldr r3, [fp, #LO_rcnts+6*4+7*4*2] |
b1be1eee |
850 | mov r0, r2, lsl #16-3 |
b861c0a9 |
851 | sub r0, r0, r3, lsl #16-3 |
b1be1eee |
852 | lsr r0, #16 @ /= 8 |
853 | bx lr |
854 | |
7e605697 |
855 | @ vim:filetype=armasm |