57871462 |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
7e605697 |
2 | * linkage_arm.s for PCSX * |
0bbd1454 |
3 | * Copyright (C) 2009-2011 Ari64 * |
b1f89e6f |
4 | * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas * |
57871462 |
5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
b021ee75 |
21 | |
665f33e1 |
22 | #include "arm_features.h" |
630b122b |
23 | #include "new_dynarec_config.h" |
b1f89e6f |
24 | #include "linkage_offsets.h" |
25 | |
26 | |
27 | #ifdef __MACH__ |
28 | #define dynarec_local ESYM(dynarec_local) |
630b122b |
29 | #define add_jump_out ESYM(add_jump_out) |
b1f89e6f |
30 | #define new_recompile_block ESYM(new_recompile_block) |
31 | #define get_addr ESYM(get_addr) |
32 | #define get_addr_ht ESYM(get_addr_ht) |
33 | #define clean_blocks ESYM(clean_blocks) |
34 | #define gen_interupt ESYM(gen_interupt) |
b1f89e6f |
35 | #define invalidate_addr ESYM(invalidate_addr) |
630b122b |
36 | #define gteCheckStallRaw ESYM(gteCheckStallRaw) |
467357cc |
37 | #define psxException ESYM(psxException) |
b1f89e6f |
38 | #endif |
f95a77f7 |
39 | |
57871462 |
40 | .bss |
41 | .align 4 |
b1f89e6f |
42 | .global dynarec_local |
57871462 |
43 | .type dynarec_local, %object |
b1f89e6f |
44 | .size dynarec_local, LO_dynarec_local_size |
57871462 |
45 | dynarec_local: |
b1f89e6f |
46 | .space LO_dynarec_local_size |
47 | |
48 | #define DRC_VAR_(name, vname, size_) \ |
49 | vname = dynarec_local + LO_##name; \ |
50 | .global vname; \ |
51 | .type vname, %object; \ |
52 | .size vname, size_ |
53 | |
54 | #define DRC_VAR(name, size_) \ |
55 | DRC_VAR_(name, ESYM(name), size_) |
56 | |
57 | DRC_VAR(next_interupt, 4) |
58 | DRC_VAR(cycle_count, 4) |
59 | DRC_VAR(last_count, 4) |
60 | DRC_VAR(pending_exception, 4) |
61 | DRC_VAR(stop, 4) |
630b122b |
62 | DRC_VAR(branch_target, 4) |
b1f89e6f |
63 | DRC_VAR(address, 4) |
7c8454e3 |
64 | DRC_VAR(hack_addr, 4) |
b1f89e6f |
65 | DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs) |
f95a77f7 |
66 | |
67 | /* psxRegs */ |
630b122b |
68 | @DRC_VAR(reg, 128) |
b1f89e6f |
69 | DRC_VAR(lo, 4) |
70 | DRC_VAR(hi, 4) |
71 | DRC_VAR(reg_cop0, 128) |
72 | DRC_VAR(reg_cop2d, 128) |
73 | DRC_VAR(reg_cop2c, 128) |
74 | DRC_VAR(pcaddr, 4) |
75 | @DRC_VAR(code, 4) |
76 | @DRC_VAR(cycle, 4) |
77 | @DRC_VAR(interrupt, 4) |
78 | @DRC_VAR(intCycle, 256) |
79 | |
80 | DRC_VAR(rcnts, 7*4*4) |
630b122b |
81 | DRC_VAR(inv_code_start, 4) |
82 | DRC_VAR(inv_code_end, 4) |
b1f89e6f |
83 | DRC_VAR(mem_rtab, 4) |
84 | DRC_VAR(mem_wtab, 4) |
85 | DRC_VAR(psxH_ptr, 4) |
86 | DRC_VAR(zeromem_ptr, 4) |
630b122b |
87 | DRC_VAR(invc_ptr, 4) |
c6d5790c |
88 | DRC_VAR(scratch_buf_ptr, 4) |
630b122b |
89 | DRC_VAR(ram_offset, 4) |
b1f89e6f |
90 | DRC_VAR(mini_ht, 256) |
91 | DRC_VAR(restore_candidate, 512) |
63cb0298 |
92 | |
57871462 |
93 | |
0e4ad319 |
94 | #ifdef TEXRELS_FORBIDDEN |
b861c0a9 |
95 | .data |
96 | .align 2 |
97 | ptr_jump_in: |
98 | .word ESYM(jump_in) |
99 | ptr_jump_dirty: |
100 | .word ESYM(jump_dirty) |
101 | ptr_hash_table: |
102 | .word ESYM(hash_table) |
103 | #endif |
104 | |
105 | |
106 | .syntax unified |
107 | .text |
108 | .align 2 |
109 | |
665f33e1 |
110 | #ifndef HAVE_ARMV5 |
111 | .macro blx rd |
112 | mov lr, pc |
113 | bx \rd |
114 | .endm |
115 | #endif |
116 | |
c67af2ac |
117 | .macro load_varadr reg var |
0e4ad319 |
118 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
1f4e070a |
119 | movw \reg, #:lower16:(\var-(1678f+8)) |
120 | movt \reg, #:upper16:(\var-(1678f+8)) |
b861c0a9 |
121 | 1678: |
122 | add \reg, pc |
0e4ad319 |
123 | #elif defined(HAVE_ARMV7) && !defined(__PIC__) |
124 | movw \reg, #:lower16:\var |
125 | movt \reg, #:upper16:\var |
c67af2ac |
126 | #else |
274c4243 |
127 | ldr \reg, =\var |
c67af2ac |
128 | #endif |
274c4243 |
129 | .endm |
130 | |
b861c0a9 |
131 | .macro load_varadr_ext reg var |
0e4ad319 |
132 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
1f4e070a |
133 | movw \reg, #:lower16:(ptr_\var-(1678f+8)) |
134 | movt \reg, #:upper16:(ptr_\var-(1678f+8)) |
b861c0a9 |
135 | 1678: |
136 | ldr \reg, [pc, \reg] |
137 | #else |
138 | load_varadr \reg \var |
139 | #endif |
140 | .endm |
141 | |
b1be1eee |
142 | .macro mov_16 reg imm |
8f2bb0cb |
143 | #ifdef HAVE_ARMV7 |
b1be1eee |
144 | movw \reg, #\imm |
c67af2ac |
145 | #else |
b1be1eee |
146 | mov \reg, #(\imm & 0x00ff) |
147 | orr \reg, #(\imm & 0xff00) |
c67af2ac |
148 | #endif |
b1be1eee |
149 | .endm |
150 | |
151 | .macro mov_24 reg imm |
8f2bb0cb |
152 | #ifdef HAVE_ARMV7 |
b1be1eee |
153 | movw \reg, #(\imm & 0xffff) |
154 | movt \reg, #(\imm >> 16) |
c67af2ac |
155 | #else |
b1be1eee |
156 | mov \reg, #(\imm & 0x0000ff) |
157 | orr \reg, #(\imm & 0x00ff00) |
158 | orr \reg, #(\imm & 0xff0000) |
c67af2ac |
159 | #endif |
b1be1eee |
160 | .endm |
161 | |
d148d265 |
162 | /* r0 = virtual target address */ |
163 | /* r1 = instruction to patch */ |
76f71c27 |
164 | .macro dyna_linker_main |
d148d265 |
165 | #ifndef NO_WRITE_EXEC |
b861c0a9 |
166 | load_varadr_ext r3, jump_in |
f968d35d |
167 | /* get_page */ |
168 | lsr r2, r0, #12 |
169 | mov r6, #4096 |
170 | bic r2, r2, #0xe0000 |
57871462 |
171 | sub r6, r6, #1 |
f968d35d |
172 | cmp r2, #0x1000 |
57871462 |
173 | ldr r7, [r1] |
f968d35d |
174 | biclt r2, #0x0e00 |
175 | and r6, r6, r2 |
57871462 |
176 | cmp r2, #2048 |
177 | add r12, r7, #2 |
178 | orrcs r2, r6, #2048 |
179 | ldr r5, [r3, r2, lsl #2] |
180 | lsl r12, r12, #8 |
630b122b |
181 | add r6, r1, r12, asr #6 /* old target */ |
76f71c27 |
182 | mov r8, #0 |
57871462 |
183 | /* jump_in lookup */ |
76f71c27 |
184 | 1: |
57871462 |
185 | movs r4, r5 |
76f71c27 |
186 | beq 2f |
de5a60c3 |
187 | ldr r3, [r5] /* ll_entry .vaddr */ |
188 | ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */ |
57871462 |
189 | teq r3, r0 |
76f71c27 |
190 | bne 1b |
76f71c27 |
191 | teq r4, r6 |
57871462 |
192 | moveq pc, r4 /* Stale i-cache */ |
76f71c27 |
193 | mov r8, r4 |
194 | b 1b /* jump_in may have dupes, continue search */ |
195 | 2: |
196 | tst r8, r8 |
197 | beq 3f /* r0 not in jump_in */ |
198 | |
199 | mov r5, r1 |
200 | mov r1, r6 |
630b122b |
201 | bl add_jump_out |
76f71c27 |
202 | sub r2, r8, r5 |
57871462 |
203 | and r1, r7, #0xff000000 |
204 | lsl r2, r2, #6 |
205 | sub r1, r1, #2 |
206 | add r1, r1, r2, lsr #8 |
207 | str r1, [r5] |
76f71c27 |
208 | mov pc, r8 |
209 | 3: |
57871462 |
210 | /* hash_table lookup */ |
211 | cmp r2, #2048 |
b861c0a9 |
212 | load_varadr_ext r3, jump_dirty |
57871462 |
213 | eor r4, r0, r0, lsl #16 |
214 | lslcc r2, r0, #9 |
b861c0a9 |
215 | load_varadr_ext r6, hash_table |
57871462 |
216 | lsr r4, r4, #12 |
217 | lsrcc r2, r2, #21 |
218 | bic r4, r4, #15 |
219 | ldr r5, [r3, r2, lsl #2] |
220 | ldr r7, [r6, r4]! |
221 | teq r7, r0 |
630b122b |
222 | ldreq pc, [r6, #8] |
223 | ldr r7, [r6, #4] |
57871462 |
224 | teq r7, r0 |
225 | ldreq pc, [r6, #12] |
226 | /* jump_dirty lookup */ |
76f71c27 |
227 | 6: |
57871462 |
228 | movs r4, r5 |
76f71c27 |
229 | beq 8f |
57871462 |
230 | ldr r3, [r5] |
231 | ldr r5, [r4, #12] |
232 | teq r3, r0 |
76f71c27 |
233 | bne 6b |
234 | 7: |
57871462 |
235 | ldr r1, [r4, #8] |
236 | /* hash_table insert */ |
237 | ldr r2, [r6] |
630b122b |
238 | ldr r3, [r6, #8] |
57871462 |
239 | str r0, [r6] |
630b122b |
240 | str r1, [r6, #8] |
241 | str r2, [r6, #4] |
57871462 |
242 | str r3, [r6, #12] |
243 | mov pc, r1 |
76f71c27 |
244 | 8: |
d148d265 |
245 | #else |
246 | /* XXX: should be able to do better than this... */ |
247 | bl get_addr_ht |
248 | mov pc, r0 |
249 | #endif |
76f71c27 |
250 | .endm |
251 | |
5c6457c3 |
252 | |
253 | FUNCTION(dyna_linker): |
76f71c27 |
254 | /* r0 = virtual target address */ |
255 | /* r1 = instruction to patch */ |
256 | dyna_linker_main |
257 | |
57871462 |
258 | mov r4, r0 |
259 | mov r5, r1 |
260 | bl new_recompile_block |
261 | tst r0, r0 |
262 | mov r0, r4 |
263 | mov r1, r5 |
264 | beq dyna_linker |
265 | /* pagefault */ |
266 | mov r1, r0 |
267 | mov r2, #8 |
268 | .size dyna_linker, .-dyna_linker |
5c6457c3 |
269 | |
270 | FUNCTION(exec_pagefault): |
57871462 |
271 | /* r0 = instruction pointer */ |
272 | /* r1 = fault address */ |
273 | /* r2 = cause */ |
b1f89e6f |
274 | ldr r3, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
275 | mvn r6, #0xF000000F |
b1f89e6f |
276 | ldr r4, [fp, #LO_reg_cop0+16] /* Context */ |
57871462 |
277 | bic r6, r6, #0x0F800000 |
b1f89e6f |
278 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
57871462 |
279 | orr r3, r3, #2 |
b1f89e6f |
280 | str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */ |
57871462 |
281 | bic r4, r4, r6 |
b1f89e6f |
282 | str r3, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
283 | and r5, r6, r1, lsr #9 |
b1f89e6f |
284 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
57871462 |
285 | and r1, r1, r6, lsl #9 |
b1f89e6f |
286 | str r1, [fp, #LO_reg_cop0+40] /* EntryHi */ |
57871462 |
287 | orr r4, r4, r5 |
b1f89e6f |
288 | str r4, [fp, #LO_reg_cop0+16] /* Context */ |
57871462 |
289 | mov r0, #0x80000000 |
290 | bl get_addr_ht |
291 | mov pc, r0 |
292 | .size exec_pagefault, .-exec_pagefault |
7139f3c8 |
293 | |
57871462 |
294 | /* Special dynamic linker for the case where a page fault |
295 | may occur in a branch delay slot */ |
5c6457c3 |
296 | FUNCTION(dyna_linker_ds): |
57871462 |
297 | /* r0 = virtual target address */ |
298 | /* r1 = instruction to patch */ |
76f71c27 |
299 | dyna_linker_main |
300 | |
57871462 |
301 | mov r4, r0 |
302 | bic r0, r0, #7 |
303 | mov r5, r1 |
304 | orr r0, r0, #1 |
305 | bl new_recompile_block |
306 | tst r0, r0 |
307 | mov r0, r4 |
308 | mov r1, r5 |
309 | beq dyna_linker_ds |
310 | /* pagefault */ |
311 | bic r1, r0, #7 |
312 | mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */ |
313 | sub r0, r1, #4 |
314 | b exec_pagefault |
315 | .size dyna_linker_ds, .-dyna_linker_ds |
7139f3c8 |
316 | |
57871462 |
317 | .align 2 |
5c6457c3 |
318 | |
319 | FUNCTION(jump_vaddr_r0): |
57871462 |
320 | eor r2, r0, r0, lsl #16 |
321 | b jump_vaddr |
322 | .size jump_vaddr_r0, .-jump_vaddr_r0 |
5c6457c3 |
323 | FUNCTION(jump_vaddr_r1): |
57871462 |
324 | eor r2, r1, r1, lsl #16 |
325 | mov r0, r1 |
326 | b jump_vaddr |
327 | .size jump_vaddr_r1, .-jump_vaddr_r1 |
5c6457c3 |
328 | FUNCTION(jump_vaddr_r2): |
57871462 |
329 | mov r0, r2 |
330 | eor r2, r2, r2, lsl #16 |
331 | b jump_vaddr |
332 | .size jump_vaddr_r2, .-jump_vaddr_r2 |
5c6457c3 |
333 | FUNCTION(jump_vaddr_r3): |
57871462 |
334 | eor r2, r3, r3, lsl #16 |
335 | mov r0, r3 |
336 | b jump_vaddr |
337 | .size jump_vaddr_r3, .-jump_vaddr_r3 |
5c6457c3 |
338 | FUNCTION(jump_vaddr_r4): |
57871462 |
339 | eor r2, r4, r4, lsl #16 |
340 | mov r0, r4 |
341 | b jump_vaddr |
342 | .size jump_vaddr_r4, .-jump_vaddr_r4 |
5c6457c3 |
343 | FUNCTION(jump_vaddr_r5): |
57871462 |
344 | eor r2, r5, r5, lsl #16 |
345 | mov r0, r5 |
346 | b jump_vaddr |
347 | .size jump_vaddr_r5, .-jump_vaddr_r5 |
5c6457c3 |
348 | FUNCTION(jump_vaddr_r6): |
57871462 |
349 | eor r2, r6, r6, lsl #16 |
350 | mov r0, r6 |
351 | b jump_vaddr |
352 | .size jump_vaddr_r6, .-jump_vaddr_r6 |
5c6457c3 |
353 | FUNCTION(jump_vaddr_r8): |
57871462 |
354 | eor r2, r8, r8, lsl #16 |
355 | mov r0, r8 |
356 | b jump_vaddr |
357 | .size jump_vaddr_r8, .-jump_vaddr_r8 |
5c6457c3 |
358 | FUNCTION(jump_vaddr_r9): |
57871462 |
359 | eor r2, r9, r9, lsl #16 |
360 | mov r0, r9 |
361 | b jump_vaddr |
362 | .size jump_vaddr_r9, .-jump_vaddr_r9 |
5c6457c3 |
363 | FUNCTION(jump_vaddr_r10): |
57871462 |
364 | eor r2, r10, r10, lsl #16 |
365 | mov r0, r10 |
366 | b jump_vaddr |
367 | .size jump_vaddr_r10, .-jump_vaddr_r10 |
5c6457c3 |
368 | FUNCTION(jump_vaddr_r12): |
57871462 |
369 | eor r2, r12, r12, lsl #16 |
370 | mov r0, r12 |
371 | b jump_vaddr |
372 | .size jump_vaddr_r12, .-jump_vaddr_r12 |
5c6457c3 |
373 | FUNCTION(jump_vaddr_r7): |
57871462 |
374 | eor r2, r7, r7, lsl #16 |
375 | add r0, r7, #0 |
376 | .size jump_vaddr_r7, .-jump_vaddr_r7 |
5c6457c3 |
377 | FUNCTION(jump_vaddr): |
b861c0a9 |
378 | load_varadr_ext r1, hash_table |
57871462 |
379 | mvn r3, #15 |
380 | and r2, r3, r2, lsr #12 |
381 | ldr r2, [r1, r2]! |
382 | teq r2, r0 |
630b122b |
383 | ldreq pc, [r1, #8] |
384 | ldr r2, [r1, #4] |
57871462 |
385 | teq r2, r0 |
386 | ldreq pc, [r1, #12] |
b1f89e6f |
387 | str r10, [fp, #LO_cycle_count] |
57871462 |
388 | bl get_addr |
b1f89e6f |
389 | ldr r10, [fp, #LO_cycle_count] |
57871462 |
390 | mov pc, r0 |
391 | .size jump_vaddr, .-jump_vaddr |
7139f3c8 |
392 | |
57871462 |
393 | .align 2 |
5c6457c3 |
394 | |
395 | FUNCTION(verify_code_ds): |
630b122b |
396 | str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG? |
5c6457c3 |
397 | FUNCTION(verify_code): |
57871462 |
398 | /* r1 = source */ |
399 | /* r2 = target */ |
400 | /* r3 = length */ |
401 | tst r3, #4 |
402 | mov r4, #0 |
403 | add r3, r1, r3 |
404 | mov r5, #0 |
405 | ldrne r4, [r1], #4 |
406 | mov r12, #0 |
407 | ldrne r5, [r2], #4 |
408 | teq r1, r3 |
409 | beq .D3 |
410 | .D2: |
411 | ldr r7, [r1], #4 |
412 | eor r9, r4, r5 |
413 | ldr r8, [r2], #4 |
414 | orrs r9, r9, r12 |
415 | bne .D4 |
416 | ldr r4, [r1], #4 |
417 | eor r12, r7, r8 |
418 | ldr r5, [r2], #4 |
419 | cmp r1, r3 |
420 | bcc .D2 |
421 | teq r7, r8 |
422 | .D3: |
423 | teqeq r4, r5 |
424 | .D4: |
b1f89e6f |
425 | ldr r8, [fp, #LO_branch_target] |
57871462 |
426 | moveq pc, lr |
427 | .D5: |
428 | bl get_addr |
429 | mov pc, r0 |
430 | .size verify_code, .-verify_code |
630b122b |
431 | .size verify_code_ds, .-verify_code_ds |
7139f3c8 |
432 | |
57871462 |
433 | .align 2 |
5c6457c3 |
434 | FUNCTION(cc_interrupt): |
b1f89e6f |
435 | ldr r0, [fp, #LO_last_count] |
57871462 |
436 | mov r1, #0 |
437 | mov r2, #0x1fc |
438 | add r10, r0, r10 |
b1f89e6f |
439 | str r1, [fp, #LO_pending_exception] |
57871462 |
440 | and r2, r2, r10, lsr #17 |
b1f89e6f |
441 | add r3, fp, #LO_restore_candidate |
442 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
443 | @@ str r10, [fp, #LO_reg_cop0+36] /* Count */ |
57871462 |
444 | ldr r4, [r2, r3] |
445 | mov r10, lr |
446 | tst r4, r4 |
447 | bne .E4 |
448 | .E1: |
449 | bl gen_interupt |
450 | mov lr, r10 |
b1f89e6f |
451 | ldr r10, [fp, #LO_cycle] |
452 | ldr r0, [fp, #LO_next_interupt] |
453 | ldr r1, [fp, #LO_pending_exception] |
454 | ldr r2, [fp, #LO_stop] |
455 | str r0, [fp, #LO_last_count] |
57871462 |
456 | sub r10, r10, r0 |
457 | tst r2, r2 |
b861c0a9 |
458 | ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
57871462 |
459 | tst r1, r1 |
460 | moveq pc, lr |
461 | .E2: |
b1f89e6f |
462 | ldr r0, [fp, #LO_pcaddr] |
57871462 |
463 | bl get_addr_ht |
464 | mov pc, r0 |
57871462 |
465 | .E4: |
466 | /* Move 'dirty' blocks to the 'clean' list */ |
467 | lsl r5, r2, #3 |
468 | str r1, [r2, r3] |
469 | .E5: |
470 | lsrs r4, r4, #1 |
471 | mov r0, r5 |
472 | add r5, r5, #1 |
473 | blcs clean_blocks |
474 | tst r5, #31 |
475 | bne .E5 |
476 | b .E1 |
57871462 |
477 | .size cc_interrupt, .-cc_interrupt |
7139f3c8 |
478 | |
57871462 |
479 | .align 2 |
5c6457c3 |
480 | FUNCTION(fp_exception): |
57871462 |
481 | mov r2, #0x10000000 |
482 | .E7: |
b1f89e6f |
483 | ldr r1, [fp, #LO_reg_cop0+48] /* Status */ |
57871462 |
484 | mov r3, #0x80000000 |
b1f89e6f |
485 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
57871462 |
486 | orr r1, #2 |
487 | add r2, r2, #0x2c |
b1f89e6f |
488 | str r1, [fp, #LO_reg_cop0+48] /* Status */ |
489 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
7139f3c8 |
490 | add r0, r3, #0x80 |
57871462 |
491 | bl get_addr_ht |
492 | mov pc, r0 |
493 | .size fp_exception, .-fp_exception |
494 | .align 2 |
5c6457c3 |
495 | FUNCTION(fp_exception_ds): |
57871462 |
496 | mov r2, #0x90000000 /* Set high bit if delay slot */ |
497 | b .E7 |
498 | .size fp_exception_ds, .-fp_exception_ds |
7139f3c8 |
499 | |
57871462 |
500 | .align 2 |
467357cc |
501 | FUNCTION(jump_break_ds): |
502 | mov r0, #0x24 |
503 | mov r1, #1 |
504 | b call_psxException |
505 | FUNCTION(jump_break): |
506 | mov r0, #0x24 |
507 | mov r1, #0 |
508 | b call_psxException |
509 | FUNCTION(jump_syscall_ds): |
510 | mov r0, #0x20 |
511 | mov r1, #1 |
512 | b call_psxException |
5c6457c3 |
513 | FUNCTION(jump_syscall): |
467357cc |
514 | mov r0, #0x20 |
515 | mov r1, #0 |
516 | |
517 | call_psxException: |
518 | ldr r3, [fp, #LO_last_count] |
519 | str r2, [fp, #LO_pcaddr] |
520 | add r10, r3, r10 |
521 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
522 | bl psxException |
7139f3c8 |
523 | |
b1f89e6f |
524 | /* note: psxException might do recursive recompiler call from it's HLE code, |
7139f3c8 |
525 | * so be ready for this */ |
630b122b |
526 | FUNCTION(jump_to_new_pc): |
b1f89e6f |
527 | ldr r1, [fp, #LO_next_interupt] |
528 | ldr r10, [fp, #LO_cycle] |
529 | ldr r0, [fp, #LO_pcaddr] |
822b27d1 |
530 | sub r10, r10, r1 |
b1f89e6f |
531 | str r1, [fp, #LO_last_count] |
7139f3c8 |
532 | bl get_addr_ht |
533 | mov pc, r0 |
630b122b |
534 | .size jump_to_new_pc, .-jump_to_new_pc |
0d16cda2 |
535 | |
7139f3c8 |
536 | .align 2 |
5c6457c3 |
537 | FUNCTION(new_dyna_leave): |
b1f89e6f |
538 | ldr r0, [fp, #LO_last_count] |
7139f3c8 |
539 | add r12, fp, #28 |
540 | add r10, r0, r10 |
b1f89e6f |
541 | str r10, [fp, #LO_cycle] |
b021ee75 |
542 | ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
7139f3c8 |
543 | .size new_dyna_leave, .-new_dyna_leave |
544 | |
0bbd1454 |
545 | .align 2 |
5c6457c3 |
546 | FUNCTION(invalidate_addr_r0): |
5df0e313 |
547 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
0bbd1454 |
548 | b invalidate_addr_call |
549 | .size invalidate_addr_r0, .-invalidate_addr_r0 |
550 | .align 2 |
5c6457c3 |
551 | FUNCTION(invalidate_addr_r1): |
5df0e313 |
552 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
553 | mov r0, r1 |
0bbd1454 |
554 | b invalidate_addr_call |
555 | .size invalidate_addr_r1, .-invalidate_addr_r1 |
556 | .align 2 |
5c6457c3 |
557 | FUNCTION(invalidate_addr_r2): |
5df0e313 |
558 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
559 | mov r0, r2 |
0bbd1454 |
560 | b invalidate_addr_call |
561 | .size invalidate_addr_r2, .-invalidate_addr_r2 |
562 | .align 2 |
5c6457c3 |
563 | FUNCTION(invalidate_addr_r3): |
5df0e313 |
564 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
565 | mov r0, r3 |
0bbd1454 |
566 | b invalidate_addr_call |
567 | .size invalidate_addr_r3, .-invalidate_addr_r3 |
568 | .align 2 |
5c6457c3 |
569 | FUNCTION(invalidate_addr_r4): |
5df0e313 |
570 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
571 | mov r0, r4 |
0bbd1454 |
572 | b invalidate_addr_call |
573 | .size invalidate_addr_r4, .-invalidate_addr_r4 |
574 | .align 2 |
5c6457c3 |
575 | FUNCTION(invalidate_addr_r5): |
5df0e313 |
576 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
577 | mov r0, r5 |
0bbd1454 |
578 | b invalidate_addr_call |
579 | .size invalidate_addr_r5, .-invalidate_addr_r5 |
580 | .align 2 |
5c6457c3 |
581 | FUNCTION(invalidate_addr_r6): |
5df0e313 |
582 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
583 | mov r0, r6 |
0bbd1454 |
584 | b invalidate_addr_call |
585 | .size invalidate_addr_r6, .-invalidate_addr_r6 |
586 | .align 2 |
5c6457c3 |
587 | FUNCTION(invalidate_addr_r7): |
5df0e313 |
588 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
589 | mov r0, r7 |
0bbd1454 |
590 | b invalidate_addr_call |
591 | .size invalidate_addr_r7, .-invalidate_addr_r7 |
592 | .align 2 |
5c6457c3 |
593 | FUNCTION(invalidate_addr_r8): |
5df0e313 |
594 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
595 | mov r0, r8 |
0bbd1454 |
596 | b invalidate_addr_call |
597 | .size invalidate_addr_r8, .-invalidate_addr_r8 |
598 | .align 2 |
5c6457c3 |
599 | FUNCTION(invalidate_addr_r9): |
5df0e313 |
600 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
601 | mov r0, r9 |
0bbd1454 |
602 | b invalidate_addr_call |
603 | .size invalidate_addr_r9, .-invalidate_addr_r9 |
604 | .align 2 |
5c6457c3 |
605 | FUNCTION(invalidate_addr_r10): |
5df0e313 |
606 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
607 | mov r0, r10 |
0bbd1454 |
608 | b invalidate_addr_call |
609 | .size invalidate_addr_r10, .-invalidate_addr_r10 |
610 | .align 2 |
5c6457c3 |
611 | FUNCTION(invalidate_addr_r12): |
5df0e313 |
612 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
613 | mov r0, r12 |
0bbd1454 |
614 | .size invalidate_addr_r12, .-invalidate_addr_r12 |
615 | .align 2 |
b1f89e6f |
616 | invalidate_addr_call: |
617 | ldr r12, [fp, #LO_inv_code_start] |
618 | ldr lr, [fp, #LO_inv_code_end] |
9be4ba64 |
619 | cmp r0, r12 |
620 | cmpcs lr, r0 |
621 | blcc invalidate_addr |
5df0e313 |
622 | ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc} |
0bbd1454 |
623 | .size invalidate_addr_call, .-invalidate_addr_call |
624 | |
57871462 |
625 | .align 2 |
5c6457c3 |
626 | FUNCTION(new_dyna_start): |
b021ee75 |
627 | /* ip is stored to conform EABI alignment */ |
628 | stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
630b122b |
629 | mov fp, r0 /* dynarec_local */ |
b1f89e6f |
630 | ldr r0, [fp, #LO_pcaddr] |
7139f3c8 |
631 | bl get_addr_ht |
b1f89e6f |
632 | ldr r1, [fp, #LO_next_interupt] |
633 | ldr r10, [fp, #LO_cycle] |
634 | str r1, [fp, #LO_last_count] |
7139f3c8 |
635 | sub r10, r10, r1 |
636 | mov pc, r0 |
57871462 |
637 | .size new_dyna_start, .-new_dyna_start |
7139f3c8 |
638 | |
7e605697 |
639 | /* --------------------------------------- */ |
7139f3c8 |
640 | |
7e605697 |
641 | .align 2 |
c6c3b1b3 |
642 | |
643 | .macro pcsx_read_mem readop tab_shift |
644 | /* r0 = address, r1 = handler_tab, r2 = cycles */ |
645 | lsl r3, r0, #20 |
646 | lsr r3, #(20+\tab_shift) |
b1f89e6f |
647 | ldr r12, [fp, #LO_last_count] |
c6c3b1b3 |
648 | ldr r1, [r1, r3, lsl #2] |
649 | add r2, r2, r12 |
650 | lsls r1, #1 |
651 | .if \tab_shift == 1 |
652 | lsl r3, #1 |
653 | \readop r0, [r1, r3] |
654 | .else |
655 | \readop r0, [r1, r3, lsl #\tab_shift] |
656 | .endif |
657 | movcc pc, lr |
b1f89e6f |
658 | str r2, [fp, #LO_cycle] |
c6c3b1b3 |
659 | bx r1 |
660 | .endm |
661 | |
5c6457c3 |
662 | FUNCTION(jump_handler_read8): |
c6c3b1b3 |
663 | add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
664 | pcsx_read_mem ldrbcc, 0 |
c6c3b1b3 |
665 | |
5c6457c3 |
666 | FUNCTION(jump_handler_read16): |
c6c3b1b3 |
667 | add r1, #0x1000/4*4 @ shift to r16 part |
10858959 |
668 | pcsx_read_mem ldrhcc, 1 |
c6c3b1b3 |
669 | |
5c6457c3 |
670 | FUNCTION(jump_handler_read32): |
c6c3b1b3 |
671 | pcsx_read_mem ldrcc, 2 |
672 | |
b96d3df7 |
673 | |
630b122b |
674 | .macro memhandler_post |
675 | ldr r0, [fp, #LO_next_interupt] |
676 | ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma |
677 | str r0, [fp, #LO_last_count] |
678 | sub r0, r2, r0 |
679 | .endm |
680 | |
b96d3df7 |
681 | .macro pcsx_write_mem wrtop tab_shift |
682 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */ |
683 | lsl r12,r0, #20 |
684 | lsr r12, #(20+\tab_shift) |
685 | ldr r3, [r3, r12, lsl #2] |
b1f89e6f |
686 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
687 | lsls r3, #1 |
630b122b |
688 | mov r0, r2 @ cycle return in case of direct store |
b96d3df7 |
689 | .if \tab_shift == 1 |
690 | lsl r12, #1 |
691 | \wrtop r1, [r3, r12] |
692 | .else |
693 | \wrtop r1, [r3, r12, lsl #\tab_shift] |
694 | .endif |
695 | movcc pc, lr |
b1f89e6f |
696 | ldr r12, [fp, #LO_last_count] |
b96d3df7 |
697 | mov r0, r1 |
698 | add r2, r2, r12 |
b1f89e6f |
699 | str r2, [fp, #LO_cycle] |
630b122b |
700 | |
701 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
702 | blx r3 |
630b122b |
703 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
704 | |
630b122b |
705 | memhandler_post |
706 | bx lr |
b96d3df7 |
707 | .endm |
708 | |
5c6457c3 |
709 | FUNCTION(jump_handler_write8): |
b96d3df7 |
710 | add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
711 | pcsx_write_mem strbcc, 0 |
b96d3df7 |
712 | |
5c6457c3 |
713 | FUNCTION(jump_handler_write16): |
b96d3df7 |
714 | add r3, #0x1000/4*4 @ shift to r16 part |
b861c0a9 |
715 | pcsx_write_mem strhcc, 1 |
b96d3df7 |
716 | |
5c6457c3 |
717 | FUNCTION(jump_handler_write32): |
b96d3df7 |
718 | pcsx_write_mem strcc, 2 |
719 | |
5c6457c3 |
720 | FUNCTION(jump_handler_write_h): |
b96d3df7 |
721 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler */ |
b1f89e6f |
722 | ldr r12, [fp, #LO_last_count] |
723 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
724 | add r2, r2, r12 |
725 | mov r0, r1 |
b1f89e6f |
726 | str r2, [fp, #LO_cycle] |
630b122b |
727 | |
728 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
729 | blx r3 |
630b122b |
730 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
731 | |
630b122b |
732 | memhandler_post |
733 | bx lr |
b96d3df7 |
734 | |
5c6457c3 |
735 | FUNCTION(jump_handle_swl): |
b96d3df7 |
736 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
737 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
738 | mov r12,r0,lsr #12 |
739 | ldr r3, [r3, r12, lsl #2] |
740 | lsls r3, #1 |
741 | bcs 4f |
742 | add r3, r0, r3 |
743 | mov r0, r2 |
744 | tst r3, #2 |
745 | beq 101f |
746 | tst r3, #1 |
747 | beq 2f |
748 | 3: |
749 | str r1, [r3, #-3] |
750 | bx lr |
751 | 2: |
752 | lsr r2, r1, #8 |
753 | lsr r1, #24 |
754 | strh r2, [r3, #-2] |
755 | strb r1, [r3] |
756 | bx lr |
757 | 101: |
758 | tst r3, #1 |
759 | lsrne r1, #16 @ 1 |
760 | lsreq r12, r1, #24 @ 0 |
b861c0a9 |
761 | strhne r1, [r3, #-1] |
762 | strbeq r12, [r3] |
b96d3df7 |
763 | bx lr |
764 | 4: |
765 | mov r0, r2 |
63cb0298 |
766 | @ b abort |
b96d3df7 |
767 | bx lr @ TODO? |
768 | |
769 | |
5c6457c3 |
770 | FUNCTION(jump_handle_swr): |
b96d3df7 |
771 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
772 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
773 | mov r12,r0,lsr #12 |
774 | ldr r3, [r3, r12, lsl #2] |
775 | lsls r3, #1 |
776 | bcs 4f |
777 | add r3, r0, r3 |
778 | and r12,r3, #3 |
779 | mov r0, r2 |
780 | cmp r12,#2 |
b861c0a9 |
781 | strbgt r1, [r3] @ 3 |
782 | strheq r1, [r3] @ 2 |
b96d3df7 |
783 | cmp r12,#1 |
784 | strlt r1, [r3] @ 0 |
785 | bxne lr |
786 | lsr r2, r1, #8 @ 1 |
787 | strb r1, [r3] |
788 | strh r2, [r3, #1] |
789 | bx lr |
790 | 4: |
791 | mov r0, r2 |
63cb0298 |
792 | @ b abort |
b96d3df7 |
793 | bx lr @ TODO? |
794 | |
795 | |
b1be1eee |
796 | .macro rcntx_read_mode0 num |
797 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
798 | ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart |
b1be1eee |
799 | mov r0, r2, lsl #16 |
b861c0a9 |
800 | sub r0, r0, r3, lsl #16 |
b1be1eee |
801 | lsr r0, #16 |
802 | bx lr |
803 | .endm |
804 | |
5c6457c3 |
805 | FUNCTION(rcnt0_read_count_m0): |
b1be1eee |
806 | rcntx_read_mode0 0 |
807 | |
5c6457c3 |
808 | FUNCTION(rcnt1_read_count_m0): |
b1be1eee |
809 | rcntx_read_mode0 1 |
810 | |
5c6457c3 |
811 | FUNCTION(rcnt2_read_count_m0): |
b1be1eee |
812 | rcntx_read_mode0 2 |
813 | |
5c6457c3 |
814 | FUNCTION(rcnt0_read_count_m1): |
b1be1eee |
815 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
816 | ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart |
b1be1eee |
817 | mov_16 r1, 0x3334 |
818 | sub r2, r2, r3 |
819 | mul r0, r1, r2 @ /= 5 |
820 | lsr r0, #16 |
821 | bx lr |
822 | |
5c6457c3 |
823 | FUNCTION(rcnt1_read_count_m1): |
b1be1eee |
824 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
825 | ldr r3, [fp, #LO_rcnts+6*4+7*4*1] |
b1be1eee |
826 | mov_24 r1, 0x1e6cde |
827 | sub r2, r2, r3 |
828 | umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd |
829 | bx lr |
830 | |
5c6457c3 |
831 | FUNCTION(rcnt2_read_count_m1): |
b1be1eee |
832 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
833 | ldr r3, [fp, #LO_rcnts+6*4+7*4*2] |
b1be1eee |
834 | mov r0, r2, lsl #16-3 |
b861c0a9 |
835 | sub r0, r0, r3, lsl #16-3 |
b1be1eee |
836 | lsr r0, #16 @ /= 8 |
837 | bx lr |
838 | |
630b122b |
839 | FUNCTION(call_gteStall): |
840 | /* r0 = op_cycles, r1 = cycles */ |
841 | ldr r2, [fp, #LO_last_count] |
842 | str lr, [fp, #LO_saved_lr] |
843 | add r1, r1, r2 |
844 | str r1, [fp, #LO_cycle] |
845 | add r1, fp, #LO_psxRegs |
846 | bl gteCheckStallRaw |
847 | ldr lr, [fp, #LO_saved_lr] |
848 | add r10, r10, r0 |
849 | bx lr |
850 | |
7e605697 |
851 | @ vim:filetype=armasm |