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1 | diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c |
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2 | index 74f32ee3..4eec8a83 100644 |
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3 | --- a/libpcsxcore/new_dynarec/new_dynarec.c |
4 | +++ b/libpcsxcore/new_dynarec/new_dynarec.c |
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5 | @@ -325,7 +325,7 @@ static struct compile_info |
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6 | int new_dynarec_hacks_old; |
7 | int new_dynarec_did_compile; |
8 | |
9 | - #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) |
10 | + #define HACK_ENABLED(x) ((NDHACK_NO_STALLS) & (x)) |
11 | |
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12 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG) |
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13 | extern int last_count; // last absolute target, often = next_interupt |
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14 | @@ -603,6 +603,7 @@ static int cycle_multiplier_active; |
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15 | |
16 | static int CLOCK_ADJUST(int x) |
17 | { |
18 | + return x * 2; |
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19 | int m = cycle_multiplier_active; |
20 | int s = (x >> 31) | 1; |
21 | return (x * m + s * 50) / 100; |
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22 | @@ -808,6 +809,9 @@ static noinline u_int generate_exception(u_int pc) |
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23 | // This is called from the recompiled JR/JALR instructions |
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24 | static void noinline *get_addr(u_int vaddr, int can_compile) |
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25 | { |
26 | +#ifdef DRC_DBG |
27 | +printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc); |
28 | +#endif |
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29 | u_int start_page = get_page_prev(vaddr); |
30 | u_int i, page, end_page = get_page(vaddr); |
31 | void *found_clean = NULL; |
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32 | @@ -7213,7 +7217,7 @@ static noinline void pass2_unneeded_regs(int istart,int iend,int r) |
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33 | // R0 is always unneeded |
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34 | u|=1; |
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35 | // Save it |
36 | - unneeded_reg[i]=u; |
37 | + unneeded_reg[i]=1;//u; |
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38 | gte_unneeded[i]=gte_u; |
39 | /* |
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40 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); |
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41 | @@ -8355,6 +8359,7 @@ static noinline void pass5a_preallocate1(void) |
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42 | static noinline void pass5b_preallocate2(void) |
43 | { |
44 | int i, hr; |
45 | + return; |
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46 | for(i=0;i<slen-1;i++) |
47 | { |
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48 | if (!i || !dops[i-1].is_jump) |
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49 | @@ -9380,6 +9385,10 @@ static int new_recompile_block(u_int addr) |
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50 | |
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51 | #ifdef ASSEM_PRINT |
52 | fflush(stdout); |
53 | +#endif |
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54 | +#ifdef DRC_DBG |
55 | +printf("new_recompile_block done\n"); |
56 | +fflush(stdout); |
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57 | #endif |
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58 | stat_inc(stat_bc_direct); |
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59 | return 0; |
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60 | diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c |
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61 | index f4b1d90e..d3975ceb 100644 |
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62 | --- a/libpcsxcore/new_dynarec/pcsxmem.c |
63 | +++ b/libpcsxcore/new_dynarec/pcsxmem.c |
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64 | @@ -258,6 +258,8 @@ static void write_biu(u32 value) |
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65 | return; |
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66 | } |
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67 | |
68 | +extern u32 handler_cycle; |
69 | +handler_cycle = psxRegs.cycle; |
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70 | memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle); |
71 | psxRegs.biuReg = value; |
72 | } |
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73 | diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c |
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74 | index d0d45ec5..4ed03c40 100644 |
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75 | --- a/libpcsxcore/psxcounters.c |
76 | +++ b/libpcsxcore/psxcounters.c |
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77 | @@ -428,9 +428,12 @@ void psxRcntUpdate() |
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78 | |
79 | /******************************************************************************/ |
80 | |
81 | +extern u32 handler_cycle; |
82 | + |
83 | void psxRcntWcount( u32 index, u32 value ) |
84 | { |
85 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
86 | +handler_cycle = psxRegs.cycle; |
87 | |
88 | _psxRcntWcount( index, value ); |
89 | psxRcntSet(); |
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90 | @@ -439,6 +442,7 @@ void psxRcntWcount( u32 index, u32 value ) |
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91 | void psxRcntWmode( u32 index, u32 value ) |
92 | { |
93 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
94 | +handler_cycle = psxRegs.cycle; |
95 | |
96 | _psxRcntWmode( index, value ); |
97 | _psxRcntWcount( index, 0 ); |
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98 | @@ -450,6 +454,7 @@ void psxRcntWmode( u32 index, u32 value ) |
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99 | void psxRcntWtarget( u32 index, u32 value ) |
100 | { |
101 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
102 | +handler_cycle = psxRegs.cycle; |
103 | |
104 | rcnts[index].target = value; |
105 | |
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106 | @@ -463,6 +468,7 @@ u32 psxRcntRcount0() |
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107 | { |
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108 | u32 index = 0; |
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109 | u32 count; |
110 | +handler_cycle = psxRegs.cycle; |
111 | |
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112 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
113 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) |
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114 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
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115 | index f6ff2e8b..2f7147c3 100644 |
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116 | --- a/libpcsxcore/psxinterpreter.c |
117 | +++ b/libpcsxcore/psxinterpreter.c |
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118 | @@ -245,7 +245,7 @@ static inline void addCycle(psxRegisters *regs) |
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119 | { |
120 | assert(regs->subCycleStep >= 0x10000); |
121 | regs->subCycle += regs->subCycleStep; |
122 | - regs->cycle += regs->subCycle >> 16; |
123 | + regs->cycle += 2; //regs->subCycle >> 16; |
124 | regs->subCycle &= 0xffff; |
125 | } |
126 | |
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127 | @@ -1348,8 +1348,15 @@ static void intShutdown() { |
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128 | // single step (may do several ops in case of a branch or load delay) |
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129 | // called by asm/dynarec |
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130 | void execI(psxRegisters *regs) { |
131 | + extern int last_count; |
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132 | + extern u32 next_interupt; |
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133 | + void do_insn_cmp(void); |
134 | + printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, next_interupt); |
135 | + last_count = 0; |
136 | do { |
137 | execIbp(psxMemRLUT, regs); |
138 | + if (regs->dloadReg[0] || regs->dloadReg[1]) |
139 | + do_insn_cmp(); |
140 | } while (regs->dloadReg[0] || regs->dloadReg[1]); |
141 | } |
142 | |