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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
ddbaf678 | 25 | #include "gpu.h" |
fc8145b7 | 26 | #include "debug.h" |
ef79bbde P |
27 | |
28 | /******************************************************************************/ | |
29 | ||
ef79bbde P |
30 | enum |
31 | { | |
32 | Rc0Gate = 0x0001, // 0 not implemented | |
33 | Rc1Gate = 0x0001, // 0 not implemented | |
34 | Rc2Disable = 0x0001, // 0 partially implemented | |
35 | RcUnknown1 = 0x0002, // 1 ? | |
36 | RcUnknown2 = 0x0004, // 2 ? | |
37 | RcCountToTarget = 0x0008, // 3 | |
38 | RcIrqOnTarget = 0x0010, // 4 | |
39 | RcIrqOnOverflow = 0x0020, // 5 | |
40 | RcIrqRegenerate = 0x0040, // 6 | |
41 | RcUnknown7 = 0x0080, // 7 ? | |
42 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
43 | Rc1HSyncClock = 0x0100, // 8 | |
44 | Rc2Unknown8 = 0x0100, // 8 ? | |
45 | Rc0Unknown9 = 0x0200, // 9 ? | |
46 | Rc1Unknown9 = 0x0200, // 9 ? | |
47 | Rc2OneEighthClock = 0x0200, // 9 | |
48 | RcUnknown10 = 0x0400, // 10 ? | |
49 | RcCountEqTarget = 0x0800, // 11 | |
50 | RcOverflow = 0x1000, // 12 | |
51 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
52 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
53 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
54 | }; | |
55 | ||
56 | #define CounterQuantity ( 4 ) | |
57 | //static const u32 CounterQuantity = 4; | |
58 | ||
59 | static const u32 CountToOverflow = 0; | |
60 | static const u32 CountToTarget = 1; | |
61 | ||
62 | static const u32 FrameRate[] = { 60, 50 }; | |
aecf98c5 | 63 | static const u32 HSyncTotal[] = { 263, 313 }; |
554a2220 | 64 | static const u32 SpuUpdInterval[] = { 32, 32 }; |
0486fdc9 | 65 | #define VBlankStart 240 |
ef79bbde | 66 | |
9f7ee52e | 67 | #define VERBOSE_LEVEL 0 |
68 | static const s32 VerboseLevel = VERBOSE_LEVEL; | |
ef79bbde P |
69 | |
70 | /******************************************************************************/ | |
71 | ||
b1be1eee | 72 | Rcnt rcnts[ CounterQuantity ]; |
ef79bbde | 73 | |
24de2dd4 | 74 | u32 hSyncCount = 0; |
75 | u32 frame_counter = 0; | |
ef79bbde | 76 | static u32 spuSyncCount = 0; |
61ef5cf4 | 77 | static u32 hsync_steps = 0; |
4f55097d | 78 | static u32 base_cycle = 0; |
ef79bbde P |
79 | |
80 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
81 | ||
82 | /******************************************************************************/ | |
83 | ||
84 | static inline | |
85 | void setIrq( u32 irq ) | |
86 | { | |
87 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
88 | } | |
89 | ||
90 | static | |
9f7ee52e | 91 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 92 | { |
9f7ee52e | 93 | #if VERBOSE_LEVEL > 0 |
ef79bbde P |
94 | if( level <= VerboseLevel ) |
95 | { | |
96 | va_list va; | |
97 | char buf[ 4096 ]; | |
98 | ||
99 | va_start( va, str ); | |
100 | vsprintf( buf, str, va ); | |
101 | va_end( va ); | |
102 | ||
ab948f7e | 103 | printf( "%s", buf ); |
ef79bbde P |
104 | fflush( stdout ); |
105 | } | |
9f7ee52e | 106 | #endif |
ef79bbde P |
107 | } |
108 | ||
109 | /******************************************************************************/ | |
110 | ||
111 | static inline | |
112 | void _psxRcntWcount( u32 index, u32 value ) | |
113 | { | |
114 | if( value > 0xffff ) | |
115 | { | |
116 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
117 | value &= 0xffff; | |
118 | } | |
119 | ||
120 | rcnts[index].cycleStart = psxRegs.cycle; | |
121 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
122 | ||
123 | // TODO: <=. | |
124 | if( value < rcnts[index].target ) | |
125 | { | |
126 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
127 | rcnts[index].counterState = CountToTarget; | |
128 | } | |
129 | else | |
130 | { | |
8ca6b0a6 | 131 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
132 | rcnts[index].counterState = CountToOverflow; |
133 | } | |
134 | } | |
135 | ||
136 | static inline | |
137 | u32 _psxRcntRcount( u32 index ) | |
138 | { | |
139 | u32 count; | |
140 | ||
141 | count = psxRegs.cycle; | |
142 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 143 | if (rcnts[index].rate > 1) |
144 | count /= rcnts[index].rate; | |
ef79bbde | 145 | |
8ca6b0a6 | 146 | if( count > 0x10000 ) |
ef79bbde | 147 | { |
8ca6b0a6 | 148 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 149 | } |
8ca6b0a6 | 150 | count &= 0xffff; |
ef79bbde P |
151 | |
152 | return count; | |
153 | } | |
154 | ||
155 | /******************************************************************************/ | |
156 | ||
157 | static | |
158 | void psxRcntSet() | |
159 | { | |
160 | s32 countToUpdate; | |
161 | u32 i; | |
162 | ||
163 | psxNextsCounter = psxRegs.cycle; | |
164 | psxNextCounter = 0x7fffffff; | |
165 | ||
166 | for( i = 0; i < CounterQuantity; ++i ) | |
167 | { | |
168 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
169 | ||
170 | if( countToUpdate < 0 ) | |
171 | { | |
172 | psxNextCounter = 0; | |
173 | break; | |
174 | } | |
175 | ||
176 | if( countToUpdate < (s32)psxNextCounter ) | |
177 | { | |
178 | psxNextCounter = countToUpdate; | |
179 | } | |
180 | } | |
5b8c000f | 181 | |
182 | psxRegs.interrupt |= (1 << PSXINT_RCNT); | |
183 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); | |
ef79bbde P |
184 | } |
185 | ||
186 | /******************************************************************************/ | |
187 | ||
188 | static | |
189 | void psxRcntReset( u32 index ) | |
190 | { | |
8ca6b0a6 | 191 | u32 rcycles; |
ef79bbde | 192 | |
53c361f0 | 193 | rcnts[index].mode |= RcUnknown10; |
194 | ||
ef79bbde P |
195 | if( rcnts[index].counterState == CountToTarget ) |
196 | { | |
8ca6b0a6 | 197 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 198 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 199 | { |
200 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
201 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
202 | } | |
203 | else | |
204 | { | |
205 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
206 | rcnts[index].counterState = CountToOverflow; | |
207 | } | |
ef79bbde P |
208 | |
209 | if( rcnts[index].mode & RcIrqOnTarget ) | |
210 | { | |
211 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
212 | { | |
8ca6b0a6 | 213 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
214 | setIrq( rcnts[index].irq ); |
215 | rcnts[index].irqState = 1; | |
216 | } | |
217 | } | |
218 | ||
219 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 220 | |
8ca6b0a6 | 221 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 222 | return; |
ef79bbde | 223 | } |
53c361f0 | 224 | |
225 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 226 | { |
8ca6b0a6 | 227 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
228 | rcycles -= 0x10000 * rcnts[index].rate; | |
229 | ||
230 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 231 | |
8ca6b0a6 | 232 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
233 | { | |
234 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
235 | rcnts[index].counterState = CountToTarget; | |
236 | } | |
ef79bbde P |
237 | |
238 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
239 | { | |
240 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
241 | { | |
8ca6b0a6 | 242 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
243 | setIrq( rcnts[index].irq ); |
244 | rcnts[index].irqState = 1; | |
245 | } | |
246 | } | |
247 | ||
248 | rcnts[index].mode |= RcOverflow; | |
249 | } | |
ef79bbde P |
250 | } |
251 | ||
252 | void psxRcntUpdate() | |
253 | { | |
254 | u32 cycle; | |
255 | ||
256 | cycle = psxRegs.cycle; | |
257 | ||
258 | // rcnt 0. | |
259 | if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) | |
260 | { | |
261 | psxRcntReset( 0 ); | |
262 | } | |
263 | ||
264 | // rcnt 1. | |
265 | if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) | |
266 | { | |
267 | psxRcntReset( 1 ); | |
268 | } | |
269 | ||
270 | // rcnt 2. | |
271 | if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) | |
272 | { | |
273 | psxRcntReset( 2 ); | |
274 | } | |
275 | ||
276 | // rcnt base. | |
277 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
278 | { | |
61ef5cf4 | 279 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
280 | u32 next_vsync, next_lace; | |
ef79bbde | 281 | |
61ef5cf4 | 282 | spuSyncCount += hsync_steps; |
283 | hSyncCount += hsync_steps; | |
ef79bbde P |
284 | |
285 | // Update spu. | |
286 | if( spuSyncCount >= SpuUpdInterval[Config.PsxType] ) | |
287 | { | |
288 | spuSyncCount = 0; | |
289 | ||
290 | if( SPU_async ) | |
291 | { | |
292 | SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target ); | |
293 | } | |
294 | } | |
295 | ||
296 | // VSync irq. | |
0486fdc9 | 297 | if( hSyncCount == VBlankStart ) |
ef79bbde | 298 | { |
0486fdc9 | 299 | HW_GPU_STATUS &= ~PSXGPU_LCF; |
72e5023f | 300 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 301 | setIrq( 0x01 ); |
302 | ||
303 | EmuUpdate(); | |
304 | GPU_updateLace(); | |
ef79bbde P |
305 | } |
306 | ||
307 | // Update lace. (with InuYasha fix) | |
308 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) | |
309 | { | |
310 | hSyncCount = 0; | |
ddbaf678 | 311 | frame_counter++; |
ef79bbde | 312 | |
0486fdc9 | 313 | gpuSyncPluginSR(); |
314 | if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS ) | |
ddbaf678 | 315 | HW_GPU_STATUS |= frame_counter << 31; |
72e5023f | 316 | GPU_vBlank( 0, HW_GPU_STATUS >> 31 ); |
ef79bbde | 317 | } |
61ef5cf4 | 318 | |
319 | // Schedule next call, in hsyncs | |
320 | hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount; | |
0486fdc9 | 321 | next_vsync = VBlankStart - hSyncCount; // ok to overflow |
61ef5cf4 | 322 | next_lace = HSyncTotal[Config.PsxType] - hSyncCount; |
323 | if( next_vsync && next_vsync < hsync_steps ) | |
324 | hsync_steps = next_vsync; | |
325 | if( next_lace && next_lace < hsync_steps ) | |
326 | hsync_steps = next_lace; | |
61ef5cf4 | 327 | |
328 | rcnts[3].cycleStart = cycle - leftover_cycles; | |
4f55097d | 329 | if (Config.PsxType) |
330 | // 20.12 precision, clk / 50 / 313 ~= 2164.14 | |
331 | base_cycle += hsync_steps * 8864320; | |
332 | else | |
333 | // clk / 60 / 263 ~= 2146.31 | |
334 | base_cycle += hsync_steps * 8791293; | |
335 | rcnts[3].cycle = base_cycle >> 12; | |
336 | base_cycle &= 0xfff; | |
ef79bbde P |
337 | } |
338 | ||
95df1a04 | 339 | psxRcntSet(); |
340 | ||
61ef5cf4 | 341 | #ifndef NDEBUG |
ef79bbde | 342 | DebugVSync(); |
61ef5cf4 | 343 | #endif |
ef79bbde P |
344 | } |
345 | ||
346 | /******************************************************************************/ | |
347 | ||
348 | void psxRcntWcount( u32 index, u32 value ) | |
349 | { | |
350 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
351 | ||
ef79bbde P |
352 | _psxRcntWcount( index, value ); |
353 | psxRcntSet(); | |
354 | } | |
355 | ||
356 | void psxRcntWmode( u32 index, u32 value ) | |
357 | { | |
358 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
359 | ||
ef79bbde P |
360 | rcnts[index].mode = value; |
361 | rcnts[index].irqState = 0; | |
362 | ||
363 | switch( index ) | |
364 | { | |
365 | case 0: | |
366 | if( value & Rc0PixelClock ) | |
367 | { | |
368 | rcnts[index].rate = 5; | |
369 | } | |
370 | else | |
371 | { | |
372 | rcnts[index].rate = 1; | |
373 | } | |
374 | break; | |
375 | case 1: | |
376 | if( value & Rc1HSyncClock ) | |
377 | { | |
378 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
379 | } | |
380 | else | |
381 | { | |
382 | rcnts[index].rate = 1; | |
383 | } | |
384 | break; | |
385 | case 2: | |
386 | if( value & Rc2OneEighthClock ) | |
387 | { | |
388 | rcnts[index].rate = 8; | |
389 | } | |
390 | else | |
391 | { | |
392 | rcnts[index].rate = 1; | |
393 | } | |
394 | ||
395 | // TODO: wcount must work. | |
396 | if( value & Rc2Disable ) | |
397 | { | |
398 | rcnts[index].rate = 0xffffffff; | |
399 | } | |
400 | break; | |
401 | } | |
402 | ||
403 | _psxRcntWcount( index, 0 ); | |
404 | psxRcntSet(); | |
405 | } | |
406 | ||
407 | void psxRcntWtarget( u32 index, u32 value ) | |
408 | { | |
409 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
410 | ||
ef79bbde P |
411 | rcnts[index].target = value; |
412 | ||
413 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
414 | psxRcntSet(); | |
415 | } | |
416 | ||
417 | /******************************************************************************/ | |
418 | ||
419 | u32 psxRcntRcount( u32 index ) | |
420 | { | |
421 | u32 count; | |
422 | ||
ef79bbde P |
423 | count = _psxRcntRcount( index ); |
424 | ||
425 | // Parasite Eve 2 fix. | |
426 | if( Config.RCntFix ) | |
427 | { | |
428 | if( index == 2 ) | |
429 | { | |
430 | if( rcnts[index].counterState == CountToTarget ) | |
431 | { | |
432 | count /= BIAS; | |
433 | } | |
434 | } | |
435 | } | |
436 | ||
437 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); | |
438 | ||
439 | return count; | |
440 | } | |
441 | ||
442 | u32 psxRcntRmode( u32 index ) | |
443 | { | |
444 | u16 mode; | |
445 | ||
ef79bbde P |
446 | mode = rcnts[index].mode; |
447 | rcnts[index].mode &= 0xe7ff; | |
448 | ||
449 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
450 | ||
451 | return mode; | |
452 | } | |
453 | ||
454 | u32 psxRcntRtarget( u32 index ) | |
455 | { | |
456 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
457 | ||
458 | return rcnts[index].target; | |
459 | } | |
460 | ||
461 | /******************************************************************************/ | |
462 | ||
463 | void psxRcntInit() | |
464 | { | |
465 | s32 i; | |
466 | ||
467 | // rcnt 0. | |
468 | rcnts[0].rate = 1; | |
469 | rcnts[0].irq = 0x10; | |
470 | ||
471 | // rcnt 1. | |
472 | rcnts[1].rate = 1; | |
473 | rcnts[1].irq = 0x20; | |
474 | ||
475 | // rcnt 2. | |
476 | rcnts[2].rate = 1; | |
477 | rcnts[2].irq = 0x40; | |
478 | ||
479 | // rcnt base. | |
480 | rcnts[3].rate = 1; | |
481 | rcnts[3].mode = RcCountToTarget; | |
482 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
483 | ||
484 | for( i = 0; i < CounterQuantity; ++i ) | |
485 | { | |
486 | _psxRcntWcount( i, 0 ); | |
487 | } | |
488 | ||
c62b43c9 | 489 | hSyncCount = 0; |
490 | spuSyncCount = 0; | |
61ef5cf4 | 491 | hsync_steps = 1; |
c62b43c9 | 492 | |
ef79bbde P |
493 | psxRcntSet(); |
494 | } | |
495 | ||
496 | /******************************************************************************/ | |
497 | ||
498 | s32 psxRcntFreeze( gzFile f, s32 Mode ) | |
499 | { | |
500 | gzfreeze( &rcnts, sizeof(rcnts) ); | |
501 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); | |
502 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
503 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
504 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
505 | ||
61ef5cf4 | 506 | if (Mode == 0) |
507 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; | |
508 | ||
4f55097d | 509 | base_cycle = 0; |
510 | ||
ef79bbde P |
511 | return 0; |
512 | } | |
513 | ||
514 | /******************************************************************************/ |