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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
fc8145b7 | 25 | #include "debug.h" |
ef79bbde P |
26 | |
27 | /******************************************************************************/ | |
28 | ||
29 | typedef struct Rcnt | |
30 | { | |
31 | u16 mode, target; | |
32 | u32 rate, irq, counterState, irqState; | |
33 | u32 cycle, cycleStart; | |
34 | } Rcnt; | |
35 | ||
36 | enum | |
37 | { | |
38 | Rc0Gate = 0x0001, // 0 not implemented | |
39 | Rc1Gate = 0x0001, // 0 not implemented | |
40 | Rc2Disable = 0x0001, // 0 partially implemented | |
41 | RcUnknown1 = 0x0002, // 1 ? | |
42 | RcUnknown2 = 0x0004, // 2 ? | |
43 | RcCountToTarget = 0x0008, // 3 | |
44 | RcIrqOnTarget = 0x0010, // 4 | |
45 | RcIrqOnOverflow = 0x0020, // 5 | |
46 | RcIrqRegenerate = 0x0040, // 6 | |
47 | RcUnknown7 = 0x0080, // 7 ? | |
48 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
49 | Rc1HSyncClock = 0x0100, // 8 | |
50 | Rc2Unknown8 = 0x0100, // 8 ? | |
51 | Rc0Unknown9 = 0x0200, // 9 ? | |
52 | Rc1Unknown9 = 0x0200, // 9 ? | |
53 | Rc2OneEighthClock = 0x0200, // 9 | |
54 | RcUnknown10 = 0x0400, // 10 ? | |
55 | RcCountEqTarget = 0x0800, // 11 | |
56 | RcOverflow = 0x1000, // 12 | |
57 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
58 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
59 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
60 | }; | |
61 | ||
62 | #define CounterQuantity ( 4 ) | |
63 | //static const u32 CounterQuantity = 4; | |
64 | ||
65 | static const u32 CountToOverflow = 0; | |
66 | static const u32 CountToTarget = 1; | |
67 | ||
68 | static const u32 FrameRate[] = { 60, 50 }; | |
69 | static const u32 VBlankStart[] = { 240, 256 }; | |
aecf98c5 | 70 | static const u32 HSyncTotal[] = { 263, 313 }; |
554a2220 | 71 | static const u32 SpuUpdInterval[] = { 32, 32 }; |
ef79bbde | 72 | |
9f7ee52e | 73 | #define VERBOSE_LEVEL 0 |
74 | static const s32 VerboseLevel = VERBOSE_LEVEL; | |
ef79bbde P |
75 | |
76 | /******************************************************************************/ | |
77 | ||
78 | static Rcnt rcnts[ CounterQuantity ]; | |
79 | ||
80 | static u32 hSyncCount = 0; | |
81 | static u32 spuSyncCount = 0; | |
61ef5cf4 | 82 | static u32 hsync_steps = 0; |
83 | static u32 gpu_wants_hcnt = 0; | |
ef79bbde P |
84 | |
85 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
86 | ||
87 | /******************************************************************************/ | |
88 | ||
89 | static inline | |
90 | void setIrq( u32 irq ) | |
91 | { | |
92 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
93 | } | |
94 | ||
95 | static | |
9f7ee52e | 96 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 97 | { |
9f7ee52e | 98 | #if VERBOSE_LEVEL > 0 |
ef79bbde P |
99 | if( level <= VerboseLevel ) |
100 | { | |
101 | va_list va; | |
102 | char buf[ 4096 ]; | |
103 | ||
104 | va_start( va, str ); | |
105 | vsprintf( buf, str, va ); | |
106 | va_end( va ); | |
107 | ||
ab948f7e | 108 | printf( "%s", buf ); |
ef79bbde P |
109 | fflush( stdout ); |
110 | } | |
9f7ee52e | 111 | #endif |
ef79bbde P |
112 | } |
113 | ||
114 | /******************************************************************************/ | |
115 | ||
116 | static inline | |
117 | void _psxRcntWcount( u32 index, u32 value ) | |
118 | { | |
119 | if( value > 0xffff ) | |
120 | { | |
121 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
122 | value &= 0xffff; | |
123 | } | |
124 | ||
125 | rcnts[index].cycleStart = psxRegs.cycle; | |
126 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
127 | ||
128 | // TODO: <=. | |
129 | if( value < rcnts[index].target ) | |
130 | { | |
131 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
132 | rcnts[index].counterState = CountToTarget; | |
133 | } | |
134 | else | |
135 | { | |
136 | rcnts[index].cycle = 0xffff * rcnts[index].rate; | |
137 | rcnts[index].counterState = CountToOverflow; | |
138 | } | |
139 | } | |
140 | ||
141 | static inline | |
142 | u32 _psxRcntRcount( u32 index ) | |
143 | { | |
144 | u32 count; | |
145 | ||
146 | count = psxRegs.cycle; | |
147 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 148 | if (rcnts[index].rate > 1) |
149 | count /= rcnts[index].rate; | |
ef79bbde P |
150 | |
151 | if( count > 0xffff ) | |
152 | { | |
153 | verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count ); | |
154 | count &= 0xffff; | |
155 | } | |
156 | ||
157 | return count; | |
158 | } | |
159 | ||
160 | /******************************************************************************/ | |
161 | ||
162 | static | |
163 | void psxRcntSet() | |
164 | { | |
165 | s32 countToUpdate; | |
166 | u32 i; | |
167 | ||
168 | psxNextsCounter = psxRegs.cycle; | |
169 | psxNextCounter = 0x7fffffff; | |
170 | ||
171 | for( i = 0; i < CounterQuantity; ++i ) | |
172 | { | |
173 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
174 | ||
175 | if( countToUpdate < 0 ) | |
176 | { | |
177 | psxNextCounter = 0; | |
178 | break; | |
179 | } | |
180 | ||
181 | if( countToUpdate < (s32)psxNextCounter ) | |
182 | { | |
183 | psxNextCounter = countToUpdate; | |
184 | } | |
185 | } | |
186 | } | |
187 | ||
188 | /******************************************************************************/ | |
189 | ||
190 | static | |
191 | void psxRcntReset( u32 index ) | |
192 | { | |
193 | u32 count; | |
194 | ||
195 | if( rcnts[index].counterState == CountToTarget ) | |
196 | { | |
197 | if( rcnts[index].mode & RcCountToTarget ) | |
198 | { | |
199 | count = psxRegs.cycle; | |
200 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 201 | if (rcnts[index].rate > 1) |
202 | count /= rcnts[index].rate; | |
ef79bbde P |
203 | count -= rcnts[index].target; |
204 | } | |
205 | else | |
206 | { | |
207 | count = _psxRcntRcount( index ); | |
208 | } | |
209 | ||
210 | _psxRcntWcount( index, count ); | |
211 | ||
212 | if( rcnts[index].mode & RcIrqOnTarget ) | |
213 | { | |
214 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
215 | { | |
216 | verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); | |
217 | setIrq( rcnts[index].irq ); | |
218 | rcnts[index].irqState = 1; | |
219 | } | |
220 | } | |
221 | ||
222 | rcnts[index].mode |= RcCountEqTarget; | |
223 | } | |
224 | else if( rcnts[index].counterState == CountToOverflow ) | |
225 | { | |
226 | count = psxRegs.cycle; | |
227 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 228 | if (rcnts[index].rate > 1) |
229 | count /= rcnts[index].rate; | |
ef79bbde P |
230 | count -= 0xffff; |
231 | ||
232 | _psxRcntWcount( index, count ); | |
233 | ||
234 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
235 | { | |
236 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
237 | { | |
238 | verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); | |
239 | setIrq( rcnts[index].irq ); | |
240 | rcnts[index].irqState = 1; | |
241 | } | |
242 | } | |
243 | ||
244 | rcnts[index].mode |= RcOverflow; | |
245 | } | |
246 | ||
247 | rcnts[index].mode |= RcUnknown10; | |
248 | ||
249 | psxRcntSet(); | |
250 | } | |
251 | ||
252 | void psxRcntUpdate() | |
253 | { | |
254 | u32 cycle; | |
255 | ||
256 | cycle = psxRegs.cycle; | |
257 | ||
258 | // rcnt 0. | |
259 | if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) | |
260 | { | |
261 | psxRcntReset( 0 ); | |
262 | } | |
263 | ||
264 | // rcnt 1. | |
265 | if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) | |
266 | { | |
267 | psxRcntReset( 1 ); | |
268 | } | |
269 | ||
270 | // rcnt 2. | |
271 | if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) | |
272 | { | |
273 | psxRcntReset( 2 ); | |
274 | } | |
275 | ||
276 | // rcnt base. | |
277 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
278 | { | |
61ef5cf4 | 279 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
280 | u32 next_vsync, next_lace; | |
ef79bbde | 281 | |
61ef5cf4 | 282 | spuSyncCount += hsync_steps; |
283 | hSyncCount += hsync_steps; | |
ef79bbde P |
284 | |
285 | // Update spu. | |
286 | if( spuSyncCount >= SpuUpdInterval[Config.PsxType] ) | |
287 | { | |
288 | spuSyncCount = 0; | |
289 | ||
290 | if( SPU_async ) | |
291 | { | |
292 | SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target ); | |
293 | } | |
294 | } | |
295 | ||
296 | // VSync irq. | |
297 | if( hSyncCount == VBlankStart[Config.PsxType] ) | |
298 | { | |
61ef5cf4 | 299 | GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt ); |
ef79bbde P |
300 | |
301 | // For the best times. :D | |
302 | //setIrq( 0x01 ); | |
303 | } | |
304 | ||
305 | // Update lace. (with InuYasha fix) | |
306 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) | |
307 | { | |
308 | hSyncCount = 0; | |
309 | ||
61ef5cf4 | 310 | GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt ); |
ef79bbde P |
311 | setIrq( 0x01 ); |
312 | ||
ef79bbde | 313 | EmuUpdate(); |
cefe86b7 | 314 | GPU_updateLace(); |
ef79bbde | 315 | } |
61ef5cf4 | 316 | |
317 | // Schedule next call, in hsyncs | |
318 | hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount; | |
319 | next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow | |
320 | next_lace = HSyncTotal[Config.PsxType] - hSyncCount; | |
321 | if( next_vsync && next_vsync < hsync_steps ) | |
322 | hsync_steps = next_vsync; | |
323 | if( next_lace && next_lace < hsync_steps ) | |
324 | hsync_steps = next_lace; | |
325 | if( gpu_wants_hcnt ) | |
326 | hsync_steps = 1; | |
327 | ||
328 | rcnts[3].cycleStart = cycle - leftover_cycles; | |
329 | rcnts[3].cycle = hsync_steps * rcnts[3].target; | |
330 | psxRcntSet(); | |
ef79bbde P |
331 | } |
332 | ||
61ef5cf4 | 333 | #ifndef NDEBUG |
ef79bbde | 334 | DebugVSync(); |
61ef5cf4 | 335 | #endif |
ef79bbde P |
336 | } |
337 | ||
338 | /******************************************************************************/ | |
339 | ||
340 | void psxRcntWcount( u32 index, u32 value ) | |
341 | { | |
342 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
343 | ||
ef79bbde P |
344 | _psxRcntWcount( index, value ); |
345 | psxRcntSet(); | |
346 | } | |
347 | ||
348 | void psxRcntWmode( u32 index, u32 value ) | |
349 | { | |
350 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
351 | ||
ef79bbde P |
352 | rcnts[index].mode = value; |
353 | rcnts[index].irqState = 0; | |
354 | ||
355 | switch( index ) | |
356 | { | |
357 | case 0: | |
358 | if( value & Rc0PixelClock ) | |
359 | { | |
360 | rcnts[index].rate = 5; | |
361 | } | |
362 | else | |
363 | { | |
364 | rcnts[index].rate = 1; | |
365 | } | |
366 | break; | |
367 | case 1: | |
368 | if( value & Rc1HSyncClock ) | |
369 | { | |
370 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
371 | } | |
372 | else | |
373 | { | |
374 | rcnts[index].rate = 1; | |
375 | } | |
376 | break; | |
377 | case 2: | |
378 | if( value & Rc2OneEighthClock ) | |
379 | { | |
380 | rcnts[index].rate = 8; | |
381 | } | |
382 | else | |
383 | { | |
384 | rcnts[index].rate = 1; | |
385 | } | |
386 | ||
387 | // TODO: wcount must work. | |
388 | if( value & Rc2Disable ) | |
389 | { | |
390 | rcnts[index].rate = 0xffffffff; | |
391 | } | |
392 | break; | |
393 | } | |
394 | ||
395 | _psxRcntWcount( index, 0 ); | |
396 | psxRcntSet(); | |
397 | } | |
398 | ||
399 | void psxRcntWtarget( u32 index, u32 value ) | |
400 | { | |
401 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
402 | ||
ef79bbde P |
403 | rcnts[index].target = value; |
404 | ||
405 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
406 | psxRcntSet(); | |
407 | } | |
408 | ||
409 | /******************************************************************************/ | |
410 | ||
411 | u32 psxRcntRcount( u32 index ) | |
412 | { | |
413 | u32 count; | |
414 | ||
ef79bbde P |
415 | count = _psxRcntRcount( index ); |
416 | ||
417 | // Parasite Eve 2 fix. | |
418 | if( Config.RCntFix ) | |
419 | { | |
420 | if( index == 2 ) | |
421 | { | |
422 | if( rcnts[index].counterState == CountToTarget ) | |
423 | { | |
424 | count /= BIAS; | |
425 | } | |
426 | } | |
427 | } | |
428 | ||
429 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); | |
430 | ||
431 | return count; | |
432 | } | |
433 | ||
434 | u32 psxRcntRmode( u32 index ) | |
435 | { | |
436 | u16 mode; | |
437 | ||
ef79bbde P |
438 | mode = rcnts[index].mode; |
439 | rcnts[index].mode &= 0xe7ff; | |
440 | ||
441 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
442 | ||
443 | return mode; | |
444 | } | |
445 | ||
446 | u32 psxRcntRtarget( u32 index ) | |
447 | { | |
448 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
449 | ||
450 | return rcnts[index].target; | |
451 | } | |
452 | ||
453 | /******************************************************************************/ | |
454 | ||
455 | void psxRcntInit() | |
456 | { | |
457 | s32 i; | |
458 | ||
459 | // rcnt 0. | |
460 | rcnts[0].rate = 1; | |
461 | rcnts[0].irq = 0x10; | |
462 | ||
463 | // rcnt 1. | |
464 | rcnts[1].rate = 1; | |
465 | rcnts[1].irq = 0x20; | |
466 | ||
467 | // rcnt 2. | |
468 | rcnts[2].rate = 1; | |
469 | rcnts[2].irq = 0x40; | |
470 | ||
471 | // rcnt base. | |
472 | rcnts[3].rate = 1; | |
473 | rcnts[3].mode = RcCountToTarget; | |
474 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
475 | ||
476 | for( i = 0; i < CounterQuantity; ++i ) | |
477 | { | |
478 | _psxRcntWcount( i, 0 ); | |
479 | } | |
480 | ||
c62b43c9 | 481 | hSyncCount = 0; |
482 | spuSyncCount = 0; | |
61ef5cf4 | 483 | hsync_steps = 1; |
c62b43c9 | 484 | |
ef79bbde P |
485 | psxRcntSet(); |
486 | } | |
487 | ||
488 | /******************************************************************************/ | |
489 | ||
490 | s32 psxRcntFreeze( gzFile f, s32 Mode ) | |
491 | { | |
492 | gzfreeze( &rcnts, sizeof(rcnts) ); | |
493 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); | |
494 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
495 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
496 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
497 | ||
61ef5cf4 | 498 | if (Mode == 0) |
499 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; | |
500 | ||
ef79bbde P |
501 | return 0; |
502 | } | |
503 | ||
504 | /******************************************************************************/ |