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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
c6a249e3 | 25 | #include "psxevents.h" |
ddbaf678 | 26 | #include "gpu.h" |
5b568098 | 27 | //#include "debug.h" |
28 | #define DebugVSync() | |
ef79bbde P |
29 | |
30 | /******************************************************************************/ | |
31 | ||
ef79bbde P |
32 | enum |
33 | { | |
d3d41455 | 34 | RcSyncModeEnable = 0x0001, // 0 |
35 | Rc01BlankPause = 0 << 1, // 1,2 | |
36 | Rc01UnblankReset = 1 << 1, // 1,2 | |
37 | Rc01UnblankReset2 = 2 << 1, // 1,2 | |
38 | Rc2Stop = 0 << 1, // 1,2 | |
39 | Rc2Stop2 = 3 << 1, // 1,2 | |
ef79bbde P |
40 | RcCountToTarget = 0x0008, // 3 |
41 | RcIrqOnTarget = 0x0010, // 4 | |
42 | RcIrqOnOverflow = 0x0020, // 5 | |
43 | RcIrqRegenerate = 0x0040, // 6 | |
44 | RcUnknown7 = 0x0080, // 7 ? | |
45 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
46 | Rc1HSyncClock = 0x0100, // 8 | |
47 | Rc2Unknown8 = 0x0100, // 8 ? | |
48 | Rc0Unknown9 = 0x0200, // 9 ? | |
49 | Rc1Unknown9 = 0x0200, // 9 ? | |
50 | Rc2OneEighthClock = 0x0200, // 9 | |
51 | RcUnknown10 = 0x0400, // 10 ? | |
52 | RcCountEqTarget = 0x0800, // 11 | |
53 | RcOverflow = 0x1000, // 12 | |
54 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
55 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
56 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
57 | }; | |
58 | ||
59 | #define CounterQuantity ( 4 ) | |
60 | //static const u32 CounterQuantity = 4; | |
61 | ||
62 | static const u32 CountToOverflow = 0; | |
63 | static const u32 CountToTarget = 1; | |
64 | ||
d6b2a130 | 65 | static const u32 HSyncTotal[] = { 263, 314 }; |
66 | #define VBlankStart 240 // todo: depend on the actual GPU setting | |
ef79bbde | 67 | |
9f7ee52e | 68 | #define VERBOSE_LEVEL 0 |
ef79bbde P |
69 | |
70 | /******************************************************************************/ | |
630b122b | 71 | #ifdef DRC_DISABLE |
93c9e42a | 72 | Rcnt rcnts[ CounterQuantity ]; |
1a32b0f8 | 73 | #endif |
24de2dd4 | 74 | u32 hSyncCount = 0; |
75 | u32 frame_counter = 0; | |
61ef5cf4 | 76 | static u32 hsync_steps = 0; |
ef79bbde P |
77 | |
78 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
79 | ||
80 | /******************************************************************************/ | |
81 | ||
d6b2a130 | 82 | static inline |
83 | u32 lineCycles(void) | |
84 | { | |
85 | if (Config.PsxType) | |
86 | return PSXCLK / 50 / HSyncTotal[1]; | |
87 | else | |
88 | return PSXCLK / 60 / HSyncTotal[0]; | |
89 | } | |
90 | ||
ef79bbde P |
91 | static inline |
92 | void setIrq( u32 irq ) | |
93 | { | |
94 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
95 | } | |
96 | ||
97 | static | |
9f7ee52e | 98 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 99 | { |
9f7ee52e | 100 | #if VERBOSE_LEVEL > 0 |
630b122b | 101 | if( level <= VERBOSE_LEVEL ) |
ef79bbde P |
102 | { |
103 | va_list va; | |
104 | char buf[ 4096 ]; | |
105 | ||
106 | va_start( va, str ); | |
107 | vsprintf( buf, str, va ); | |
108 | va_end( va ); | |
109 | ||
ab948f7e | 110 | printf( "%s", buf ); |
ef79bbde P |
111 | fflush( stdout ); |
112 | } | |
9f7ee52e | 113 | #endif |
ef79bbde P |
114 | } |
115 | ||
116 | /******************************************************************************/ | |
117 | ||
118 | static inline | |
119 | void _psxRcntWcount( u32 index, u32 value ) | |
120 | { | |
bb0379b7 | 121 | value &= 0xffff; |
ef79bbde P |
122 | |
123 | rcnts[index].cycleStart = psxRegs.cycle; | |
124 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
125 | ||
126 | // TODO: <=. | |
127 | if( value < rcnts[index].target ) | |
128 | { | |
129 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
130 | rcnts[index].counterState = CountToTarget; | |
131 | } | |
132 | else | |
133 | { | |
8ca6b0a6 | 134 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
135 | rcnts[index].counterState = CountToOverflow; |
136 | } | |
137 | } | |
138 | ||
139 | static inline | |
140 | u32 _psxRcntRcount( u32 index ) | |
141 | { | |
142 | u32 count; | |
143 | ||
144 | count = psxRegs.cycle; | |
145 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 146 | if (rcnts[index].rate > 1) |
147 | count /= rcnts[index].rate; | |
ef79bbde | 148 | |
8ca6b0a6 | 149 | if( count > 0x10000 ) |
ef79bbde | 150 | { |
8ca6b0a6 | 151 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 152 | } |
8ca6b0a6 | 153 | count &= 0xffff; |
ef79bbde P |
154 | |
155 | return count; | |
156 | } | |
157 | ||
a29f182f | 158 | static |
159 | void _psxRcntWmode( u32 index, u32 value ) | |
160 | { | |
161 | rcnts[index].mode = value; | |
162 | ||
163 | switch( index ) | |
164 | { | |
165 | case 0: | |
166 | if( value & Rc0PixelClock ) | |
167 | { | |
168 | rcnts[index].rate = 5; | |
169 | } | |
170 | else | |
171 | { | |
172 | rcnts[index].rate = 1; | |
173 | } | |
174 | break; | |
175 | case 1: | |
176 | if( value & Rc1HSyncClock ) | |
177 | { | |
d6b2a130 | 178 | rcnts[index].rate = lineCycles(); |
a29f182f | 179 | } |
180 | else | |
181 | { | |
182 | rcnts[index].rate = 1; | |
183 | } | |
184 | break; | |
185 | case 2: | |
186 | if( value & Rc2OneEighthClock ) | |
187 | { | |
188 | rcnts[index].rate = 8; | |
189 | } | |
190 | else | |
191 | { | |
192 | rcnts[index].rate = 1; | |
193 | } | |
194 | ||
195 | // TODO: wcount must work. | |
d3d41455 | 196 | if( (value & 7) == (RcSyncModeEnable | Rc2Stop) || |
197 | (value & 7) == (RcSyncModeEnable | Rc2Stop2) ) | |
a29f182f | 198 | { |
199 | rcnts[index].rate = 0xffffffff; | |
200 | } | |
201 | break; | |
202 | } | |
203 | } | |
204 | ||
ef79bbde P |
205 | /******************************************************************************/ |
206 | ||
207 | static | |
208 | void psxRcntSet() | |
209 | { | |
210 | s32 countToUpdate; | |
211 | u32 i; | |
212 | ||
213 | psxNextsCounter = psxRegs.cycle; | |
214 | psxNextCounter = 0x7fffffff; | |
215 | ||
216 | for( i = 0; i < CounterQuantity; ++i ) | |
217 | { | |
218 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
219 | ||
220 | if( countToUpdate < 0 ) | |
221 | { | |
222 | psxNextCounter = 0; | |
223 | break; | |
224 | } | |
225 | ||
226 | if( countToUpdate < (s32)psxNextCounter ) | |
227 | { | |
228 | psxNextCounter = countToUpdate; | |
229 | } | |
230 | } | |
5b8c000f | 231 | |
c6a249e3 | 232 | set_event(PSXINT_RCNT, psxNextCounter); |
ef79bbde P |
233 | } |
234 | ||
235 | /******************************************************************************/ | |
236 | ||
237 | static | |
238 | void psxRcntReset( u32 index ) | |
239 | { | |
8ca6b0a6 | 240 | u32 rcycles; |
ef79bbde | 241 | |
53c361f0 | 242 | rcnts[index].mode |= RcUnknown10; |
243 | ||
ef79bbde P |
244 | if( rcnts[index].counterState == CountToTarget ) |
245 | { | |
8ca6b0a6 | 246 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 247 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 248 | { |
249 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
250 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
251 | } | |
252 | else | |
253 | { | |
254 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
255 | rcnts[index].counterState = CountToOverflow; | |
256 | } | |
ef79bbde P |
257 | |
258 | if( rcnts[index].mode & RcIrqOnTarget ) | |
259 | { | |
260 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
261 | { | |
8ca6b0a6 | 262 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
263 | setIrq( rcnts[index].irq ); |
264 | rcnts[index].irqState = 1; | |
265 | } | |
266 | } | |
267 | ||
268 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 269 | |
8ca6b0a6 | 270 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 271 | return; |
ef79bbde | 272 | } |
53c361f0 | 273 | |
274 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 275 | { |
8ca6b0a6 | 276 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
277 | rcycles -= 0x10000 * rcnts[index].rate; | |
278 | ||
279 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 280 | |
8ca6b0a6 | 281 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
282 | { | |
283 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
284 | rcnts[index].counterState = CountToTarget; | |
285 | } | |
ef79bbde P |
286 | |
287 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
288 | { | |
289 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
290 | { | |
8ca6b0a6 | 291 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
292 | setIrq( rcnts[index].irq ); |
293 | rcnts[index].irqState = 1; | |
294 | } | |
295 | } | |
296 | ||
297 | rcnts[index].mode |= RcOverflow; | |
298 | } | |
ef79bbde P |
299 | } |
300 | ||
43614ebd | 301 | static void scheduleRcntBase(void) |
302 | { | |
303 | // Schedule next call, in hsyncs | |
304 | if (hSyncCount < VBlankStart) | |
305 | hsync_steps = VBlankStart - hSyncCount; | |
306 | else | |
307 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; | |
308 | ||
309 | if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType]) | |
310 | { | |
311 | rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; | |
312 | } | |
313 | else | |
314 | { | |
315 | // clk / 50 / 314 ~= 2157.25 | |
316 | // clk / 60 / 263 ~= 2146.31 | |
317 | u32 mult = Config.PsxType ? 8836089 : 8791293; | |
318 | rcnts[3].cycle = hsync_steps * mult >> 12; | |
319 | } | |
320 | } | |
321 | ||
ef79bbde P |
322 | void psxRcntUpdate() |
323 | { | |
d3d41455 | 324 | u32 cycle, cycles_passed; |
ef79bbde P |
325 | |
326 | cycle = psxRegs.cycle; | |
327 | ||
328 | // rcnt 0. | |
d3d41455 | 329 | cycles_passed = cycle - rcnts[0].cycleStart; |
330 | while( cycles_passed >= rcnts[0].cycle ) | |
ef79bbde | 331 | { |
d3d41455 | 332 | if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
333 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
d6b2a130 | 334 | && cycles_passed > lineCycles()) |
d3d41455 | 335 | { |
d6b2a130 | 336 | u32 q = cycles_passed / (lineCycles() + 1u); |
337 | rcnts[0].cycleStart += q * lineCycles(); | |
d3d41455 | 338 | break; |
339 | } | |
340 | else | |
341 | psxRcntReset( 0 ); | |
342 | ||
343 | cycles_passed = cycle - rcnts[0].cycleStart; | |
ef79bbde P |
344 | } |
345 | ||
346 | // rcnt 1. | |
74a0bb9f | 347 | while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) |
ef79bbde P |
348 | { |
349 | psxRcntReset( 1 ); | |
350 | } | |
351 | ||
352 | // rcnt 2. | |
74a0bb9f | 353 | while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) |
ef79bbde P |
354 | { |
355 | psxRcntReset( 2 ); | |
356 | } | |
357 | ||
358 | // rcnt base. | |
359 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
360 | { | |
61ef5cf4 | 361 | hSyncCount += hsync_steps; |
ef79bbde | 362 | |
ef79bbde | 363 | // VSync irq. |
0486fdc9 | 364 | if( hSyncCount == VBlankStart ) |
ef79bbde | 365 | { |
adb7d7ac | 366 | HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF); |
72e5023f | 367 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 368 | setIrq( 0x01 ); |
369 | ||
370 | EmuUpdate(); | |
371 | GPU_updateLace(); | |
d618a240 | 372 | |
373 | if( SPU_async ) | |
374 | { | |
375 | SPU_async( cycle, 1 ); | |
376 | } | |
ef79bbde P |
377 | } |
378 | ||
840639a5 | 379 | // Update lace. |
380 | if( hSyncCount >= HSyncTotal[Config.PsxType] ) | |
ef79bbde | 381 | { |
d6b2a130 | 382 | u32 status, field = 0; |
43614ebd | 383 | rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; |
ef79bbde | 384 | hSyncCount = 0; |
ddbaf678 | 385 | frame_counter++; |
ef79bbde | 386 | |
0486fdc9 | 387 | gpuSyncPluginSR(); |
4db82c07 | 388 | status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD; |
389 | if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) { | |
390 | field = frame_counter & 1; | |
391 | status |= field << 31; | |
392 | status ^= field << 13; | |
393 | } | |
394 | HW_GPU_STATUS = SWAP32(status); | |
395 | GPU_vBlank(0, field); | |
8cba0a22 | 396 | if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0) |
397 | psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow | |
d3d41455 | 398 | |
d6b2a130 | 399 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
400 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
401 | { | |
402 | rcnts[0].cycleStart = rcnts[3].cycleStart; | |
403 | } | |
404 | ||
405 | if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
406 | (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
407 | { | |
408 | rcnts[1].cycleStart = rcnts[3].cycleStart; | |
409 | } | |
410 | else if (rcnts[1].mode & Rc1HSyncClock) | |
d3d41455 | 411 | { |
d6b2a130 | 412 | // adjust to remove the rounding error |
413 | _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate); | |
d3d41455 | 414 | } |
ef79bbde | 415 | } |
61ef5cf4 | 416 | |
43614ebd | 417 | scheduleRcntBase(); |
ef79bbde P |
418 | } |
419 | ||
95df1a04 | 420 | psxRcntSet(); |
421 | ||
ee8fd567 | 422 | #if 0 //ndef NDEBUG |
ef79bbde | 423 | DebugVSync(); |
61ef5cf4 | 424 | #endif |
ef79bbde P |
425 | } |
426 | ||
427 | /******************************************************************************/ | |
428 | ||
429 | void psxRcntWcount( u32 index, u32 value ) | |
430 | { | |
431 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
432 | ||
ef79bbde P |
433 | _psxRcntWcount( index, value ); |
434 | psxRcntSet(); | |
435 | } | |
436 | ||
437 | void psxRcntWmode( u32 index, u32 value ) | |
438 | { | |
439 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
440 | ||
a29f182f | 441 | _psxRcntWmode( index, value ); |
ef79bbde | 442 | _psxRcntWcount( index, 0 ); |
a29f182f | 443 | |
444 | rcnts[index].irqState = 0; | |
ef79bbde P |
445 | psxRcntSet(); |
446 | } | |
447 | ||
448 | void psxRcntWtarget( u32 index, u32 value ) | |
449 | { | |
450 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
451 | ||
ef79bbde P |
452 | rcnts[index].target = value; |
453 | ||
454 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
455 | psxRcntSet(); | |
456 | } | |
457 | ||
458 | /******************************************************************************/ | |
459 | ||
d3d41455 | 460 | u32 psxRcntRcount0() |
461 | { | |
462 | u32 index = 0; | |
463 | u32 count; | |
464 | ||
465 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
466 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
467 | { | |
468 | count = psxRegs.cycle - rcnts[index].cycleStart; | |
d6b2a130 | 469 | //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u; |
470 | count = count % lineCycles(); | |
d3d41455 | 471 | rcnts[index].cycleStart = psxRegs.cycle - count; |
472 | } | |
473 | else | |
474 | count = _psxRcntRcount( index ); | |
475 | ||
476 | verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
477 | ||
478 | return count; | |
479 | } | |
480 | ||
481 | u32 psxRcntRcount1() | |
482 | { | |
483 | u32 index = 1; | |
484 | u32 count; | |
485 | ||
486 | count = _psxRcntRcount( index ); | |
487 | ||
488 | verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
489 | ||
490 | return count; | |
491 | } | |
492 | ||
493 | u32 psxRcntRcount2() | |
ef79bbde | 494 | { |
d3d41455 | 495 | u32 index = 2; |
ef79bbde P |
496 | u32 count; |
497 | ||
ef79bbde P |
498 | count = _psxRcntRcount( index ); |
499 | ||
d3d41455 | 500 | verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode); |
ef79bbde P |
501 | |
502 | return count; | |
503 | } | |
504 | ||
505 | u32 psxRcntRmode( u32 index ) | |
506 | { | |
507 | u16 mode; | |
508 | ||
ef79bbde P |
509 | mode = rcnts[index].mode; |
510 | rcnts[index].mode &= 0xe7ff; | |
511 | ||
512 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
513 | ||
514 | return mode; | |
515 | } | |
516 | ||
517 | u32 psxRcntRtarget( u32 index ) | |
518 | { | |
519 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
520 | ||
521 | return rcnts[index].target; | |
522 | } | |
523 | ||
524 | /******************************************************************************/ | |
525 | ||
526 | void psxRcntInit() | |
527 | { | |
528 | s32 i; | |
529 | ||
530 | // rcnt 0. | |
531 | rcnts[0].rate = 1; | |
532 | rcnts[0].irq = 0x10; | |
533 | ||
534 | // rcnt 1. | |
535 | rcnts[1].rate = 1; | |
536 | rcnts[1].irq = 0x20; | |
537 | ||
538 | // rcnt 2. | |
539 | rcnts[2].rate = 1; | |
540 | rcnts[2].irq = 0x40; | |
541 | ||
542 | // rcnt base. | |
543 | rcnts[3].rate = 1; | |
ef79bbde P |
544 | |
545 | for( i = 0; i < CounterQuantity; ++i ) | |
546 | { | |
547 | _psxRcntWcount( i, 0 ); | |
548 | } | |
549 | ||
c62b43c9 | 550 | hSyncCount = 0; |
61ef5cf4 | 551 | hsync_steps = 1; |
c62b43c9 | 552 | |
d6b2a130 | 553 | scheduleRcntBase(); |
ef79bbde P |
554 | psxRcntSet(); |
555 | } | |
556 | ||
557 | /******************************************************************************/ | |
558 | ||
496d88d4 | 559 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 560 | { |
d618a240 | 561 | u32 spuSyncCount = 0; |
6a3fa667 | 562 | u32 count; |
a29f182f | 563 | s32 i; |
564 | ||
1a32b0f8 | 565 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
ef79bbde P |
566 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
567 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
568 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
569 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
570 | ||
61ef5cf4 | 571 | if (Mode == 0) |
a29f182f | 572 | { |
630b122b | 573 | rcnts[3].rate = 1; |
403a6290 | 574 | for( i = 0; i < CounterQuantity - 1; ++i ) |
6a3fa667 | 575 | { |
a29f182f | 576 | _psxRcntWmode( i, rcnts[i].mode ); |
6a3fa667 | 577 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; |
578 | if (count > 0x1000) | |
579 | _psxRcntWcount( i, count & 0xffff ); | |
580 | } | |
43614ebd | 581 | scheduleRcntBase(); |
a29f182f | 582 | psxRcntSet(); |
a29f182f | 583 | } |
4f55097d | 584 | |
ef79bbde P |
585 | return 0; |
586 | } | |
587 | ||
588 | /******************************************************************************/ | |
43614ebd | 589 | // vim:ts=4:shiftwidth=4:expandtab |