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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
ddbaf678 | 25 | #include "gpu.h" |
fc8145b7 | 26 | #include "debug.h" |
ef79bbde P |
27 | |
28 | /******************************************************************************/ | |
29 | ||
ef79bbde P |
30 | enum |
31 | { | |
32 | Rc0Gate = 0x0001, // 0 not implemented | |
33 | Rc1Gate = 0x0001, // 0 not implemented | |
34 | Rc2Disable = 0x0001, // 0 partially implemented | |
35 | RcUnknown1 = 0x0002, // 1 ? | |
36 | RcUnknown2 = 0x0004, // 2 ? | |
37 | RcCountToTarget = 0x0008, // 3 | |
38 | RcIrqOnTarget = 0x0010, // 4 | |
39 | RcIrqOnOverflow = 0x0020, // 5 | |
40 | RcIrqRegenerate = 0x0040, // 6 | |
41 | RcUnknown7 = 0x0080, // 7 ? | |
42 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
43 | Rc1HSyncClock = 0x0100, // 8 | |
44 | Rc2Unknown8 = 0x0100, // 8 ? | |
45 | Rc0Unknown9 = 0x0200, // 9 ? | |
46 | Rc1Unknown9 = 0x0200, // 9 ? | |
47 | Rc2OneEighthClock = 0x0200, // 9 | |
48 | RcUnknown10 = 0x0400, // 10 ? | |
49 | RcCountEqTarget = 0x0800, // 11 | |
50 | RcOverflow = 0x1000, // 12 | |
51 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
52 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
53 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
54 | }; | |
55 | ||
56 | #define CounterQuantity ( 4 ) | |
57 | //static const u32 CounterQuantity = 4; | |
58 | ||
59 | static const u32 CountToOverflow = 0; | |
60 | static const u32 CountToTarget = 1; | |
61 | ||
62 | static const u32 FrameRate[] = { 60, 50 }; | |
a9836fd6 | 63 | static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL |
0486fdc9 | 64 | #define VBlankStart 240 |
ef79bbde | 65 | |
9f7ee52e | 66 | #define VERBOSE_LEVEL 0 |
4b7da20a | 67 | #if VERBOSE_LEVEL > 0 |
9f7ee52e | 68 | static const s32 VerboseLevel = VERBOSE_LEVEL; |
4b7da20a | 69 | #endif |
ef79bbde P |
70 | |
71 | /******************************************************************************/ | |
72 | ||
1a32b0f8 | 73 | #ifndef NEW_DYNAREC |
93c9e42a | 74 | Rcnt rcnts[ CounterQuantity ]; |
1a32b0f8 | 75 | #endif |
93c9e42a | 76 | |
24de2dd4 | 77 | u32 hSyncCount = 0; |
78 | u32 frame_counter = 0; | |
61ef5cf4 | 79 | static u32 hsync_steps = 0; |
4f55097d | 80 | static u32 base_cycle = 0; |
ef79bbde P |
81 | |
82 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
83 | ||
84 | /******************************************************************************/ | |
85 | ||
86 | static inline | |
87 | void setIrq( u32 irq ) | |
88 | { | |
89 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
90 | } | |
91 | ||
92 | static | |
9f7ee52e | 93 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 94 | { |
9f7ee52e | 95 | #if VERBOSE_LEVEL > 0 |
ef79bbde P |
96 | if( level <= VerboseLevel ) |
97 | { | |
98 | va_list va; | |
99 | char buf[ 4096 ]; | |
100 | ||
101 | va_start( va, str ); | |
102 | vsprintf( buf, str, va ); | |
103 | va_end( va ); | |
104 | ||
ab948f7e | 105 | printf( "%s", buf ); |
ef79bbde P |
106 | fflush( stdout ); |
107 | } | |
9f7ee52e | 108 | #endif |
ef79bbde P |
109 | } |
110 | ||
111 | /******************************************************************************/ | |
112 | ||
113 | static inline | |
114 | void _psxRcntWcount( u32 index, u32 value ) | |
115 | { | |
116 | if( value > 0xffff ) | |
117 | { | |
118 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
119 | value &= 0xffff; | |
120 | } | |
121 | ||
122 | rcnts[index].cycleStart = psxRegs.cycle; | |
123 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
124 | ||
125 | // TODO: <=. | |
126 | if( value < rcnts[index].target ) | |
127 | { | |
128 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
129 | rcnts[index].counterState = CountToTarget; | |
130 | } | |
131 | else | |
132 | { | |
8ca6b0a6 | 133 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
134 | rcnts[index].counterState = CountToOverflow; |
135 | } | |
136 | } | |
137 | ||
138 | static inline | |
139 | u32 _psxRcntRcount( u32 index ) | |
140 | { | |
141 | u32 count; | |
142 | ||
143 | count = psxRegs.cycle; | |
144 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 145 | if (rcnts[index].rate > 1) |
146 | count /= rcnts[index].rate; | |
ef79bbde | 147 | |
8ca6b0a6 | 148 | if( count > 0x10000 ) |
ef79bbde | 149 | { |
8ca6b0a6 | 150 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 151 | } |
8ca6b0a6 | 152 | count &= 0xffff; |
ef79bbde P |
153 | |
154 | return count; | |
155 | } | |
156 | ||
a29f182f | 157 | static |
158 | void _psxRcntWmode( u32 index, u32 value ) | |
159 | { | |
160 | rcnts[index].mode = value; | |
161 | ||
162 | switch( index ) | |
163 | { | |
164 | case 0: | |
165 | if( value & Rc0PixelClock ) | |
166 | { | |
167 | rcnts[index].rate = 5; | |
168 | } | |
169 | else | |
170 | { | |
171 | rcnts[index].rate = 1; | |
172 | } | |
173 | break; | |
174 | case 1: | |
175 | if( value & Rc1HSyncClock ) | |
176 | { | |
177 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
178 | } | |
179 | else | |
180 | { | |
181 | rcnts[index].rate = 1; | |
182 | } | |
183 | break; | |
184 | case 2: | |
185 | if( value & Rc2OneEighthClock ) | |
186 | { | |
187 | rcnts[index].rate = 8; | |
188 | } | |
189 | else | |
190 | { | |
191 | rcnts[index].rate = 1; | |
192 | } | |
193 | ||
194 | // TODO: wcount must work. | |
195 | if( value & Rc2Disable ) | |
196 | { | |
197 | rcnts[index].rate = 0xffffffff; | |
198 | } | |
199 | break; | |
200 | } | |
201 | } | |
202 | ||
ef79bbde P |
203 | /******************************************************************************/ |
204 | ||
205 | static | |
206 | void psxRcntSet() | |
207 | { | |
208 | s32 countToUpdate; | |
209 | u32 i; | |
210 | ||
211 | psxNextsCounter = psxRegs.cycle; | |
212 | psxNextCounter = 0x7fffffff; | |
213 | ||
214 | for( i = 0; i < CounterQuantity; ++i ) | |
215 | { | |
216 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
217 | ||
218 | if( countToUpdate < 0 ) | |
219 | { | |
220 | psxNextCounter = 0; | |
221 | break; | |
222 | } | |
223 | ||
224 | if( countToUpdate < (s32)psxNextCounter ) | |
225 | { | |
226 | psxNextCounter = countToUpdate; | |
227 | } | |
228 | } | |
5b8c000f | 229 | |
230 | psxRegs.interrupt |= (1 << PSXINT_RCNT); | |
231 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); | |
ef79bbde P |
232 | } |
233 | ||
234 | /******************************************************************************/ | |
235 | ||
236 | static | |
237 | void psxRcntReset( u32 index ) | |
238 | { | |
8ca6b0a6 | 239 | u32 rcycles; |
ef79bbde | 240 | |
53c361f0 | 241 | rcnts[index].mode |= RcUnknown10; |
242 | ||
ef79bbde P |
243 | if( rcnts[index].counterState == CountToTarget ) |
244 | { | |
8ca6b0a6 | 245 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 246 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 247 | { |
248 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
249 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
250 | } | |
251 | else | |
252 | { | |
253 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
254 | rcnts[index].counterState = CountToOverflow; | |
255 | } | |
ef79bbde P |
256 | |
257 | if( rcnts[index].mode & RcIrqOnTarget ) | |
258 | { | |
259 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
260 | { | |
8ca6b0a6 | 261 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
262 | setIrq( rcnts[index].irq ); |
263 | rcnts[index].irqState = 1; | |
264 | } | |
265 | } | |
266 | ||
267 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 268 | |
8ca6b0a6 | 269 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 270 | return; |
ef79bbde | 271 | } |
53c361f0 | 272 | |
273 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 274 | { |
8ca6b0a6 | 275 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
276 | rcycles -= 0x10000 * rcnts[index].rate; | |
277 | ||
278 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 279 | |
8ca6b0a6 | 280 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
281 | { | |
282 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
283 | rcnts[index].counterState = CountToTarget; | |
284 | } | |
ef79bbde P |
285 | |
286 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
287 | { | |
288 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
289 | { | |
8ca6b0a6 | 290 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
291 | setIrq( rcnts[index].irq ); |
292 | rcnts[index].irqState = 1; | |
293 | } | |
294 | } | |
295 | ||
296 | rcnts[index].mode |= RcOverflow; | |
297 | } | |
ef79bbde P |
298 | } |
299 | ||
300 | void psxRcntUpdate() | |
301 | { | |
302 | u32 cycle; | |
303 | ||
304 | cycle = psxRegs.cycle; | |
305 | ||
306 | // rcnt 0. | |
307 | if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) | |
308 | { | |
309 | psxRcntReset( 0 ); | |
310 | } | |
311 | ||
312 | // rcnt 1. | |
313 | if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) | |
314 | { | |
315 | psxRcntReset( 1 ); | |
316 | } | |
317 | ||
318 | // rcnt 2. | |
319 | if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) | |
320 | { | |
321 | psxRcntReset( 2 ); | |
322 | } | |
323 | ||
324 | // rcnt base. | |
325 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
326 | { | |
61ef5cf4 | 327 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
d618a240 | 328 | u32 next_vsync; |
ef79bbde | 329 | |
61ef5cf4 | 330 | hSyncCount += hsync_steps; |
ef79bbde | 331 | |
ef79bbde | 332 | // VSync irq. |
0486fdc9 | 333 | if( hSyncCount == VBlankStart ) |
ef79bbde | 334 | { |
0486fdc9 | 335 | HW_GPU_STATUS &= ~PSXGPU_LCF; |
72e5023f | 336 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 337 | setIrq( 0x01 ); |
338 | ||
339 | EmuUpdate(); | |
340 | GPU_updateLace(); | |
d618a240 | 341 | |
342 | if( SPU_async ) | |
343 | { | |
344 | SPU_async( cycle, 1 ); | |
345 | } | |
ef79bbde P |
346 | } |
347 | ||
348 | // Update lace. (with InuYasha fix) | |
349 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) | |
350 | { | |
351 | hSyncCount = 0; | |
ddbaf678 | 352 | frame_counter++; |
ef79bbde | 353 | |
0486fdc9 | 354 | gpuSyncPluginSR(); |
355 | if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS ) | |
ddbaf678 | 356 | HW_GPU_STATUS |= frame_counter << 31; |
72e5023f | 357 | GPU_vBlank( 0, HW_GPU_STATUS >> 31 ); |
ef79bbde | 358 | } |
61ef5cf4 | 359 | |
360 | // Schedule next call, in hsyncs | |
d618a240 | 361 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; |
0486fdc9 | 362 | next_vsync = VBlankStart - hSyncCount; // ok to overflow |
61ef5cf4 | 363 | if( next_vsync && next_vsync < hsync_steps ) |
364 | hsync_steps = next_vsync; | |
61ef5cf4 | 365 | |
366 | rcnts[3].cycleStart = cycle - leftover_cycles; | |
4f55097d | 367 | if (Config.PsxType) |
368 | // 20.12 precision, clk / 50 / 313 ~= 2164.14 | |
369 | base_cycle += hsync_steps * 8864320; | |
370 | else | |
371 | // clk / 60 / 263 ~= 2146.31 | |
372 | base_cycle += hsync_steps * 8791293; | |
373 | rcnts[3].cycle = base_cycle >> 12; | |
374 | base_cycle &= 0xfff; | |
ef79bbde P |
375 | } |
376 | ||
95df1a04 | 377 | psxRcntSet(); |
378 | ||
61ef5cf4 | 379 | #ifndef NDEBUG |
ef79bbde | 380 | DebugVSync(); |
61ef5cf4 | 381 | #endif |
ef79bbde P |
382 | } |
383 | ||
384 | /******************************************************************************/ | |
385 | ||
386 | void psxRcntWcount( u32 index, u32 value ) | |
387 | { | |
388 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
389 | ||
ef79bbde P |
390 | _psxRcntWcount( index, value ); |
391 | psxRcntSet(); | |
392 | } | |
393 | ||
394 | void psxRcntWmode( u32 index, u32 value ) | |
395 | { | |
396 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
397 | ||
a29f182f | 398 | _psxRcntWmode( index, value ); |
ef79bbde | 399 | _psxRcntWcount( index, 0 ); |
a29f182f | 400 | |
401 | rcnts[index].irqState = 0; | |
ef79bbde P |
402 | psxRcntSet(); |
403 | } | |
404 | ||
405 | void psxRcntWtarget( u32 index, u32 value ) | |
406 | { | |
407 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
408 | ||
ef79bbde P |
409 | rcnts[index].target = value; |
410 | ||
411 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
412 | psxRcntSet(); | |
413 | } | |
414 | ||
415 | /******************************************************************************/ | |
416 | ||
417 | u32 psxRcntRcount( u32 index ) | |
418 | { | |
419 | u32 count; | |
420 | ||
ef79bbde P |
421 | count = _psxRcntRcount( index ); |
422 | ||
423 | // Parasite Eve 2 fix. | |
424 | if( Config.RCntFix ) | |
425 | { | |
426 | if( index == 2 ) | |
427 | { | |
428 | if( rcnts[index].counterState == CountToTarget ) | |
429 | { | |
430 | count /= BIAS; | |
431 | } | |
432 | } | |
433 | } | |
434 | ||
435 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); | |
436 | ||
437 | return count; | |
438 | } | |
439 | ||
440 | u32 psxRcntRmode( u32 index ) | |
441 | { | |
442 | u16 mode; | |
443 | ||
ef79bbde P |
444 | mode = rcnts[index].mode; |
445 | rcnts[index].mode &= 0xe7ff; | |
446 | ||
447 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
448 | ||
449 | return mode; | |
450 | } | |
451 | ||
452 | u32 psxRcntRtarget( u32 index ) | |
453 | { | |
454 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
455 | ||
456 | return rcnts[index].target; | |
457 | } | |
458 | ||
459 | /******************************************************************************/ | |
460 | ||
461 | void psxRcntInit() | |
462 | { | |
463 | s32 i; | |
464 | ||
465 | // rcnt 0. | |
466 | rcnts[0].rate = 1; | |
467 | rcnts[0].irq = 0x10; | |
468 | ||
469 | // rcnt 1. | |
470 | rcnts[1].rate = 1; | |
471 | rcnts[1].irq = 0x20; | |
472 | ||
473 | // rcnt 2. | |
474 | rcnts[2].rate = 1; | |
475 | rcnts[2].irq = 0x40; | |
476 | ||
477 | // rcnt base. | |
478 | rcnts[3].rate = 1; | |
479 | rcnts[3].mode = RcCountToTarget; | |
480 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
481 | ||
482 | for( i = 0; i < CounterQuantity; ++i ) | |
483 | { | |
484 | _psxRcntWcount( i, 0 ); | |
485 | } | |
486 | ||
c62b43c9 | 487 | hSyncCount = 0; |
61ef5cf4 | 488 | hsync_steps = 1; |
c62b43c9 | 489 | |
ef79bbde P |
490 | psxRcntSet(); |
491 | } | |
492 | ||
493 | /******************************************************************************/ | |
494 | ||
496d88d4 | 495 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 496 | { |
d618a240 | 497 | u32 spuSyncCount = 0; |
a29f182f | 498 | u32 count; |
499 | s32 i; | |
500 | ||
1a32b0f8 | 501 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
ef79bbde P |
502 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
503 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
504 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
505 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
506 | ||
61ef5cf4 | 507 | if (Mode == 0) |
a29f182f | 508 | { |
509 | // don't trust things from a savestate | |
510 | for( i = 0; i < CounterQuantity; ++i ) | |
511 | { | |
512 | _psxRcntWmode( i, rcnts[i].mode ); | |
513 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; | |
514 | _psxRcntWcount( i, count ); | |
515 | } | |
61ef5cf4 | 516 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; |
a29f182f | 517 | psxRcntSet(); |
61ef5cf4 | 518 | |
a29f182f | 519 | base_cycle = 0; |
520 | } | |
4f55097d | 521 | |
ef79bbde P |
522 | return 0; |
523 | } | |
524 | ||
525 | /******************************************************************************/ |