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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
ddbaf678 | 25 | #include "gpu.h" |
fc8145b7 | 26 | #include "debug.h" |
ef79bbde P |
27 | |
28 | /******************************************************************************/ | |
29 | ||
ef79bbde P |
30 | enum |
31 | { | |
32 | Rc0Gate = 0x0001, // 0 not implemented | |
33 | Rc1Gate = 0x0001, // 0 not implemented | |
34 | Rc2Disable = 0x0001, // 0 partially implemented | |
35 | RcUnknown1 = 0x0002, // 1 ? | |
36 | RcUnknown2 = 0x0004, // 2 ? | |
37 | RcCountToTarget = 0x0008, // 3 | |
38 | RcIrqOnTarget = 0x0010, // 4 | |
39 | RcIrqOnOverflow = 0x0020, // 5 | |
40 | RcIrqRegenerate = 0x0040, // 6 | |
41 | RcUnknown7 = 0x0080, // 7 ? | |
42 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
43 | Rc1HSyncClock = 0x0100, // 8 | |
44 | Rc2Unknown8 = 0x0100, // 8 ? | |
45 | Rc0Unknown9 = 0x0200, // 9 ? | |
46 | Rc1Unknown9 = 0x0200, // 9 ? | |
47 | Rc2OneEighthClock = 0x0200, // 9 | |
48 | RcUnknown10 = 0x0400, // 10 ? | |
49 | RcCountEqTarget = 0x0800, // 11 | |
50 | RcOverflow = 0x1000, // 12 | |
51 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
52 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
53 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
54 | }; | |
55 | ||
56 | #define CounterQuantity ( 4 ) | |
57 | //static const u32 CounterQuantity = 4; | |
58 | ||
59 | static const u32 CountToOverflow = 0; | |
60 | static const u32 CountToTarget = 1; | |
61 | ||
62 | static const u32 FrameRate[] = { 60, 50 }; | |
630b122b | 63 | static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL |
0486fdc9 | 64 | #define VBlankStart 240 |
ef79bbde | 65 | |
9f7ee52e | 66 | #define VERBOSE_LEVEL 0 |
ef79bbde P |
67 | |
68 | /******************************************************************************/ | |
630b122b | 69 | #ifdef DRC_DISABLE |
93c9e42a | 70 | Rcnt rcnts[ CounterQuantity ]; |
1a32b0f8 | 71 | #endif |
24de2dd4 | 72 | u32 hSyncCount = 0; |
73 | u32 frame_counter = 0; | |
61ef5cf4 | 74 | static u32 hsync_steps = 0; |
ef79bbde P |
75 | |
76 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
77 | ||
78 | /******************************************************************************/ | |
79 | ||
80 | static inline | |
81 | void setIrq( u32 irq ) | |
82 | { | |
83 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
84 | } | |
85 | ||
86 | static | |
9f7ee52e | 87 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 88 | { |
9f7ee52e | 89 | #if VERBOSE_LEVEL > 0 |
630b122b | 90 | if( level <= VERBOSE_LEVEL ) |
ef79bbde P |
91 | { |
92 | va_list va; | |
93 | char buf[ 4096 ]; | |
94 | ||
95 | va_start( va, str ); | |
96 | vsprintf( buf, str, va ); | |
97 | va_end( va ); | |
98 | ||
ab948f7e | 99 | printf( "%s", buf ); |
ef79bbde P |
100 | fflush( stdout ); |
101 | } | |
9f7ee52e | 102 | #endif |
ef79bbde P |
103 | } |
104 | ||
105 | /******************************************************************************/ | |
106 | ||
107 | static inline | |
108 | void _psxRcntWcount( u32 index, u32 value ) | |
109 | { | |
110 | if( value > 0xffff ) | |
111 | { | |
112 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
113 | value &= 0xffff; | |
114 | } | |
115 | ||
116 | rcnts[index].cycleStart = psxRegs.cycle; | |
117 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
118 | ||
119 | // TODO: <=. | |
120 | if( value < rcnts[index].target ) | |
121 | { | |
122 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
123 | rcnts[index].counterState = CountToTarget; | |
124 | } | |
125 | else | |
126 | { | |
8ca6b0a6 | 127 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
128 | rcnts[index].counterState = CountToOverflow; |
129 | } | |
130 | } | |
131 | ||
132 | static inline | |
133 | u32 _psxRcntRcount( u32 index ) | |
134 | { | |
135 | u32 count; | |
136 | ||
137 | count = psxRegs.cycle; | |
138 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 139 | if (rcnts[index].rate > 1) |
140 | count /= rcnts[index].rate; | |
ef79bbde | 141 | |
8ca6b0a6 | 142 | if( count > 0x10000 ) |
ef79bbde | 143 | { |
8ca6b0a6 | 144 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 145 | } |
8ca6b0a6 | 146 | count &= 0xffff; |
ef79bbde P |
147 | |
148 | return count; | |
149 | } | |
150 | ||
a29f182f | 151 | static |
152 | void _psxRcntWmode( u32 index, u32 value ) | |
153 | { | |
154 | rcnts[index].mode = value; | |
155 | ||
156 | switch( index ) | |
157 | { | |
158 | case 0: | |
159 | if( value & Rc0PixelClock ) | |
160 | { | |
161 | rcnts[index].rate = 5; | |
162 | } | |
163 | else | |
164 | { | |
165 | rcnts[index].rate = 1; | |
166 | } | |
167 | break; | |
168 | case 1: | |
169 | if( value & Rc1HSyncClock ) | |
170 | { | |
171 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
172 | } | |
173 | else | |
174 | { | |
175 | rcnts[index].rate = 1; | |
176 | } | |
177 | break; | |
178 | case 2: | |
179 | if( value & Rc2OneEighthClock ) | |
180 | { | |
181 | rcnts[index].rate = 8; | |
182 | } | |
183 | else | |
184 | { | |
185 | rcnts[index].rate = 1; | |
186 | } | |
187 | ||
188 | // TODO: wcount must work. | |
189 | if( value & Rc2Disable ) | |
190 | { | |
191 | rcnts[index].rate = 0xffffffff; | |
192 | } | |
193 | break; | |
194 | } | |
195 | } | |
196 | ||
ef79bbde P |
197 | /******************************************************************************/ |
198 | ||
199 | static | |
200 | void psxRcntSet() | |
201 | { | |
202 | s32 countToUpdate; | |
203 | u32 i; | |
204 | ||
205 | psxNextsCounter = psxRegs.cycle; | |
206 | psxNextCounter = 0x7fffffff; | |
207 | ||
208 | for( i = 0; i < CounterQuantity; ++i ) | |
209 | { | |
210 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
211 | ||
212 | if( countToUpdate < 0 ) | |
213 | { | |
214 | psxNextCounter = 0; | |
215 | break; | |
216 | } | |
217 | ||
218 | if( countToUpdate < (s32)psxNextCounter ) | |
219 | { | |
220 | psxNextCounter = countToUpdate; | |
221 | } | |
222 | } | |
5b8c000f | 223 | |
224 | psxRegs.interrupt |= (1 << PSXINT_RCNT); | |
225 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); | |
ef79bbde P |
226 | } |
227 | ||
228 | /******************************************************************************/ | |
229 | ||
230 | static | |
231 | void psxRcntReset( u32 index ) | |
232 | { | |
8ca6b0a6 | 233 | u32 rcycles; |
ef79bbde | 234 | |
53c361f0 | 235 | rcnts[index].mode |= RcUnknown10; |
236 | ||
ef79bbde P |
237 | if( rcnts[index].counterState == CountToTarget ) |
238 | { | |
8ca6b0a6 | 239 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 240 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 241 | { |
242 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
243 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
244 | } | |
245 | else | |
246 | { | |
247 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
248 | rcnts[index].counterState = CountToOverflow; | |
249 | } | |
ef79bbde P |
250 | |
251 | if( rcnts[index].mode & RcIrqOnTarget ) | |
252 | { | |
253 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
254 | { | |
8ca6b0a6 | 255 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
256 | setIrq( rcnts[index].irq ); |
257 | rcnts[index].irqState = 1; | |
258 | } | |
259 | } | |
260 | ||
261 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 262 | |
8ca6b0a6 | 263 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 264 | return; |
ef79bbde | 265 | } |
53c361f0 | 266 | |
267 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 268 | { |
8ca6b0a6 | 269 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
270 | rcycles -= 0x10000 * rcnts[index].rate; | |
271 | ||
272 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 273 | |
8ca6b0a6 | 274 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
275 | { | |
276 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
277 | rcnts[index].counterState = CountToTarget; | |
278 | } | |
ef79bbde P |
279 | |
280 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
281 | { | |
282 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
283 | { | |
8ca6b0a6 | 284 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
285 | setIrq( rcnts[index].irq ); |
286 | rcnts[index].irqState = 1; | |
287 | } | |
288 | } | |
289 | ||
290 | rcnts[index].mode |= RcOverflow; | |
291 | } | |
ef79bbde P |
292 | } |
293 | ||
43614ebd | 294 | static void scheduleRcntBase(void) |
295 | { | |
296 | // Schedule next call, in hsyncs | |
297 | if (hSyncCount < VBlankStart) | |
298 | hsync_steps = VBlankStart - hSyncCount; | |
299 | else | |
300 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; | |
301 | ||
302 | if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType]) | |
303 | { | |
304 | rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; | |
305 | } | |
306 | else | |
307 | { | |
308 | // clk / 50 / 314 ~= 2157.25 | |
309 | // clk / 60 / 263 ~= 2146.31 | |
310 | u32 mult = Config.PsxType ? 8836089 : 8791293; | |
311 | rcnts[3].cycle = hsync_steps * mult >> 12; | |
312 | } | |
313 | } | |
314 | ||
ef79bbde P |
315 | void psxRcntUpdate() |
316 | { | |
317 | u32 cycle; | |
318 | ||
319 | cycle = psxRegs.cycle; | |
320 | ||
321 | // rcnt 0. | |
74a0bb9f | 322 | while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) |
ef79bbde P |
323 | { |
324 | psxRcntReset( 0 ); | |
325 | } | |
326 | ||
327 | // rcnt 1. | |
74a0bb9f | 328 | while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) |
ef79bbde P |
329 | { |
330 | psxRcntReset( 1 ); | |
331 | } | |
332 | ||
333 | // rcnt 2. | |
74a0bb9f | 334 | while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) |
ef79bbde P |
335 | { |
336 | psxRcntReset( 2 ); | |
337 | } | |
338 | ||
339 | // rcnt base. | |
340 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
341 | { | |
61ef5cf4 | 342 | hSyncCount += hsync_steps; |
ef79bbde | 343 | |
ef79bbde | 344 | // VSync irq. |
0486fdc9 | 345 | if( hSyncCount == VBlankStart ) |
ef79bbde | 346 | { |
adb7d7ac | 347 | HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF); |
72e5023f | 348 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 349 | setIrq( 0x01 ); |
350 | ||
351 | EmuUpdate(); | |
352 | GPU_updateLace(); | |
d618a240 | 353 | |
354 | if( SPU_async ) | |
355 | { | |
356 | SPU_async( cycle, 1 ); | |
357 | } | |
ef79bbde P |
358 | } |
359 | ||
840639a5 | 360 | // Update lace. |
361 | if( hSyncCount >= HSyncTotal[Config.PsxType] ) | |
ef79bbde | 362 | { |
43614ebd | 363 | rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; |
ef79bbde | 364 | hSyncCount = 0; |
ddbaf678 | 365 | frame_counter++; |
ef79bbde | 366 | |
0486fdc9 | 367 | gpuSyncPluginSR(); |
adb7d7ac PC |
368 | if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS)) |
369 | HW_GPU_STATUS |= SWAP32(frame_counter << 31); | |
370 | GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31); | |
ef79bbde | 371 | } |
61ef5cf4 | 372 | |
43614ebd | 373 | scheduleRcntBase(); |
ef79bbde P |
374 | } |
375 | ||
95df1a04 | 376 | psxRcntSet(); |
377 | ||
61ef5cf4 | 378 | #ifndef NDEBUG |
ef79bbde | 379 | DebugVSync(); |
61ef5cf4 | 380 | #endif |
ef79bbde P |
381 | } |
382 | ||
383 | /******************************************************************************/ | |
384 | ||
385 | void psxRcntWcount( u32 index, u32 value ) | |
386 | { | |
387 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
388 | ||
ef79bbde P |
389 | _psxRcntWcount( index, value ); |
390 | psxRcntSet(); | |
391 | } | |
392 | ||
393 | void psxRcntWmode( u32 index, u32 value ) | |
394 | { | |
395 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
396 | ||
a29f182f | 397 | _psxRcntWmode( index, value ); |
ef79bbde | 398 | _psxRcntWcount( index, 0 ); |
a29f182f | 399 | |
400 | rcnts[index].irqState = 0; | |
ef79bbde P |
401 | psxRcntSet(); |
402 | } | |
403 | ||
404 | void psxRcntWtarget( u32 index, u32 value ) | |
405 | { | |
406 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
407 | ||
ef79bbde P |
408 | rcnts[index].target = value; |
409 | ||
410 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
411 | psxRcntSet(); | |
412 | } | |
413 | ||
414 | /******************************************************************************/ | |
415 | ||
416 | u32 psxRcntRcount( u32 index ) | |
417 | { | |
418 | u32 count; | |
419 | ||
ef79bbde P |
420 | count = _psxRcntRcount( index ); |
421 | ||
ef79bbde P |
422 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); |
423 | ||
424 | return count; | |
425 | } | |
426 | ||
427 | u32 psxRcntRmode( u32 index ) | |
428 | { | |
429 | u16 mode; | |
430 | ||
ef79bbde P |
431 | mode = rcnts[index].mode; |
432 | rcnts[index].mode &= 0xe7ff; | |
433 | ||
434 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
435 | ||
436 | return mode; | |
437 | } | |
438 | ||
439 | u32 psxRcntRtarget( u32 index ) | |
440 | { | |
441 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
442 | ||
443 | return rcnts[index].target; | |
444 | } | |
445 | ||
446 | /******************************************************************************/ | |
447 | ||
448 | void psxRcntInit() | |
449 | { | |
450 | s32 i; | |
451 | ||
452 | // rcnt 0. | |
453 | rcnts[0].rate = 1; | |
454 | rcnts[0].irq = 0x10; | |
455 | ||
456 | // rcnt 1. | |
457 | rcnts[1].rate = 1; | |
458 | rcnts[1].irq = 0x20; | |
459 | ||
460 | // rcnt 2. | |
461 | rcnts[2].rate = 1; | |
462 | rcnts[2].irq = 0x40; | |
463 | ||
464 | // rcnt base. | |
465 | rcnts[3].rate = 1; | |
466 | rcnts[3].mode = RcCountToTarget; | |
467 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
468 | ||
469 | for( i = 0; i < CounterQuantity; ++i ) | |
470 | { | |
471 | _psxRcntWcount( i, 0 ); | |
472 | } | |
473 | ||
c62b43c9 | 474 | hSyncCount = 0; |
61ef5cf4 | 475 | hsync_steps = 1; |
c62b43c9 | 476 | |
ef79bbde P |
477 | psxRcntSet(); |
478 | } | |
479 | ||
480 | /******************************************************************************/ | |
481 | ||
496d88d4 | 482 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 483 | { |
d618a240 | 484 | u32 spuSyncCount = 0; |
a29f182f | 485 | u32 count; |
486 | s32 i; | |
487 | ||
1a32b0f8 | 488 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
ef79bbde P |
489 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
490 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
491 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
492 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
493 | ||
61ef5cf4 | 494 | if (Mode == 0) |
a29f182f | 495 | { |
496 | // don't trust things from a savestate | |
630b122b | 497 | rcnts[3].rate = 1; |
a29f182f | 498 | for( i = 0; i < CounterQuantity; ++i ) |
499 | { | |
500 | _psxRcntWmode( i, rcnts[i].mode ); | |
501 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; | |
502 | _psxRcntWcount( i, count ); | |
503 | } | |
43614ebd | 504 | scheduleRcntBase(); |
a29f182f | 505 | psxRcntSet(); |
a29f182f | 506 | } |
4f55097d | 507 | |
ef79bbde P |
508 | return 0; |
509 | } | |
510 | ||
511 | /******************************************************************************/ | |
43614ebd | 512 | // vim:ts=4:shiftwidth=4:expandtab |