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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Handles PSX DMA functions. | |
22 | */ | |
23 | ||
24 | #include "psxdma.h" | |
6c036261 | 25 | #include "gpu.h" |
ef79bbde | 26 | |
d01bb904 | 27 | #ifndef min |
28 | #define min(a, b) ((b) < (a) ? (b) : (a)) | |
29 | #endif | |
0300a353 | 30 | #ifndef PSXDMA_LOG |
31 | #define PSXDMA_LOG(...) | |
32 | #endif | |
d01bb904 | 33 | |
ef79bbde P |
34 | // Dma0/1 in Mdec.c |
35 | // Dma3 in CdRom.c | |
36 | ||
37 | void spuInterrupt() { | |
ad418c19 | 38 | if (HW_DMA4_CHCR & SWAP32(0x01000000)) |
39 | { | |
40 | HW_DMA4_CHCR &= SWAP32(~0x01000000); | |
41 | DMA_INTERRUPT(4); | |
42 | } | |
ef79bbde P |
43 | } |
44 | ||
45 | void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU | |
0300a353 | 46 | u32 words, words_max = 0, words_copy; |
ef79bbde | 47 | u16 *ptr; |
ef79bbde | 48 | |
0300a353 | 49 | madr &= ~3; |
50 | ptr = getDmaRam(madr, &words_max); | |
51 | if (ptr == INVALID_PTR) | |
52 | log_unhandled("bad dma4 madr %x\n", madr); | |
53 | ||
54 | words = words_copy = (bcr >> 16) * (bcr & 0xffff); | |
55 | if (words_copy > words_max) { | |
56 | log_unhandled("bad dma4 madr %x bcr %x\n", madr, bcr); | |
57 | words_copy = words_max; | |
58 | } | |
59 | ||
ef79bbde P |
60 | switch (chcr) { |
61 | case 0x01000201: //cpu to spu transfer | |
ef79bbde | 62 | PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %x addr = %x size = %x\n", chcr, madr, bcr); |
0300a353 | 63 | if (ptr == INVALID_PTR) |
ef79bbde | 64 | break; |
0300a353 | 65 | SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle); |
66 | HW_DMA4_MADR = SWAPu32(madr + words_copy * 2); | |
7b68d92c | 67 | SPUDMA_INT(words * 4); |
ef79bbde P |
68 | return; |
69 | ||
70 | case 0x01000200: //spu to cpu transfer | |
ef79bbde | 71 | PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %x addr = %x size = %x\n", chcr, madr, bcr); |
0300a353 | 72 | if (ptr == INVALID_PTR) |
ef79bbde | 73 | break; |
0300a353 | 74 | SPU_readDMAMem(ptr, words_copy * 2, psxRegs.cycle); |
75 | psxCpu->Clear(madr, words_copy); | |
58ebb94c | 76 | |
0300a353 | 77 | HW_DMA4_MADR = SWAPu32(madr + words_copy * 4); |
7b68d92c | 78 | SPUDMA_INT(words * 4); |
58ebb94c | 79 | return; |
ef79bbde | 80 | |
ef79bbde | 81 | default: |
7df2c03c | 82 | log_unhandled("*** DMA4 SPU - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr); |
ef79bbde | 83 | break; |
ef79bbde P |
84 | } |
85 | ||
86 | HW_DMA4_CHCR &= SWAP32(~0x01000000); | |
87 | DMA_INTERRUPT(4); | |
88 | } | |
89 | ||
57a757ce | 90 | // Taken from PEOPS SOFTGPU |
91 | static inline boolean CheckForEndlessLoop(u32 laddr, u32 *lUsedAddr) { | |
92 | if (laddr == lUsedAddr[1]) return TRUE; | |
93 | if (laddr == lUsedAddr[2]) return TRUE; | |
94 | ||
95 | if (laddr < lUsedAddr[0]) lUsedAddr[1] = laddr; | |
96 | else lUsedAddr[2] = laddr; | |
97 | ||
98 | lUsedAddr[0] = laddr; | |
99 | ||
100 | return FALSE; | |
101 | } | |
102 | ||
103 | static u32 gpuDmaChainSize(u32 addr) { | |
104 | u32 size; | |
105 | u32 DMACommandCounter = 0; | |
106 | u32 lUsedAddr[3]; | |
107 | ||
108 | lUsedAddr[0] = lUsedAddr[1] = lUsedAddr[2] = 0xffffff; | |
109 | ||
110 | // initial linked list ptr (word) | |
111 | size = 1; | |
112 | ||
113 | do { | |
114 | addr &= 0x1ffffc; | |
115 | ||
116 | if (DMACommandCounter++ > 2000000) break; | |
117 | if (CheckForEndlessLoop(addr, lUsedAddr)) break; | |
118 | ||
119 | // # 32-bit blocks to transfer | |
120 | size += psxMu8( addr + 3 ); | |
121 | ||
122 | // next 32-bit pointer | |
123 | addr = psxMu32( addr & ~0x3 ) & 0xffffff; | |
124 | size += 1; | |
5b568098 | 125 | } while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF |
126 | // any pointer with bit 23 set will do. | |
57a757ce | 127 | |
128 | return size; | |
129 | } | |
130 | ||
ef79bbde | 131 | void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU |
d01bb904 | 132 | u32 *ptr, madr_next, *madr_next_p, size; |
0300a353 | 133 | u32 words, words_left, words_max, words_copy; |
fae38d7a | 134 | int do_walking; |
ef79bbde | 135 | |
0300a353 | 136 | madr &= ~3; |
57a757ce | 137 | switch (chcr) { |
ef79bbde | 138 | case 0x01000200: // vram2mem |
57a757ce | 139 | PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr); |
d01bb904 | 140 | ptr = getDmaRam(madr, &words_max); |
b012a437 | 141 | if (ptr == INVALID_PTR) { |
0300a353 | 142 | log_unhandled("bad dma2 madr %x\n", madr); |
ef79bbde P |
143 | break; |
144 | } | |
57a757ce | 145 | // BA blocks * BS words (word = 32-bits) |
0300a353 | 146 | words = words_copy = (bcr >> 16) * (bcr & 0xffff); |
147 | if (words > words_max) { | |
148 | log_unhandled("bad dma2 madr %x bcr %x\n", madr, bcr); | |
149 | words_copy = words_max; | |
150 | } | |
d01bb904 | 151 | GPU_readDataMem(ptr, words_copy); |
152 | psxCpu->Clear(madr, words_copy); | |
58ebb94c | 153 | |
0300a353 | 154 | HW_DMA2_MADR = SWAPu32(madr + words_copy * 4); |
57a757ce | 155 | |
156 | // already 32-bit word size ((size * 4) / 4) | |
58ebb94c | 157 | GPUDMA_INT(words / 4); |
57a757ce | 158 | return; |
ef79bbde P |
159 | |
160 | case 0x01000201: // mem2vram | |
57a757ce | 161 | PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lx size = %lx\n", chcr, madr, bcr); |
0300a353 | 162 | words = words_left = (bcr >> 16) * (bcr & 0xffff); |
163 | while (words_left > 0) { | |
164 | ptr = getDmaRam(madr, &words_max); | |
165 | if (ptr == INVALID_PTR) { | |
166 | log_unhandled("bad2 dma madr %x\n", madr); | |
167 | break; | |
168 | } | |
169 | words_copy = min(words_left, words_max); | |
170 | GPU_writeDataMem(ptr, words_copy); | |
171 | words_left -= words_copy; | |
172 | madr += words_copy * 4; | |
ef79bbde | 173 | } |
58ebb94c | 174 | |
0300a353 | 175 | HW_DMA2_MADR = SWAPu32(madr); |
57a757ce | 176 | |
177 | // already 32-bit word size ((size * 4) / 4) | |
58ebb94c | 178 | GPUDMA_INT(words / 4); |
ef79bbde P |
179 | return; |
180 | ||
181 | case 0x01000401: // dma chain | |
57a757ce | 182 | PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %lx addr = %lx size = %lx\n", chcr, madr, bcr); |
fae38d7a | 183 | // when not emulating walking progress, end immediately |
184 | madr_next = 0xffffff; | |
57a757ce | 185 | |
fae38d7a | 186 | do_walking = Config.GpuListWalking; |
187 | if (do_walking < 0) | |
188 | do_walking = Config.hacks.gpu_slow_list_walking; | |
189 | madr_next_p = do_walking ? &madr_next : NULL; | |
190 | ||
191 | size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff, madr_next_p); | |
b03e0caf | 192 | if ((int)size <= 0) |
193 | size = gpuDmaChainSize(madr); | |
58ebb94c | 194 | |
fae38d7a | 195 | HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY); |
196 | HW_DMA2_MADR = SWAPu32(madr_next); | |
58ebb94c | 197 | |
57a757ce | 198 | // Tekken 3 = use 1.0 only (not 1.5x) |
199 | ||
200 | // Einhander = parse linked list in pieces (todo) | |
57a757ce | 201 | // Rebel Assault 2 = parse linked list in pieces (todo) |
57a757ce | 202 | GPUDMA_INT(size); |
203 | return; | |
ef79bbde | 204 | |
ef79bbde | 205 | default: |
7df2c03c | 206 | log_unhandled("*** DMA 2 - GPU unknown *** %x addr = %x size = %x\n", chcr, madr, bcr); |
ef79bbde | 207 | break; |
ef79bbde P |
208 | } |
209 | ||
210 | HW_DMA2_CHCR &= SWAP32(~0x01000000); | |
211 | DMA_INTERRUPT(2); | |
212 | } | |
213 | ||
214 | void gpuInterrupt() { | |
fae38d7a | 215 | if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000))) |
216 | { | |
217 | u32 size, madr_next = 0xffffff; | |
218 | size = GPU_dmaChain((u32 *)psxM, HW_DMA2_MADR & 0x1fffff, &madr_next); | |
219 | HW_DMA2_MADR = SWAPu32(madr_next); | |
220 | GPUDMA_INT(size); | |
221 | return; | |
222 | } | |
ad418c19 | 223 | if (HW_DMA2_CHCR & SWAP32(0x01000000)) |
224 | { | |
225 | HW_DMA2_CHCR &= SWAP32(~0x01000000); | |
226 | DMA_INTERRUPT(2); | |
227 | } | |
adb7d7ac | 228 | HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy |
ef79bbde P |
229 | } |
230 | ||
231 | void psxDma6(u32 madr, u32 bcr, u32 chcr) { | |
0300a353 | 232 | u32 words, words_max; |
233 | u32 *mem; | |
ef79bbde | 234 | |
ef79bbde | 235 | PSXDMA_LOG("*** DMA6 OT *** %x addr = %x size = %x\n", chcr, madr, bcr); |
ef79bbde P |
236 | |
237 | if (chcr == 0x11000002) { | |
0300a353 | 238 | mem = getDmaRam(madr, &words_max); |
b012a437 | 239 | if (mem == INVALID_PTR) { |
0300a353 | 240 | log_unhandled("bad6 dma madr %x\n", madr); |
ef79bbde P |
241 | HW_DMA6_CHCR &= SWAP32(~0x01000000); |
242 | DMA_INTERRUPT(6); | |
243 | return; | |
244 | } | |
245 | ||
57a757ce | 246 | // already 32-bit size |
fc4803bd | 247 | words = bcr; |
57a757ce | 248 | |
0300a353 | 249 | while (bcr-- && mem > (u32 *)psxM) { |
ef79bbde P |
250 | *mem-- = SWAP32((madr - 4) & 0xffffff); |
251 | madr -= 4; | |
252 | } | |
adb7d7ac | 253 | *++mem = SWAP32(0xffffff); |
57a757ce | 254 | |
fc4803bd | 255 | //GPUOTCDMA_INT(size); |
256 | // halted | |
257 | psxRegs.cycle += words; | |
258 | GPUOTCDMA_INT(16); | |
57a757ce | 259 | return; |
ef79bbde | 260 | } |
ef79bbde P |
261 | else { |
262 | // Unknown option | |
7df2c03c | 263 | log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr); |
ef79bbde | 264 | } |
ef79bbde P |
265 | |
266 | HW_DMA6_CHCR &= SWAP32(~0x01000000); | |
267 | DMA_INTERRUPT(6); | |
268 | } | |
269 | ||
57a757ce | 270 | void gpuotcInterrupt() |
271 | { | |
ad418c19 | 272 | if (HW_DMA6_CHCR & SWAP32(0x01000000)) |
273 | { | |
274 | HW_DMA6_CHCR &= SWAP32(~0x01000000); | |
275 | DMA_INTERRUPT(6); | |
276 | } | |
57a757ce | 277 | } |