[pcsx_rearmed.git] / libpcsxcore / psxevents.h

#ifndef __PSXEVENTS_H__
#define __PSXEVENTS_H__

#include "psxcommon.h"

enum {
	PSXINT_SIO = 0,      // sioInterrupt
	PSXINT_CDR,          // cdrInterrupt
	PSXINT_CDREAD,       // cdrPlayReadInterrupt
	PSXINT_GPUDMA,       // gpuInterrupt
	PSXINT_MDECOUTDMA,   // mdec1Interrupt
	PSXINT_SPUDMA,       // spuInterrupt
	PSXINT_SPU_IRQ,      // spuDelayedIrq
	PSXINT_MDECINDMA,    // mdec0Interrupt
	PSXINT_GPUOTCDMA,    // gpuotcInterrupt
	PSXINT_CDRDMA,       // cdrDmaInterrupt
	PSXINT_NEWDRC_CHECK, // (none)
	PSXINT_RCNT,         // psxRcntUpdate
	PSXINT_CDRLID,       // cdrLidSeekInterrupt
	PSXINT_IRQ10,        // irq10Interrupt
	PSXINT_SPU_UPDATE,   // spuUpdate
	PSXINT_COUNT
};

#define set_event_raw_abs(e, abs) { \
	u32 abs_ = abs; \
	s32 di_ = psxRegs.next_interupt - abs_; \
	psxRegs.event_cycles[e] = abs_; \
	if (di_ > 0) { \
		/*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, psxRegs.next_interupt, abs_);*/ \
		psxRegs.next_interupt = abs_; \
	} \
}

#define set_event(e, c) do { \
	psxRegs.interrupt |= (1 << (e)); \
	psxRegs.intCycle[e].cycle = c; \
	psxRegs.intCycle[e].sCycle = psxRegs.cycle; \
	set_event_raw_abs(e, psxRegs.cycle + (c)) \
} while (0)

union psxCP0Regs_;
struct psxRegisters;

u32  schedule_timeslice(struct psxRegisters *regs);
void irq_test(union psxCP0Regs_ *cp0);
void gen_interupt(union psxCP0Regs_ *cp0);
void events_restore(void);

#endif // __PSXEVENTS_H__
Commit	Line	Data
9a0a61d2	1	#ifndef __PSXEVENTS_H__
	2	#define __PSXEVENTS_H__
	3
	4	#include "psxcommon.h"
	5
	6	enum {
	7	PSXINT_SIO = 0, // sioInterrupt
	8	PSXINT_CDR, // cdrInterrupt
	9	PSXINT_CDREAD, // cdrPlayReadInterrupt
	10	PSXINT_GPUDMA, // gpuInterrupt
	11	PSXINT_MDECOUTDMA, // mdec1Interrupt
	12	PSXINT_SPUDMA, // spuInterrupt
c2eee46b	13	PSXINT_SPU_IRQ, // spuDelayedIrq
9a0a61d2	14	PSXINT_MDECINDMA, // mdec0Interrupt
	15	PSXINT_GPUOTCDMA, // gpuotcInterrupt
	16	PSXINT_CDRDMA, // cdrDmaInterrupt
	17	PSXINT_NEWDRC_CHECK, // (none)
	18	PSXINT_RCNT, // psxRcntUpdate
	19	PSXINT_CDRLID, // cdrLidSeekInterrupt
	20	PSXINT_IRQ10, // irq10Interrupt
	21	PSXINT_SPU_UPDATE, // spuUpdate
	22	PSXINT_COUNT
	23	};
	24
9a0a61d2	25	#define set_event_raw_abs(e, abs) { \
9a0a61d2	26	u32 abs_ = abs; \
c87406ff	27	s32 di_ = psxRegs.next_interupt - abs_; \
92dc6b2f	28	psxRegs.event_cycles[e] = abs_; \
9a0a61d2	29	if (di_ > 0) { \
c87406ff	30	/printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, psxRegs.next_interupt, abs_);/ \
c87406ff	31	psxRegs.next_interupt = abs_; \
9a0a61d2	32	} \
	33	}
	34
	35	#define set_event(e, c) do { \
	36	psxRegs.interrupt \|= (1 << (e)); \
	37	psxRegs.intCycle[e].cycle = c; \
	38	psxRegs.intCycle[e].sCycle = psxRegs.cycle; \
	39	set_event_raw_abs(e, psxRegs.cycle + (c)) \
	40	} while (0)
	41
	42	union psxCP0Regs_;
c87406ff	43	struct psxRegisters;
	44
	45	u32 schedule_timeslice(struct psxRegisters *regs);
9a0a61d2	46	void irq_test(union psxCP0Regs_ *cp0);
	47	void gen_interupt(union psxCP0Regs_ *cp0);
	48	void events_restore(void);
	49
	50	#endif // __PSXEVENTS_H__