[pcsx_rearmed.git] / libpcsxcore / psxmem.c

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
* PSX memory functions.
*/

// TODO: Implement caches & cycle penalty.

#include "psxmem.h"
#include "psxmem_map.h"
#include "r3000a.h"
#include "psxhw.h"
#include "debug.h"

#include "memmap.h"

#ifdef USE_LIBRETRO_VFS
#include <streams/file_stream_transforms.h>
#endif

#ifndef MAP_ANONYMOUS
#define MAP_ANONYMOUS MAP_ANON
#endif

boolean writeok = TRUE;

#ifndef NDEBUG
#include "debug.h"
#else
void DebugCheckBP(u32 address, enum breakpoint_types type) {}
#endif

void *(*psxMapHook)(unsigned long addr, size_t size, int is_fixed,
		enum psxMapTag tag);
void (*psxUnmapHook)(void *ptr, size_t size, enum psxMapTag tag);

void *psxMap(unsigned long addr, size_t size, int is_fixed,
		enum psxMapTag tag)
{
#ifdef LIGHTREC
#ifdef MAP_FIXED_NOREPLACE
	int flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED_NOREPLACE;
#else
	int flags = MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED;
#endif
#else
	int flags = MAP_PRIVATE | MAP_ANONYMOUS;
#endif

	int try_ = 0;
	unsigned long mask;
	void *req, *ret;

retry:
	if (psxMapHook != NULL) {
		ret = psxMapHook(addr, size, 0, tag);
		if (ret == NULL)
			return NULL;
	}
	else {
		/* avoid MAP_FIXED, it overrides existing mappings.. */
		/* if (is_fixed)
			flags |= MAP_FIXED; */

		req = (void *)addr;
		ret = mmap(req, size, PROT_READ | PROT_WRITE, flags, -1, 0);
		if (ret == MAP_FAILED)
			return NULL;
	}

	if (addr != 0 && ret != (void *)addr) {
		SysMessage("psxMap: warning: wanted to map @%08x, got %p\n",
			addr, ret);

		if (is_fixed) {
			psxUnmap(ret, size, tag);
			return NULL;
		}

		if (((addr ^ (unsigned long)ret) & ~0xff000000l) && try_ < 2)
		{
			psxUnmap(ret, size, tag);

			// try to use similarly aligned memory instead
			// (recompiler needs this)
			mask = try_ ? 0xffff : 0xffffff;
			addr = ((unsigned long)ret + mask) & ~mask;
			try_++;
			goto retry;
		}
	}

	return ret;
}

void psxUnmap(void *ptr, size_t size, enum psxMapTag tag)
{
	if (psxUnmapHook != NULL) {
		psxUnmapHook(ptr, size, tag);
		return;
	}

	if (ptr)
		munmap(ptr, size);
}

s8 *psxM = NULL; // Kernel & User Memory (2 Meg)
s8 *psxP = NULL; // Parallel Port (64K)
s8 *psxR = NULL; // BIOS ROM (512K)
s8 *psxH = NULL; // Scratch Pad (1K) & Hardware Registers (8K)

u8 **psxMemWLUT = NULL;
u8 **psxMemRLUT = NULL;

/*  Playstation Memory Map (from Playstation doc by Joshua Walker)
0x0000_0000-0x0000_ffff		Kernel (64K)
0x0001_0000-0x001f_ffff		User Memory (1.9 Meg)

0x1f00_0000-0x1f00_ffff		Parallel Port (64K)

0x1f80_0000-0x1f80_03ff		Scratch Pad (1024 bytes)

0x1f80_1000-0x1f80_2fff		Hardware Registers (8K)

0x1fc0_0000-0x1fc7_ffff		BIOS (512K)

0x8000_0000-0x801f_ffff		Kernel and User Memory Mirror (2 Meg) Cached
0x9fc0_0000-0x9fc7_ffff		BIOS Mirror (512K) Cached

0xa000_0000-0xa01f_ffff		Kernel and User Memory Mirror (2 Meg) Uncached
0xbfc0_0000-0xbfc7_ffff		BIOS Mirror (512K) Uncached
*/

int psxMemInit() {
	int i;

	psxMemRLUT = (u8 **)malloc(0x10000 * sizeof(void *));
	psxMemWLUT = (u8 **)malloc(0x10000 * sizeof(void *));
	memset(psxMemRLUT, 0, 0x10000 * sizeof(void *));
	memset(psxMemWLUT, 0, 0x10000 * sizeof(void *));

#ifdef LIGHTREC
	psxM = psxMap(0x30000000, 0x00210000, 1, MAP_TAG_RAM);
	if (psxM == NULL)
		psxM = psxMap(0x70000000, 0x00210000, 1, MAP_TAG_RAM);

#else
	psxM = psxMap(0x80000000, 0x00210000, 1, MAP_TAG_RAM);
#endif
#ifndef RAM_FIXED
	if (psxM == NULL)
		psxM = psxMap(0x77000000, 0x00210000, 0, MAP_TAG_RAM);
#endif
	if (psxM == NULL) {
		SysMessage(_("mapping main RAM failed"));
		return -1;
	}

	psxP = &psxM[0x200000];
#ifdef LIGHTREC
	psxH = psxMap(0x4f800000, 0x10000, 0, MAP_TAG_OTHER);
	if (psxH == NULL)
		psxH = psxMap(0x8f800000, 0x10000, 0, MAP_TAG_OTHER);

	psxR = psxMap(0x4fc00000, 0x80000, 0, MAP_TAG_OTHER);
	if (psxR == NULL)
		psxR = psxMap(0x8fc00000, 0x80000, 0, MAP_TAG_OTHER);
#else
	psxH = psxMap(0x1f800000, 0x10000, 0, MAP_TAG_OTHER);
	psxR = psxMap(0x1fc00000, 0x80000, 0, MAP_TAG_OTHER);
#endif

	if (psxMemRLUT == NULL || psxMemWLUT == NULL || 
	    psxR == NULL || psxP == NULL || psxH == NULL) {
		SysMessage(_("Error allocating memory!"));
		psxMemShutdown();
		return -1;
	}

// MemR
	for (i = 0; i < 0x80; i++) psxMemRLUT[i + 0x0000] = (u8 *)&psxM[(i & 0x1f) << 16];

	memcpy(psxMemRLUT + 0x8000, psxMemRLUT, 0x80 * sizeof(void *));
	memcpy(psxMemRLUT + 0xa000, psxMemRLUT, 0x80 * sizeof(void *));

	psxMemRLUT[0x1f00] = (u8 *)psxP;
	psxMemRLUT[0x1f80] = (u8 *)psxH;

	for (i = 0; i < 0x08; i++) psxMemRLUT[i + 0x1fc0] = (u8 *)&psxR[i << 16];

	memcpy(psxMemRLUT + 0x9fc0, psxMemRLUT + 0x1fc0, 0x08 * sizeof(void *));
	memcpy(psxMemRLUT + 0xbfc0, psxMemRLUT + 0x1fc0, 0x08 * sizeof(void *));

// MemW
	for (i = 0; i < 0x80; i++) psxMemWLUT[i + 0x0000] = (u8 *)&psxM[(i & 0x1f) << 16];

	memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
	memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));

	psxMemWLUT[0x1f00] = (u8 *)psxP;
	psxMemWLUT[0x1f80] = (u8 *)psxH;

	return 0;
}

void psxMemReset() {
	FILE *f = NULL;
	char bios[1024];

	memset(psxM, 0, 0x00200000);
	memset(psxP, 0xff, 0x00010000);

	Config.HLE = TRUE;

	if (strcmp(Config.Bios, "HLE") != 0) {
		sprintf(bios, "%s/%s", Config.BiosDir, Config.Bios);
		f = fopen(bios, "rb");

		if (f == NULL) {
			SysMessage(_("Could not open BIOS:\"%s\". Enabling HLE Bios!\n"), bios);
			memset(psxR, 0, 0x80000);
		} else {
			if (fread(psxR, 1, 0x80000, f) == 0x80000) {
				Config.HLE = FALSE;
			} else {
				SysMessage(_("The selected BIOS:\"%s\" is of wrong size. Enabling HLE Bios!\n"), bios);
			}
			fclose(f);
		}
	}
}

void psxMemShutdown() {
	psxUnmap(psxM, 0x00210000, MAP_TAG_RAM); psxM = NULL;
	psxUnmap(psxH, 0x10000, MAP_TAG_OTHER); psxH = NULL;
	psxUnmap(psxR, 0x80000, MAP_TAG_OTHER); psxR = NULL;

	free(psxMemRLUT); psxMemRLUT = NULL;
	free(psxMemWLUT); psxMemWLUT = NULL;
}

u8 psxMemRead8(u32 mem) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			return psxHu8(mem);
		else
			return psxHwRead8(mem);
	} else {
		p = (char *)(psxMemRLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, R1);
			return *(u8 *)(p + (mem & 0xffff));
		} else {
#ifdef PSXMEM_LOG
			PSXMEM_LOG("err lb %8.8lx\n", mem);
#endif
			return 0xFF;
		}
	}
}

u16 psxMemRead16(u32 mem) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			return psxHu16(mem);
		else
			return psxHwRead16(mem);
	} else {
		p = (char *)(psxMemRLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, R2);
			return SWAPu16(*(u16 *)(p + (mem & 0xffff)));
		} else {
#ifdef PSXMEM_LOG
			PSXMEM_LOG("err lh %8.8lx\n", mem);
#endif
			return 0xFFFF;
		}
	}
}

u32 psxMemRead32(u32 mem) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			return psxHu32(mem);
		else
			return psxHwRead32(mem);
	} else {
		p = (char *)(psxMemRLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, R4);
			return SWAPu32(*(u32 *)(p + (mem & 0xffff)));
		} else {
#ifdef PSXMEM_LOG
			if (writeok) { PSXMEM_LOG("err lw %8.8lx\n", mem); }
#endif
			return 0xFFFFFFFF;
		}
	}
}

void psxMemWrite8(u32 mem, u8 value) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			psxHu8(mem) = value;
		else
			psxHwWrite8(mem, value);
	} else {
		p = (char *)(psxMemWLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, W1);
			*(u8 *)(p + (mem & 0xffff)) = value;
#ifdef PSXREC
			psxCpu->Clear((mem & (~3)), 1);
#endif
		} else {
#ifdef PSXMEM_LOG
			PSXMEM_LOG("err sb %8.8lx\n", mem);
#endif
		}
	}
}

void psxMemWrite16(u32 mem, u16 value) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			psxHu16ref(mem) = SWAPu16(value);
		else
			psxHwWrite16(mem, value);
	} else {
		p = (char *)(psxMemWLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, W2);
			*(u16 *)(p + (mem & 0xffff)) = SWAPu16(value);
#ifdef PSXREC
			psxCpu->Clear((mem & (~3)), 1);
#endif
		} else {
#ifdef PSXMEM_LOG
			PSXMEM_LOG("err sh %8.8lx\n", mem);
#endif
		}
	}
}

void psxMemWrite32(u32 mem, u32 value) {
	char *p;
#if defined(ICACHE_EMULATION)
	/*  Stores in PS1 code during cache isolation invalidate cachelines.
	 * It is assumed that cache-flush routines write to the lowest 4KB of
	 * address space for Icache, or 1KB for Dcache/scratchpad.
	 *  Originally, stores had to check 'writeok' in psxRegs struct before
	 * writing to RAM. To eliminate this necessity, we could simply patch the
	 * BIOS 0x44 FlushCache() A0 jumptable entry. Unfortunately, this won't
	 * work for some games that use less-buggy non-BIOS cache-flush routines
	 * like '007 Tomorrow Never Dies', often provided by SN-systems, the PS1
	 * toolchain provider.
	 *  Instead, we backup the lowest 64KB PS1 RAM when the cache is isolated.
	 * All stores write to RAM regardless of cache state. Thus, cache-flush
	 * routines temporarily trash the lowest 4KB of PS1 RAM. Fortunately, they
	 * ran in a 'critical section' with interrupts disabled, so there's little
	 * worry of PS1 code ever reading the trashed contents.
	 *  We point the relevant portions of psxMemRLUT[] to the 64KB backup while
	 * cache is isolated. This is in case the dynarec needs to recompile some
	 * code during isolation. As long as it reads code using psxMemRLUT[] ptrs,
	 * it should never see trashed RAM contents.
	 *
	 * -senquack, mips dynarec team, 2017
	 */
	static u32 mem_bak[0x10000/4];
#endif
	u32 t;
	u32 m = mem & 0xffff;
//	if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n");
	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if (m < 0x400)
			psxHu32ref(mem) = SWAPu32(value);
		else
			psxHwWrite32(mem, value);
	} else {
		p = (char *)(psxMemWLUT[t]);
		if (p != NULL) {
			if (Config.Debug)
				DebugCheckBP((mem & 0xffffff) | 0x80000000, W4);
			*(u32 *)(p + (mem & 0xffff)) = SWAPu32(value);
#ifdef PSXREC
			psxCpu->Clear(mem, 1);
#endif
		} else {
			if (mem != 0xfffe0130) {
#ifdef PSXREC
				if (!writeok)
					psxCpu->Clear(mem, 1);
#endif

#ifdef PSXMEM_LOG
				if (writeok) { PSXMEM_LOG("err sw %8.8lx\n", mem); }
#endif
			} else {
				int i;

				switch (value) {
					case 0x800: case 0x804:
						if (writeok == FALSE) break;
						writeok = FALSE;
						memset(psxMemWLUT + 0x0000, 0, 0x80 * sizeof(void *));
						memset(psxMemWLUT + 0x8000, 0, 0x80 * sizeof(void *));
						memset(psxMemWLUT + 0xa000, 0, 0x80 * sizeof(void *));
#ifdef ICACHE_EMULATION
						/* Cache is now isolated, pending cache-flush sequence:
						*  Backup lower 64KB of PS1 RAM, adjust psxMemRLUT[].
						*/
						memcpy((void*)mem_bak, (void*)psxM, sizeof(mem_bak));
						psxMemRLUT[0x0000] = psxMemRLUT[0x0020] = psxMemRLUT[0x0040] = psxMemRLUT[0x0060] = (u8 *)mem_bak;
						psxMemRLUT[0x8000] = psxMemRLUT[0x8020] = psxMemRLUT[0x8040] = psxMemRLUT[0x8060] = (u8 *)mem_bak;
						psxMemRLUT[0xa000] = psxMemRLUT[0xa020] = psxMemRLUT[0xa040] = psxMemRLUT[0xa060] = (u8 *)mem_bak;
						psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_ISOLATED, NULL);
#endif
						break;
					case 0x00: case 0x1e988:
						if (writeok == TRUE) break;
						writeok = TRUE;
						for (i = 0; i < 0x80; i++) psxMemWLUT[i + 0x0000] = (void *)&psxM[(i & 0x1f) << 16];
						memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
						memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));
#ifdef ICACHE_EMULATION
						/* Cache is now unisolated:
						* Restore lower 64KB RAM contents and psxMemRLUT[].
						*/
						memcpy((void*)psxM, (void*)mem_bak, sizeof(mem_bak));
						psxMemRLUT[0x0000] = psxMemRLUT[0x0020] = psxMemRLUT[0x0040] = psxMemRLUT[0x0060] = (u8 *)psxM;
						psxMemRLUT[0x8000] = psxMemRLUT[0x8020] = psxMemRLUT[0x8040] = psxMemRLUT[0x8060] = (u8 *)psxM;
						psxMemRLUT[0xa000] = psxMemRLUT[0xa020] = psxMemRLUT[0xa040] = psxMemRLUT[0xa060] = (u8 *)psxM;
						/* Dynarecs might take this opportunity to flush their code cache */
						psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
#endif
						break;
					default:
#ifdef PSXMEM_LOG
						PSXMEM_LOG("unk %8.8lx = %x\n", mem, value);
#endif
						break;
				}
			}
		}
	}
}

void *psxMemPointer(u32 mem) {
	char *p;
	u32 t;

	t = mem >> 16;
	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
		if ((mem & 0xffff) < 0x400)
			return (void *)&psxH[mem];
		else
			return NULL;
	} else {
		p = (char *)(psxMemWLUT[t]);
		if (p != NULL) {
			return (void *)(p + (mem & 0xffff));
		}
		return NULL;
	}
}
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* PSX memory functions.
	22	*/
	23
	24	// TODO: Implement caches & cycle penalty.
	25
	26	#include "psxmem.h"
87e5b45f	27	#include "psxmem_map.h"
ef79bbde P	28	#include "r3000a.h"
ef79bbde P	29	#include "psxhw.h"
fc8145b7	30	#include "debug.h"
ce0e7ac9	31
ce0e7ac9	32	#include "memmap.h"
ef79bbde	33
226a5691	34	#ifdef USE_LIBRETRO_VFS
	35	#include <streams/file_stream_transforms.h>
	36	#endif
	37
ef79bbde P	38	#ifndef MAP_ANONYMOUS
	39	#define MAP_ANONYMOUS MAP_ANON
	40	#endif
	41
7a811716	42	boolean writeok = TRUE;
7a811716	43
9361a5aa EC	44	#ifndef NDEBUG
	45	#include "debug.h"
	46	#else
11a43034	47	void DebugCheckBP(u32 address, enum breakpoint_types type) {}
	48	#endif
	49
87e5b45f	50	void (psxMapHook)(unsigned long addr, size_t size, int is_fixed,
	51	enum psxMapTag tag);
	52	void (psxUnmapHook)(void ptr, size_t size, enum psxMapTag tag);
	53
	54	void *psxMap(unsigned long addr, size_t size, int is_fixed,
	55	enum psxMapTag tag)
	56	{
a62012a7	57	#ifdef LIGHTREC
f12a6e13 ZC	58	#ifdef MAP_FIXED_NOREPLACE
	59	int flags = MAP_PRIVATE \| MAP_ANONYMOUS \| MAP_FIXED_NOREPLACE;
	60	#else
38c19eff	61	int flags = MAP_PRIVATE \| MAP_ANONYMOUS \| MAP_FIXED;
f12a6e13	62	#endif
a62012a7 T	63	#else
	64	int flags = MAP_PRIVATE \| MAP_ANONYMOUS;
	65	#endif
	66
5644b26c	67	int try_ = 0;
b0dd9956	68	unsigned long mask;
87e5b45f	69	void req, ret;
87e5b45f	70
b0dd9956	71	retry:
b0dd9956	72	if (psxMapHook != NULL) {
85f23982	73	ret = psxMapHook(addr, size, 0, tag);
	74	if (ret == NULL)
	75	return NULL;
	76	}
	77	else {
	78	/* avoid MAP_FIXED, it overrides existing mappings.. */
	79	/* if (is_fixed)
	80	flags \|= MAP_FIXED; */
	81
	82	req = (void *)addr;
	83	ret = mmap(req, size, PROT_READ \| PROT_WRITE, flags, -1, 0);
	84	if (ret == MAP_FAILED)
	85	return NULL;
b0dd9956	86	}
87e5b45f	87
b0dd9956	88	if (addr != 0 && ret != (void *)addr) {
	89	SysMessage("psxMap: warning: wanted to map @%08x, got %p\n",
	90	addr, ret);
	91
0069615f	92	if (is_fixed) {
	93	psxUnmap(ret, size, tag);
	94	return NULL;
	95	}
	96
5644b26c	97	if (((addr ^ (unsigned long)ret) & ~0xff000000l) && try_ < 2)
b0dd9956	98	{
	99	psxUnmap(ret, size, tag);
	100
	101	// try to use similarly aligned memory instead
	102	// (recompiler needs this)
5644b26c	103	mask = try_ ? 0xffff : 0xffffff;
	104	addr = ((unsigned long)ret + mask) & ~mask;
	105	try_++;
b0dd9956	106	goto retry;
	107	}
	108	}
87e5b45f	109
	110	return ret;
	111	}
	112
	113	void psxUnmap(void *ptr, size_t size, enum psxMapTag tag)
	114	{
	115	if (psxUnmapHook != NULL) {
	116	psxUnmapHook(ptr, size, tag);
	117	return;
	118	}
	119
88901dd2	120	if (ptr)
88901dd2	121	munmap(ptr, size);
87e5b45f	122	}
87e5b45f	123
ef79bbde P	124	s8 *psxM = NULL; // Kernel & User Memory (2 Meg)
	125	s8 *psxP = NULL; // Parallel Port (64K)
	126	s8 *psxR = NULL; // BIOS ROM (512K)
	127	s8 *psxH = NULL; // Scratch Pad (1K) & Hardware Registers (8K)
	128
	129	u8 **psxMemWLUT = NULL;
	130	u8 **psxMemRLUT = NULL;
	131
	132	/* Playstation Memory Map (from Playstation doc by Joshua Walker)
	133	0x0000_0000-0x0000_ffff Kernel (64K)
	134	0x0001_0000-0x001f_ffff User Memory (1.9 Meg)
	135
	136	0x1f00_0000-0x1f00_ffff Parallel Port (64K)
	137
	138	0x1f80_0000-0x1f80_03ff Scratch Pad (1024 bytes)
	139
	140	0x1f80_1000-0x1f80_2fff Hardware Registers (8K)
	141
	142	0x1fc0_0000-0x1fc7_ffff BIOS (512K)
	143
	144	0x8000_0000-0x801f_ffff Kernel and User Memory Mirror (2 Meg) Cached
	145	0x9fc0_0000-0x9fc7_ffff BIOS Mirror (512K) Cached
	146
	147	0xa000_0000-0xa01f_ffff Kernel and User Memory Mirror (2 Meg) Uncached
	148	0xbfc0_0000-0xbfc7_ffff BIOS Mirror (512K) Uncached
	149	*/
	150
	151	int psxMemInit() {
	152	int i;
	153
	154	psxMemRLUT = (u8 *)malloc(0x10000 sizeof(void *));
	155	psxMemWLUT = (u8 *)malloc(0x10000 sizeof(void *));
	156	memset(psxMemRLUT, 0, 0x10000 * sizeof(void *));
	157	memset(psxMemWLUT, 0, 0x10000 * sizeof(void *));
	158
a62012a7	159	#ifdef LIGHTREC
38c19eff	160	psxM = psxMap(0x30000000, 0x00210000, 1, MAP_TAG_RAM);
f12a6e13 ZC	161	if (psxM == NULL)
	162	psxM = psxMap(0x70000000, 0x00210000, 1, MAP_TAG_RAM);
	163
a62012a7 T	164	#else
	165	psxM = psxMap(0x80000000, 0x00210000, 1, MAP_TAG_RAM);
	166	#endif
a327ad27	167	#ifndef RAM_FIXED
a4874585	168	if (psxM == NULL)
f23d3386	169	psxM = psxMap(0x77000000, 0x00210000, 0, MAP_TAG_RAM);
a327ad27	170	#endif
87e5b45f	171	if (psxM == NULL) {
a327ad27	172	SysMessage(_("mapping main RAM failed"));
	173	return -1;
	174	}
ef79bbde P	175
ef79bbde P	176	psxP = &psxM[0x200000];
a62012a7	177	#ifdef LIGHTREC
38c19eff	178	psxH = psxMap(0x4f800000, 0x10000, 0, MAP_TAG_OTHER);
f12a6e13 ZC	179	if (psxH == NULL)
	180	psxH = psxMap(0x8f800000, 0x10000, 0, MAP_TAG_OTHER);
	181
38c19eff	182	psxR = psxMap(0x4fc00000, 0x80000, 0, MAP_TAG_OTHER);
f12a6e13 ZC	183	if (psxR == NULL)
f12a6e13 ZC	184	psxR = psxMap(0x8fc00000, 0x80000, 0, MAP_TAG_OTHER);
a62012a7 T	185	#else
	186	psxH = psxMap(0x1f800000, 0x10000, 0, MAP_TAG_OTHER);
	187	psxR = psxMap(0x1fc00000, 0x80000, 0, MAP_TAG_OTHER);
	188	#endif
ef79bbde P	189
ef79bbde P	190	if (psxMemRLUT == NULL \|\| psxMemWLUT == NULL \|\|
6d760c92	191	psxR == NULL \|\| psxP == NULL \|\| psxH == NULL) {
ef79bbde	192	SysMessage(_("Error allocating memory!"));
88901dd2	193	psxMemShutdown();
ef79bbde P	194	return -1;
	195	}
	196
	197	// MemR
	198	for (i = 0; i < 0x80; i++) psxMemRLUT[i + 0x0000] = (u8 *)&psxM[(i & 0x1f) << 16];
	199
	200	memcpy(psxMemRLUT + 0x8000, psxMemRLUT, 0x80 * sizeof(void *));
	201	memcpy(psxMemRLUT + 0xa000, psxMemRLUT, 0x80 * sizeof(void *));
	202
	203	psxMemRLUT[0x1f00] = (u8 *)psxP;
	204	psxMemRLUT[0x1f80] = (u8 *)psxH;
	205
	206	for (i = 0; i < 0x08; i++) psxMemRLUT[i + 0x1fc0] = (u8 *)&psxR[i << 16];
	207
	208	memcpy(psxMemRLUT + 0x9fc0, psxMemRLUT + 0x1fc0, 0x08 * sizeof(void *));
	209	memcpy(psxMemRLUT + 0xbfc0, psxMemRLUT + 0x1fc0, 0x08 * sizeof(void *));
	210
	211	// MemW
	212	for (i = 0; i < 0x80; i++) psxMemWLUT[i + 0x0000] = (u8 *)&psxM[(i & 0x1f) << 16];
	213
	214	memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
	215	memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));
	216
	217	psxMemWLUT[0x1f00] = (u8 *)psxP;
	218	psxMemWLUT[0x1f80] = (u8 *)psxH;
	219
	220	return 0;
	221	}
	222
	223	void psxMemReset() {
	224	FILE *f = NULL;
	225	char bios[1024];
	226
	227	memset(psxM, 0, 0x00200000);
23643ee7	228	memset(psxP, 0xff, 0x00010000);
ef79bbde	229
9361a5aa EC	230	Config.HLE = TRUE;
9361a5aa EC	231
ef79bbde P	232	if (strcmp(Config.Bios, "HLE") != 0) {
ef79bbde P	233	sprintf(bios, "%s/%s", Config.BiosDir, Config.Bios);
226a5691	234	f = fopen(bios, "rb");
ef79bbde P	235
	236	if (f == NULL) {
	237	SysMessage(_("Could not open BIOS:\"%s\". Enabling HLE Bios!\n"), bios);
	238	memset(psxR, 0, 0x80000);
ef79bbde	239	} else {
9361a5aa EC	240	if (fread(psxR, 1, 0x80000, f) == 0x80000) {
	241	Config.HLE = FALSE;
	242	} else {
	243	SysMessage(_("The selected BIOS:\"%s\" is of wrong size. Enabling HLE Bios!\n"), bios);
	244	}
ef79bbde	245	fclose(f);
ef79bbde	246	}
9361a5aa	247	}
ef79bbde P	248	}
	249
	250	void psxMemShutdown() {
88901dd2	251	psxUnmap(psxM, 0x00210000, MAP_TAG_RAM); psxM = NULL;
	252	psxUnmap(psxH, 0x10000, MAP_TAG_OTHER); psxH = NULL;
	253	psxUnmap(psxR, 0x80000, MAP_TAG_OTHER); psxR = NULL;
ef79bbde	254
88901dd2	255	free(psxMemRLUT); psxMemRLUT = NULL;
88901dd2	256	free(psxMemWLUT); psxMemWLUT = NULL;
ef79bbde P	257	}
ef79bbde P	258
ef79bbde P	259	u8 psxMemRead8(u32 mem) {
	260	char *p;
	261	u32 t;
	262
	263	t = mem >> 16;
9dd7d179	264	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	265	if ((mem & 0xffff) < 0x400)
ef79bbde P	266	return psxHu8(mem);
	267	else
	268	return psxHwRead8(mem);
	269	} else {
	270	p = (char *)(psxMemRLUT[t]);
	271	if (p != NULL) {
	272	if (Config.Debug)
	273	DebugCheckBP((mem & 0xffffff) \| 0x80000000, R1);
	274	return (u8 )(p + (mem & 0xffff));
	275	} else {
	276	#ifdef PSXMEM_LOG
	277	PSXMEM_LOG("err lb %8.8lx\n", mem);
	278	#endif
e86be808	279	return 0xFF;
ef79bbde P	280	}
	281	}
	282	}
	283
	284	u16 psxMemRead16(u32 mem) {
	285	char *p;
	286	u32 t;
	287
	288	t = mem >> 16;
9dd7d179	289	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	290	if ((mem & 0xffff) < 0x400)
ef79bbde P	291	return psxHu16(mem);
	292	else
	293	return psxHwRead16(mem);
	294	} else {
	295	p = (char *)(psxMemRLUT[t]);
	296	if (p != NULL) {
	297	if (Config.Debug)
	298	DebugCheckBP((mem & 0xffffff) \| 0x80000000, R2);
	299	return SWAPu16((u16 )(p + (mem & 0xffff)));
	300	} else {
	301	#ifdef PSXMEM_LOG
	302	PSXMEM_LOG("err lh %8.8lx\n", mem);
	303	#endif
e86be808	304	return 0xFFFF;
ef79bbde P	305	}
	306	}
	307	}
	308
	309	u32 psxMemRead32(u32 mem) {
	310	char *p;
	311	u32 t;
	312
	313	t = mem >> 16;
9dd7d179	314	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	315	if ((mem & 0xffff) < 0x400)
ef79bbde P	316	return psxHu32(mem);
	317	else
	318	return psxHwRead32(mem);
	319	} else {
	320	p = (char *)(psxMemRLUT[t]);
	321	if (p != NULL) {
	322	if (Config.Debug)
	323	DebugCheckBP((mem & 0xffffff) \| 0x80000000, R4);
	324	return SWAPu32((u32 )(p + (mem & 0xffff)));
	325	} else {
	326	#ifdef PSXMEM_LOG
	327	if (writeok) { PSXMEM_LOG("err lw %8.8lx\n", mem); }
	328	#endif
e86be808	329	return 0xFFFFFFFF;
ef79bbde P	330	}
	331	}
	332	}
	333
	334	void psxMemWrite8(u32 mem, u8 value) {
	335	char *p;
	336	u32 t;
	337
	338	t = mem >> 16;
9dd7d179	339	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	340	if ((mem & 0xffff) < 0x400)
ef79bbde P	341	psxHu8(mem) = value;
	342	else
	343	psxHwWrite8(mem, value);
	344	} else {
	345	p = (char *)(psxMemWLUT[t]);
	346	if (p != NULL) {
	347	if (Config.Debug)
	348	DebugCheckBP((mem & 0xffffff) \| 0x80000000, W1);
	349	(u8 )(p + (mem & 0xffff)) = value;
	350	#ifdef PSXREC
	351	psxCpu->Clear((mem & (~3)), 1);
	352	#endif
	353	} else {
	354	#ifdef PSXMEM_LOG
	355	PSXMEM_LOG("err sb %8.8lx\n", mem);
	356	#endif
	357	}
	358	}
	359	}
	360
	361	void psxMemWrite16(u32 mem, u16 value) {
	362	char *p;
	363	u32 t;
	364
	365	t = mem >> 16;
9dd7d179	366	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	367	if ((mem & 0xffff) < 0x400)
ef79bbde P	368	psxHu16ref(mem) = SWAPu16(value);
	369	else
	370	psxHwWrite16(mem, value);
	371	} else {
	372	p = (char *)(psxMemWLUT[t]);
	373	if (p != NULL) {
	374	if (Config.Debug)
	375	DebugCheckBP((mem & 0xffffff) \| 0x80000000, W2);
	376	(u16 )(p + (mem & 0xffff)) = SWAPu16(value);
	377	#ifdef PSXREC
3e31e934	378	psxCpu->Clear((mem & (~3)), 1);
ef79bbde P	379	#endif
	380	} else {
	381	#ifdef PSXMEM_LOG
	382	PSXMEM_LOG("err sh %8.8lx\n", mem);
	383	#endif
	384	}
	385	}
	386	}
	387
	388	void psxMemWrite32(u32 mem, u32 value) {
	389	char *p;
7a811716	390	#if defined(ICACHE_EMULATION)
	391	/* Stores in PS1 code during cache isolation invalidate cachelines.
	392	* It is assumed that cache-flush routines write to the lowest 4KB of
	393	* address space for Icache, or 1KB for Dcache/scratchpad.
	394	* Originally, stores had to check 'writeok' in psxRegs struct before
	395	* writing to RAM. To eliminate this necessity, we could simply patch the
	396	* BIOS 0x44 FlushCache() A0 jumptable entry. Unfortunately, this won't
	397	* work for some games that use less-buggy non-BIOS cache-flush routines
	398	* like '007 Tomorrow Never Dies', often provided by SN-systems, the PS1
	399	* toolchain provider.
	400	* Instead, we backup the lowest 64KB PS1 RAM when the cache is isolated.
	401	* All stores write to RAM regardless of cache state. Thus, cache-flush
	402	* routines temporarily trash the lowest 4KB of PS1 RAM. Fortunately, they
	403	* ran in a 'critical section' with interrupts disabled, so there's little
	404	* worry of PS1 code ever reading the trashed contents.
	405	* We point the relevant portions of psxMemRLUT[] to the 64KB backup while
	406	* cache is isolated. This is in case the dynarec needs to recompile some
	407	* code during isolation. As long as it reads code using psxMemRLUT[] ptrs,
	408	* it should never see trashed RAM contents.
	409	*
	410	* -senquack, mips dynarec team, 2017
	411	*/
	412	static u32 mem_bak[0x10000/4];
	413	#endif
ef79bbde	414	u32 t;
7a811716	415	u32 m = mem & 0xffff;
ef79bbde P	416	// if ((mem&0x1fffff) == 0x71E18 \|\| value == 0x48088800) SysPrintf("t2fix!!\n");
ef79bbde P	417	t = mem >> 16;
9dd7d179	418	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
7a811716	419	if (m < 0x400)
ef79bbde P	420	psxHu32ref(mem) = SWAPu32(value);
	421	else
	422	psxHwWrite32(mem, value);
	423	} else {
	424	p = (char *)(psxMemWLUT[t]);
	425	if (p != NULL) {
	426	if (Config.Debug)
	427	DebugCheckBP((mem & 0xffffff) \| 0x80000000, W4);
	428	(u32 )(p + (mem & 0xffff)) = SWAPu32(value);
	429	#ifdef PSXREC
	430	psxCpu->Clear(mem, 1);
	431	#endif
	432	} else {
	433	if (mem != 0xfffe0130) {
	434	#ifdef PSXREC
	435	if (!writeok)
	436	psxCpu->Clear(mem, 1);
	437	#endif
	438
	439	#ifdef PSXMEM_LOG
	440	if (writeok) { PSXMEM_LOG("err sw %8.8lx\n", mem); }
	441	#endif
	442	} else {
	443	int i;
	444
	445	switch (value) {
	446	case 0x800: case 0x804:
7a811716	447	if (writeok == FALSE) break;
7a811716	448	writeok = FALSE;
ef79bbde P	449	memset(psxMemWLUT + 0x0000, 0, 0x80 * sizeof(void *));
	450	memset(psxMemWLUT + 0x8000, 0, 0x80 * sizeof(void *));
	451	memset(psxMemWLUT + 0xa000, 0, 0x80 * sizeof(void *));
7a811716	452	#ifdef ICACHE_EMULATION
	453	/* Cache is now isolated, pending cache-flush sequence:
	454	* Backup lower 64KB of PS1 RAM, adjust psxMemRLUT[].
	455	*/
	456	memcpy((void)mem_bak, (void)psxM, sizeof(mem_bak));
	457	psxMemRLUT[0x0000] = psxMemRLUT[0x0020] = psxMemRLUT[0x0040] = psxMemRLUT[0x0060] = (u8 *)mem_bak;
	458	psxMemRLUT[0x8000] = psxMemRLUT[0x8020] = psxMemRLUT[0x8040] = psxMemRLUT[0x8060] = (u8 *)mem_bak;
	459	psxMemRLUT[0xa000] = psxMemRLUT[0xa020] = psxMemRLUT[0xa040] = psxMemRLUT[0xa060] = (u8 *)mem_bak;
	460	psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_ISOLATED, NULL);
	461	#endif
ef79bbde P	462	break;
ef79bbde P	463	case 0x00: case 0x1e988:
7a811716	464	if (writeok == TRUE) break;
7a811716	465	writeok = TRUE;
ef79bbde P	466	for (i = 0; i < 0x80; i++) psxMemWLUT[i + 0x0000] = (void *)&psxM[(i & 0x1f) << 16];
	467	memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
	468	memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));
7a811716	469	#ifdef ICACHE_EMULATION
	470	/* Cache is now unisolated:
	471	* Restore lower 64KB RAM contents and psxMemRLUT[].
	472	*/
	473	memcpy((void)psxM, (void)mem_bak, sizeof(mem_bak));
	474	psxMemRLUT[0x0000] = psxMemRLUT[0x0020] = psxMemRLUT[0x0040] = psxMemRLUT[0x0060] = (u8 *)psxM;
	475	psxMemRLUT[0x8000] = psxMemRLUT[0x8020] = psxMemRLUT[0x8040] = psxMemRLUT[0x8060] = (u8 *)psxM;
	476	psxMemRLUT[0xa000] = psxMemRLUT[0xa020] = psxMemRLUT[0xa040] = psxMemRLUT[0xa060] = (u8 *)psxM;
	477	/* Dynarecs might take this opportunity to flush their code cache */
	478	psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
	479	#endif
ef79bbde P	480	break;
	481	default:
	482	#ifdef PSXMEM_LOG
	483	PSXMEM_LOG("unk %8.8lx = %x\n", mem, value);
	484	#endif
	485	break;
	486	}
	487	}
	488	}
	489	}
	490	}
	491
	492	void *psxMemPointer(u32 mem) {
	493	char *p;
	494	u32 t;
	495
	496	t = mem >> 16;
9dd7d179	497	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
9dd7d179	498	if ((mem & 0xffff) < 0x400)
ef79bbde P	499	return (void *)&psxH[mem];
	500	else
	501	return NULL;
	502	} else {
	503	p = (char *)(psxMemWLUT[t]);
	504	if (p != NULL) {
	505	return (void *)(p + (mem & 0xffff));
	506	}
	507	return NULL;
	508	}
	509	}