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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * R3000A CPU functions. | |
22 | */ | |
23 | ||
24 | #include "r3000a.h" | |
25 | #include "cdrom.h" | |
26 | #include "mdec.h" | |
27 | #include "gte.h" | |
28 | ||
29 | R3000Acpu *psxCpu = NULL; | |
1a32b0f8 | 30 | #ifndef NEW_DYNAREC |
93c9e42a | 31 | psxRegisters psxRegs; |
1a32b0f8 | 32 | #endif |
ef79bbde P |
33 | |
34 | int psxInit() { | |
202b29d4 | 35 | SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__); |
ef79bbde | 36 | |
87cc59de | 37 | #if defined(NEW_DYNAREC) || defined(LIGHTREC) |
ef79bbde P |
38 | if (Config.Cpu == CPU_INTERPRETER) { |
39 | psxCpu = &psxInt; | |
40 | } else psxCpu = &psxRec; | |
41 | #else | |
42 | psxCpu = &psxInt; | |
43 | #endif | |
44 | ||
45 | Log = 0; | |
46 | ||
47 | if (psxMemInit() == -1) return -1; | |
48 | ||
49 | return psxCpu->Init(); | |
50 | } | |
51 | ||
52 | void psxReset() { | |
ef79bbde P |
53 | psxMemReset(); |
54 | ||
76e889bc | 55 | memset(&psxRegs, 0x00, sizeof(psxRegs)); |
7a811716 | 56 | writeok = TRUE; |
ef79bbde P |
57 | psxRegs.pc = 0xbfc00000; // Start in bootstrap |
58 | ||
59 | psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1 | |
60 | psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A | |
61 | ||
c24732c0 | 62 | psxCpu->Reset(); |
63 | ||
ef79bbde P |
64 | psxHwReset(); |
65 | psxBiosInit(); | |
66 | ||
67 | if (!Config.HLE) | |
68 | psxExecuteBios(); | |
69 | ||
70 | #ifdef EMU_LOG | |
71 | EMU_LOG("*BIOS END*\n"); | |
72 | #endif | |
73 | Log = 0; | |
74 | } | |
75 | ||
76 | void psxShutdown() { | |
77 | psxMemShutdown(); | |
78 | psxBiosShutdown(); | |
79 | ||
80 | psxCpu->Shutdown(); | |
81 | } | |
82 | ||
83 | void psxException(u32 code, u32 bd) { | |
7a811716 | 84 | #ifdef ICACHE_EMULATION |
85 | /* Without the CPU_INTERPRETER condition, this will make Lightrec crash. | |
86 | * Hopefully a better solution than this mess is found. - Gameblabla | |
87 | */ | |
88 | if (Config.icache_emulation && Config.Cpu == CPU_INTERPRETER) | |
89 | { | |
90 | psxRegs.code = SWAPu32(*Read_ICache(psxRegs.pc)); | |
91 | } | |
92 | else | |
93 | #endif | |
94 | { | |
95 | psxRegs.code = PSXMu32(psxRegs.pc); | |
96 | } | |
97 | ||
98 | if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) { | |
665e364a | 99 | // "hokuto no ken" / "Crash Bandicot 2" ... |
100 | // BIOS does not allow to return to GTE instructions | |
101 | // (just skips it, supposedly because it's scheduled already) | |
62656449 | 102 | // so we execute it here |
103 | extern void (*psxCP2[64])(void *cp2regs); | |
104 | psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2D); | |
665e364a | 105 | } |
106 | ||
ef79bbde | 107 | // Set the Cause |
48e74ef5 | 108 | psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code; |
ef79bbde P |
109 | |
110 | // Set the EPC & PC | |
111 | if (bd) { | |
112 | #ifdef PSXCPU_LOG | |
113 | PSXCPU_LOG("bd set!!!\n"); | |
114 | #endif | |
115 | SysPrintf("bd set!!!\n"); | |
116 | psxRegs.CP0.n.Cause |= 0x80000000; | |
117 | psxRegs.CP0.n.EPC = (psxRegs.pc - 4); | |
118 | } else | |
119 | psxRegs.CP0.n.EPC = (psxRegs.pc); | |
120 | ||
121 | if (psxRegs.CP0.n.Status & 0x400000) | |
122 | psxRegs.pc = 0xbfc00180; | |
123 | else | |
124 | psxRegs.pc = 0x80000080; | |
125 | ||
126 | // Set the Status | |
127 | psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status &~0x3f) | | |
128 | ((psxRegs.CP0.n.Status & 0xf) << 2); | |
129 | ||
ef79bbde P |
130 | if (Config.HLE) psxBiosException(); |
131 | } | |
132 | ||
133 | void psxBranchTest() { | |
134 | if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) | |
135 | psxRcntUpdate(); | |
136 | ||
137 | if (psxRegs.interrupt) { | |
d28b54b1 | 138 | if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio |
139 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) { | |
140 | psxRegs.interrupt &= ~(1 << PSXINT_SIO); | |
ef79bbde P |
141 | sioInterrupt(); |
142 | } | |
143 | } | |
d28b54b1 | 144 | if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr |
145 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) { | |
146 | psxRegs.interrupt &= ~(1 << PSXINT_CDR); | |
ef79bbde P |
147 | cdrInterrupt(); |
148 | } | |
149 | } | |
d28b54b1 | 150 | if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read |
151 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) { | |
152 | psxRegs.interrupt &= ~(1 << PSXINT_CDREAD); | |
ef79bbde P |
153 | cdrReadInterrupt(); |
154 | } | |
155 | } | |
d28b54b1 | 156 | if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma |
157 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) { | |
158 | psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA); | |
ef79bbde P |
159 | gpuInterrupt(); |
160 | } | |
161 | } | |
d28b54b1 | 162 | if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma |
163 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) { | |
164 | psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA); | |
ef79bbde P |
165 | mdec1Interrupt(); |
166 | } | |
167 | } | |
d28b54b1 | 168 | if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma |
169 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) { | |
170 | psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA); | |
ef79bbde P |
171 | spuInterrupt(); |
172 | } | |
173 | } | |
528ad661 | 174 | if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in |
175 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) { | |
176 | psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA); | |
177 | mdec0Interrupt(); | |
178 | } | |
179 | } | |
57a757ce | 180 | if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc |
181 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) { | |
182 | psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA); | |
183 | gpuotcInterrupt(); | |
184 | } | |
185 | } | |
9f8b032d | 186 | if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom |
187 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) { | |
188 | psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA); | |
189 | cdrDmaInterrupt(); | |
190 | } | |
191 | } | |
7f457614 | 192 | if (psxRegs.interrupt & (1 << PSXINT_CDRPLAY)) { // cdr play timing |
193 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRPLAY].sCycle) >= psxRegs.intCycle[PSXINT_CDRPLAY].cycle) { | |
194 | psxRegs.interrupt &= ~(1 << PSXINT_CDRPLAY); | |
195 | cdrPlayInterrupt(); | |
196 | } | |
197 | } | |
9f8b032d | 198 | if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states |
199 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) { | |
200 | psxRegs.interrupt &= ~(1 << PSXINT_CDRLID); | |
201 | cdrLidSeekInterrupt(); | |
202 | } | |
203 | } | |
2b30c129 | 204 | if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update |
205 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) { | |
206 | psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE); | |
207 | spuUpdate(); | |
208 | } | |
209 | } | |
ef79bbde P |
210 | } |
211 | ||
212 | if (psxHu32(0x1070) & psxHu32(0x1074)) { | |
213 | if ((psxRegs.CP0.n.Status & 0x401) == 0x401) { | |
214 | #ifdef PSXCPU_LOG | |
215 | PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074)); | |
216 | #endif | |
217 | // SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074)); | |
218 | psxException(0x400, 0); | |
219 | } | |
220 | } | |
221 | } | |
222 | ||
223 | void psxJumpTest() { | |
224 | if (!Config.HLE && Config.PsxOut) { | |
225 | u32 call = psxRegs.GPR.n.t1 & 0xff; | |
226 | switch (psxRegs.pc & 0x1fffff) { | |
227 | case 0xa0: | |
228 | #ifdef PSXBIOS_LOG | |
229 | if (call != 0x28 && call != 0xe) { | |
230 | PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); } | |
231 | #endif | |
232 | if (biosA0[call]) | |
233 | biosA0[call](); | |
234 | break; | |
235 | case 0xb0: | |
236 | #ifdef PSXBIOS_LOG | |
237 | if (call != 0x17 && call != 0xb) { | |
238 | PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); } | |
239 | #endif | |
240 | if (biosB0[call]) | |
241 | biosB0[call](); | |
242 | break; | |
243 | case 0xc0: | |
244 | #ifdef PSXBIOS_LOG | |
245 | PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); | |
246 | #endif | |
247 | if (biosC0[call]) | |
248 | biosC0[call](); | |
249 | break; | |
250 | } | |
251 | } | |
252 | } | |
253 | ||
254 | void psxExecuteBios() { | |
255 | while (psxRegs.pc != 0x80030000) | |
256 | psxCpu->ExecuteBlock(); | |
257 | } | |
258 |