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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * R3000A CPU functions. | |
22 | */ | |
23 | ||
24 | #include "r3000a.h" | |
25 | #include "cdrom.h" | |
26 | #include "mdec.h" | |
27 | #include "gte.h" | |
630b122b | 28 | #include "psxinterpreter.h" |
ef79bbde P |
29 | |
30 | R3000Acpu *psxCpu = NULL; | |
630b122b | 31 | #ifdef DRC_DISABLE |
93c9e42a | 32 | psxRegisters psxRegs; |
1a32b0f8 | 33 | #endif |
ef79bbde P |
34 | |
35 | int psxInit() { | |
202b29d4 | 36 | SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__); |
ef79bbde | 37 | |
630b122b | 38 | #ifndef DRC_DISABLE |
ef79bbde P |
39 | if (Config.Cpu == CPU_INTERPRETER) { |
40 | psxCpu = &psxInt; | |
41 | } else psxCpu = &psxRec; | |
42 | #else | |
630b122b | 43 | Config.Cpu = CPU_INTERPRETER; |
ef79bbde P |
44 | psxCpu = &psxInt; |
45 | #endif | |
46 | ||
47 | Log = 0; | |
48 | ||
49 | if (psxMemInit() == -1) return -1; | |
50 | ||
51 | return psxCpu->Init(); | |
52 | } | |
53 | ||
54 | void psxReset() { | |
ef79bbde P |
55 | psxMemReset(); |
56 | ||
630b122b | 57 | memset(&psxRegs, 0, sizeof(psxRegs)); |
58 | ||
ef79bbde P |
59 | psxRegs.pc = 0xbfc00000; // Start in bootstrap |
60 | ||
61 | psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1 | |
62 | psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A | |
63 | ||
c24732c0 | 64 | psxCpu->Reset(); |
65 | ||
ef79bbde P |
66 | psxHwReset(); |
67 | psxBiosInit(); | |
68 | ||
69 | if (!Config.HLE) | |
70 | psxExecuteBios(); | |
71 | ||
72 | #ifdef EMU_LOG | |
73 | EMU_LOG("*BIOS END*\n"); | |
74 | #endif | |
75 | Log = 0; | |
76 | } | |
77 | ||
78 | void psxShutdown() { | |
ef79bbde P |
79 | psxBiosShutdown(); |
80 | ||
81 | psxCpu->Shutdown(); | |
479d58cf PC |
82 | |
83 | psxMemShutdown(); | |
ef79bbde P |
84 | } |
85 | ||
86 | void psxException(u32 code, u32 bd) { | |
630b122b | 87 | psxRegs.code = fetch(psxRegs.pc); |
88 | ||
7a811716 | 89 | if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) { |
665e364a | 90 | // "hokuto no ken" / "Crash Bandicot 2" ... |
91 | // BIOS does not allow to return to GTE instructions | |
92 | // (just skips it, supposedly because it's scheduled already) | |
62656449 | 93 | // so we execute it here |
94 | extern void (*psxCP2[64])(void *cp2regs); | |
95 | psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2D); | |
665e364a | 96 | } |
97 | ||
ef79bbde | 98 | // Set the Cause |
48e74ef5 | 99 | psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code; |
ef79bbde P |
100 | |
101 | // Set the EPC & PC | |
102 | if (bd) { | |
103 | #ifdef PSXCPU_LOG | |
104 | PSXCPU_LOG("bd set!!!\n"); | |
105 | #endif | |
ef79bbde P |
106 | psxRegs.CP0.n.Cause |= 0x80000000; |
107 | psxRegs.CP0.n.EPC = (psxRegs.pc - 4); | |
108 | } else | |
109 | psxRegs.CP0.n.EPC = (psxRegs.pc); | |
110 | ||
111 | if (psxRegs.CP0.n.Status & 0x400000) | |
112 | psxRegs.pc = 0xbfc00180; | |
113 | else | |
114 | psxRegs.pc = 0x80000080; | |
115 | ||
116 | // Set the Status | |
117 | psxRegs.CP0.n.Status = (psxRegs.CP0.n.Status &~0x3f) | | |
118 | ((psxRegs.CP0.n.Status & 0xf) << 2); | |
119 | ||
ef79bbde P |
120 | if (Config.HLE) psxBiosException(); |
121 | } | |
122 | ||
123 | void psxBranchTest() { | |
124 | if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) | |
125 | psxRcntUpdate(); | |
126 | ||
127 | if (psxRegs.interrupt) { | |
d28b54b1 | 128 | if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio |
129 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) { | |
130 | psxRegs.interrupt &= ~(1 << PSXINT_SIO); | |
ef79bbde P |
131 | sioInterrupt(); |
132 | } | |
133 | } | |
d28b54b1 | 134 | if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr |
135 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) { | |
136 | psxRegs.interrupt &= ~(1 << PSXINT_CDR); | |
ef79bbde P |
137 | cdrInterrupt(); |
138 | } | |
139 | } | |
d28b54b1 | 140 | if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read |
141 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) { | |
142 | psxRegs.interrupt &= ~(1 << PSXINT_CDREAD); | |
28eea6ac | 143 | cdrPlaySeekReadInterrupt(); |
ef79bbde P |
144 | } |
145 | } | |
d28b54b1 | 146 | if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma |
147 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) { | |
148 | psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA); | |
ef79bbde P |
149 | gpuInterrupt(); |
150 | } | |
151 | } | |
d28b54b1 | 152 | if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma |
153 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) { | |
154 | psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA); | |
ef79bbde P |
155 | mdec1Interrupt(); |
156 | } | |
157 | } | |
d28b54b1 | 158 | if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma |
159 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) { | |
160 | psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA); | |
ef79bbde P |
161 | spuInterrupt(); |
162 | } | |
163 | } | |
528ad661 | 164 | if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in |
165 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) { | |
166 | psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA); | |
167 | mdec0Interrupt(); | |
168 | } | |
169 | } | |
57a757ce | 170 | if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc |
171 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) { | |
172 | psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA); | |
173 | gpuotcInterrupt(); | |
174 | } | |
175 | } | |
9f8b032d | 176 | if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom |
177 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) { | |
178 | psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA); | |
179 | cdrDmaInterrupt(); | |
180 | } | |
181 | } | |
182 | if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states | |
183 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) { | |
184 | psxRegs.interrupt &= ~(1 << PSXINT_CDRLID); | |
185 | cdrLidSeekInterrupt(); | |
186 | } | |
187 | } | |
2b30c129 | 188 | if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update |
189 | if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) { | |
190 | psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE); | |
191 | spuUpdate(); | |
192 | } | |
193 | } | |
ef79bbde P |
194 | } |
195 | ||
196 | if (psxHu32(0x1070) & psxHu32(0x1074)) { | |
197 | if ((psxRegs.CP0.n.Status & 0x401) == 0x401) { | |
198 | #ifdef PSXCPU_LOG | |
199 | PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074)); | |
200 | #endif | |
201 | // SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074)); | |
202 | psxException(0x400, 0); | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
207 | void psxJumpTest() { | |
208 | if (!Config.HLE && Config.PsxOut) { | |
209 | u32 call = psxRegs.GPR.n.t1 & 0xff; | |
210 | switch (psxRegs.pc & 0x1fffff) { | |
211 | case 0xa0: | |
212 | #ifdef PSXBIOS_LOG | |
213 | if (call != 0x28 && call != 0xe) { | |
214 | PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); } | |
215 | #endif | |
216 | if (biosA0[call]) | |
217 | biosA0[call](); | |
218 | break; | |
219 | case 0xb0: | |
220 | #ifdef PSXBIOS_LOG | |
221 | if (call != 0x17 && call != 0xb) { | |
222 | PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); } | |
223 | #endif | |
224 | if (biosB0[call]) | |
225 | biosB0[call](); | |
226 | break; | |
227 | case 0xc0: | |
228 | #ifdef PSXBIOS_LOG | |
229 | PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); | |
230 | #endif | |
231 | if (biosC0[call]) | |
232 | biosC0[call](); | |
233 | break; | |
234 | } | |
235 | } | |
236 | } | |
237 | ||
238 | void psxExecuteBios() { | |
239 | while (psxRegs.pc != 0x80030000) | |
240 | psxCpu->ExecuteBlock(); | |
241 | } | |
242 |