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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
4 | struct Pico32x Pico32x; |
5 | |
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6 | static void sh2_irq_cb(int id, int level) |
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7 | { |
8 | // diagnostic for now |
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9 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
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10 | } |
11 | |
12 | void p32x_update_irls(void) |
13 | { |
14 | int irqs, mlvl = 0, slvl = 0; |
15 | |
16 | // msh2 |
17 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
18 | while ((irqs >>= 1)) |
19 | mlvl++; |
20 | mlvl *= 2; |
21 | |
22 | // ssh2 |
23 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
24 | while ((irqs >>= 1)) |
25 | slvl++; |
26 | slvl *= 2; |
27 | |
28 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
29 | sh2_irl_irq(&msh2, mlvl); |
30 | if (mlvl) |
31 | p32x_poll_event(0); |
32 | sh2_irl_irq(&ssh2, slvl); |
33 | } |
34 | |
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35 | void Pico32xStartup(void) |
36 | { |
37 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
38 | |
39 | PicoAHW |= PAHW_32X; |
40 | PicoMemSetup32x(); |
41 | |
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42 | sh2_init(&msh2, 0); |
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43 | msh2.irq_callback = sh2_irq_cb; |
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44 | sh2_reset(&msh2); |
45 | |
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46 | sh2_init(&ssh2, 1); |
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47 | ssh2.irq_callback = sh2_irq_cb; |
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48 | sh2_reset(&ssh2); |
49 | |
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50 | if (!Pico.m.pal) |
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51 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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52 | |
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53 | emu_32x_startup(); |
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54 | } |
55 | |
56 | void Pico32xInit(void) |
57 | { |
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58 | } |
59 | |
60 | void PicoPower32x(void) |
61 | { |
62 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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63 | |
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64 | Pico32x.regs[0] = 0x0082; // SH2 reset? |
65 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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66 | } |
67 | |
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68 | void PicoUnload32x(void) |
69 | { |
70 | if (Pico32xMem != NULL) |
71 | free(Pico32xMem); |
72 | Pico32xMem = NULL; |
73 | |
74 | PicoAHW &= ~PAHW_32X; |
75 | } |
76 | |
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77 | void PicoReset32x(void) |
78 | { |
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79 | extern int p32x_csum_faked; |
80 | p32x_csum_faked = 0; // tmp |
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81 | } |
82 | |
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83 | static void p32x_start_blank(void) |
84 | { |
85 | // enter vblank |
86 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
87 | |
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88 | // FB swap waits until vblank |
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89 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
90 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
91 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
92 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
93 | } |
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94 | |
95 | p32x_poll_event(1); |
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96 | } |
97 | |
98 | // FIXME.. |
99 | static __inline void SekRunM68k(int cyc) |
100 | { |
101 | int cyc_do; |
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102 | SekCycleAim += cyc; |
103 | if (Pico32x.emu_flags & P32XF_68KPOLL) { |
104 | SekCycleCnt = SekCycleAim; |
105 | return; |
106 | } |
107 | if ((cyc_do = SekCycleAim - SekCycleCnt) <= 0) |
108 | return; |
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109 | #if defined(EMU_CORE_DEBUG) |
110 | // this means we do run-compare |
111 | SekCycleCnt+=CM_compareRun(cyc_do, 0); |
112 | #elif defined(EMU_C68K) |
113 | PicoCpuCM68k.cycles=cyc_do; |
114 | CycloneRun(&PicoCpuCM68k); |
115 | SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles; |
116 | #elif defined(EMU_M68K) |
117 | SekCycleCnt+=m68k_execute(cyc_do); |
118 | #elif defined(EMU_F68K) |
119 | SekCycleCnt+=fm68k_emulate(cyc_do+1, 0, 0); |
120 | #endif |
121 | } |
122 | |
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123 | // ~1463.8, but due to cache misses and slow mem |
124 | // it's much lower than that |
125 | #define SH2_LINE_CYCLES 700 |
126 | |
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127 | #define PICO_32X |
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128 | #define RUN_SH2S \ |
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129 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
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130 | sh2_execute(&msh2, SH2_LINE_CYCLES); \ |
131 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
132 | sh2_execute(&ssh2, SH2_LINE_CYCLES); |
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133 | |
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134 | #include "../pico_cmn.c" |
135 | |
136 | void PicoFrame32x(void) |
137 | { |
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138 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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139 | if ((Pico32x.vdp_regs[0] & 3 ) != 0) // no forced blanking |
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140 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no pal access |
141 | |
142 | p32x_poll_event(1); |
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143 | |
144 | PicoFrameStart(); |
145 | PicoFrameHints(); |
146 | } |