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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
4 | struct Pico32x Pico32x; |
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5 | SH2 sh2s[2]; |
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6 | |
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7 | static void sh2_irq_cb(int id, int level) |
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8 | { |
9 | // diagnostic for now |
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10 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
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11 | } |
12 | |
13 | void p32x_update_irls(void) |
14 | { |
15 | int irqs, mlvl = 0, slvl = 0; |
16 | |
17 | // msh2 |
18 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
19 | while ((irqs >>= 1)) |
20 | mlvl++; |
21 | mlvl *= 2; |
22 | |
23 | // ssh2 |
24 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
25 | while ((irqs >>= 1)) |
26 | slvl++; |
27 | slvl *= 2; |
28 | |
29 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
30 | sh2_irl_irq(&msh2, mlvl); |
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31 | sh2_irl_irq(&ssh2, slvl); |
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32 | mlvl = mlvl ? 1 : 0; |
33 | slvl = slvl ? 1 : 0; |
34 | p32x_poll_event(mlvl | (slvl << 1), 0); |
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35 | } |
36 | |
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37 | void Pico32xStartup(void) |
38 | { |
39 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
40 | |
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41 | // TODO: OOM handling |
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42 | PicoAHW |= PAHW_32X; |
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43 | sh2_init(&msh2, 0); |
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44 | msh2.irq_callback = sh2_irq_cb; |
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45 | sh2_init(&ssh2, 1); |
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46 | ssh2.irq_callback = sh2_irq_cb; |
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47 | |
48 | PicoMemSetup32x(); |
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49 | |
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50 | if (!Pico.m.pal) |
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51 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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52 | |
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53 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
54 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
55 | |
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56 | emu_32x_startup(); |
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57 | } |
58 | |
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59 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
60 | void p32x_reset_sh2s(void) |
61 | { |
62 | elprintf(EL_32X, "sh2 reset"); |
63 | |
64 | sh2_reset(&msh2); |
65 | sh2_reset(&ssh2); |
66 | |
67 | // if we don't have BIOS set, perform it's work here. |
68 | // MSH2 |
69 | if (p32x_bios_m == NULL) { |
70 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
71 | unsigned int vbr; |
72 | |
73 | // initial data |
74 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
75 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
76 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
77 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
78 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
79 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
80 | idl_src, idl_dst, idl_size); |
81 | } |
82 | else |
83 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
84 | |
85 | // GBR/VBR |
86 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
87 | sh2_set_gbr(0, 0x20004000); |
88 | sh2_set_vbr(0, vbr); |
89 | |
90 | // checksum and M_OK |
91 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
92 | // program will set M_OK |
93 | } |
94 | |
95 | // SSH2 |
96 | if (p32x_bios_s == NULL) { |
97 | unsigned int vbr; |
98 | |
99 | // GBR/VBR |
100 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
101 | sh2_set_gbr(1, 0x20004000); |
102 | sh2_set_vbr(1, vbr); |
103 | // program will set S_OK |
104 | } |
105 | } |
106 | |
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107 | void Pico32xInit(void) |
108 | { |
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109 | } |
110 | |
111 | void PicoPower32x(void) |
112 | { |
113 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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114 | |
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115 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
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116 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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117 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
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118 | } |
119 | |
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120 | void PicoUnload32x(void) |
121 | { |
122 | if (Pico32xMem != NULL) |
123 | free(Pico32xMem); |
124 | Pico32xMem = NULL; |
125 | |
126 | PicoAHW &= ~PAHW_32X; |
127 | } |
128 | |
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129 | void PicoReset32x(void) |
130 | { |
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131 | if (PicoAHW & PAHW_32X) { |
132 | Pico32x.sh2irqs |= P32XI_VRES; |
133 | p32x_update_irls(); |
134 | p32x_poll_event(3, 0); |
135 | } |
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136 | } |
137 | |
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138 | static void p32x_start_blank(void) |
139 | { |
140 | // enter vblank |
141 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
142 | |
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143 | // FB swap waits until vblank |
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144 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
145 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
146 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
147 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
148 | } |
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149 | |
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150 | Pico32x.sh2irqs |= P32XI_VINT; |
151 | p32x_update_irls(); |
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152 | p32x_poll_event(3, 1); |
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153 | } |
154 | |
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155 | static __inline void run_m68k(int cyc) |
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156 | { |
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157 | #if defined(EMU_C68K) |
158 | PicoCpuCM68k.cycles = cyc; |
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159 | CycloneRun(&PicoCpuCM68k); |
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160 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
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161 | #elif defined(EMU_M68K) |
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162 | SekCycleCnt += m68k_execute(cyc); |
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163 | #elif defined(EMU_F68K) |
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164 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
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165 | #endif |
166 | } |
167 | |
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168 | // ~1463.8, but due to cache misses and slow mem |
169 | // it's much lower than that |
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170 | //#define SH2_LINE_CYCLES 735 |
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171 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
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172 | |
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173 | #define PICO_32X |
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174 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
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175 | { \ |
176 | int slice; \ |
177 | SekCycleAim += m68k_cycles; \ |
178 | while (SekCycleCnt < SekCycleAim) { \ |
179 | slice = SekCycleCnt; \ |
180 | run_m68k(SekCycleAim - SekCycleCnt); \ |
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181 | if (!(Pico32x.regs[0] & P32XS_nRES)) \ |
182 | continue; /* SH2s reseting */ \ |
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183 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
184 | if (SekCycleCnt < SekCycleAim) \ |
185 | elprintf(EL_32X, "slice %d", slice); \ |
186 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
187 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
188 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
189 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
190 | } \ |
191 | } |
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192 | |
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193 | #define STEP_68K 24 |
194 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
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195 | { \ |
196 | int i; \ |
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197 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
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198 | run_m68k(STEP_68K); \ |
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199 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
200 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
201 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
202 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
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203 | } \ |
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204 | /* last step */ \ |
205 | i = (m68k_cycles) - i; \ |
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206 | run_m68k(i); \ |
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207 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
208 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
209 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
210 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
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211 | } |
212 | |
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213 | #define CPUS_RUN CPUS_RUN_SIMPLE |
214 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
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215 | |
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216 | #include "../pico_cmn.c" |
217 | |
218 | void PicoFrame32x(void) |
219 | { |
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220 | pwm_frame_smp_cnt = 0; |
221 | |
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222 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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223 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
224 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
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225 | |
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226 | p32x_poll_event(3, 1); |
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227 | |
228 | PicoFrameStart(); |
229 | PicoFrameHints(); |
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230 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
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231 | } |
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232 | |