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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
4 | struct Pico32x Pico32x; |
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5 | SH2 sh2s[2]; |
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6 | |
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7 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
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8 | { |
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9 | if (sh2->pending_irl > sh2->pending_int_irq) { |
10 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
11 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
12 | return 64 + sh2->pending_irl / 2; |
13 | } else { |
14 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
15 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
16 | sh2->pending_int_irq = 0; // auto-clear |
17 | sh2->pending_level = sh2->pending_irl; |
18 | return sh2->pending_int_vector; |
19 | } |
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20 | } |
21 | |
22 | void p32x_update_irls(void) |
23 | { |
24 | int irqs, mlvl = 0, slvl = 0; |
25 | |
26 | // msh2 |
27 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
28 | while ((irqs >>= 1)) |
29 | mlvl++; |
30 | mlvl *= 2; |
31 | |
32 | // ssh2 |
33 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
34 | while ((irqs >>= 1)) |
35 | slvl++; |
36 | slvl *= 2; |
37 | |
38 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
39 | sh2_irl_irq(&msh2, mlvl); |
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40 | sh2_irl_irq(&ssh2, slvl); |
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41 | mlvl = mlvl ? 1 : 0; |
42 | slvl = slvl ? 1 : 0; |
43 | p32x_poll_event(mlvl | (slvl << 1), 0); |
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44 | } |
45 | |
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46 | void Pico32xStartup(void) |
47 | { |
48 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
49 | |
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50 | // TODO: OOM handling |
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51 | PicoAHW |= PAHW_32X; |
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52 | sh2_init(&msh2, 0); |
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53 | msh2.irq_callback = sh2_irq_cb; |
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54 | sh2_init(&ssh2, 1); |
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55 | ssh2.irq_callback = sh2_irq_cb; |
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56 | |
57 | PicoMemSetup32x(); |
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58 | |
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59 | if (!Pico.m.pal) |
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60 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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61 | |
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62 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
63 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
64 | |
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65 | emu_32x_startup(); |
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66 | } |
67 | |
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68 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
69 | void p32x_reset_sh2s(void) |
70 | { |
71 | elprintf(EL_32X, "sh2 reset"); |
72 | |
73 | sh2_reset(&msh2); |
74 | sh2_reset(&ssh2); |
75 | |
76 | // if we don't have BIOS set, perform it's work here. |
77 | // MSH2 |
78 | if (p32x_bios_m == NULL) { |
79 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
80 | unsigned int vbr; |
81 | |
82 | // initial data |
83 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
84 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
85 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
86 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
87 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
88 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
89 | idl_src, idl_dst, idl_size); |
90 | } |
91 | else |
92 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
93 | |
94 | // GBR/VBR |
95 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
96 | sh2_set_gbr(0, 0x20004000); |
97 | sh2_set_vbr(0, vbr); |
98 | |
99 | // checksum and M_OK |
100 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
101 | // program will set M_OK |
102 | } |
103 | |
104 | // SSH2 |
105 | if (p32x_bios_s == NULL) { |
106 | unsigned int vbr; |
107 | |
108 | // GBR/VBR |
109 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
110 | sh2_set_gbr(1, 0x20004000); |
111 | sh2_set_vbr(1, vbr); |
112 | // program will set S_OK |
113 | } |
114 | } |
115 | |
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116 | void Pico32xInit(void) |
117 | { |
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118 | } |
119 | |
120 | void PicoPower32x(void) |
121 | { |
122 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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123 | |
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124 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
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125 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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126 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
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127 | } |
128 | |
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129 | void PicoUnload32x(void) |
130 | { |
131 | if (Pico32xMem != NULL) |
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132 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
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133 | Pico32xMem = NULL; |
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134 | sh2_finish(&msh2); |
135 | sh2_finish(&ssh2); |
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136 | |
137 | PicoAHW &= ~PAHW_32X; |
138 | } |
139 | |
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140 | void PicoReset32x(void) |
141 | { |
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142 | if (PicoAHW & PAHW_32X) { |
143 | Pico32x.sh2irqs |= P32XI_VRES; |
144 | p32x_update_irls(); |
145 | p32x_poll_event(3, 0); |
146 | } |
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147 | } |
148 | |
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149 | static void p32x_start_blank(void) |
150 | { |
151 | // enter vblank |
152 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
153 | |
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154 | // FB swap waits until vblank |
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155 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
156 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
157 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
158 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
159 | } |
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160 | |
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161 | Pico32x.sh2irqs |= P32XI_VINT; |
162 | p32x_update_irls(); |
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163 | p32x_poll_event(3, 1); |
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164 | } |
165 | |
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166 | static __inline void run_m68k(int cyc) |
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167 | { |
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168 | pprof_start(m68k); |
169 | |
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170 | #if defined(EMU_C68K) |
171 | PicoCpuCM68k.cycles = cyc; |
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172 | CycloneRun(&PicoCpuCM68k); |
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173 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
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174 | #elif defined(EMU_M68K) |
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175 | SekCycleCnt += m68k_execute(cyc); |
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176 | #elif defined(EMU_F68K) |
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177 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
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178 | #endif |
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179 | |
180 | pprof_end(m68k); |
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181 | } |
182 | |
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183 | // ~1463.8, but due to cache misses and slow mem |
184 | // it's much lower than that |
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185 | //#define SH2_LINE_CYCLES 735 |
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186 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
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187 | |
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188 | #define PICO_32X |
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189 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
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190 | { \ |
191 | int slice; \ |
192 | SekCycleAim += m68k_cycles; \ |
193 | while (SekCycleCnt < SekCycleAim) { \ |
194 | slice = SekCycleCnt; \ |
195 | run_m68k(SekCycleAim - SekCycleCnt); \ |
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196 | if (!(Pico32x.regs[0] & P32XS_nRES)) \ |
197 | continue; /* SH2s reseting */ \ |
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198 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
199 | if (SekCycleCnt < SekCycleAim) \ |
200 | elprintf(EL_32X, "slice %d", slice); \ |
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201 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) { \ |
202 | pprof_start(ssh2); \ |
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203 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
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204 | pprof_end(ssh2); \ |
205 | } \ |
206 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) { \ |
207 | pprof_start(msh2); \ |
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208 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
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209 | pprof_end(msh2); \ |
210 | } \ |
211 | pprof_start(dummy); \ |
212 | pprof_end(dummy); \ |
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213 | } \ |
214 | } |
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215 | |
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216 | #define STEP_68K 24 |
217 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
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218 | { \ |
219 | int i; \ |
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220 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
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221 | run_m68k(STEP_68K); \ |
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222 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
223 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
224 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
225 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
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226 | } \ |
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227 | /* last step */ \ |
228 | i = (m68k_cycles) - i; \ |
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229 | run_m68k(i); \ |
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230 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
231 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
232 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
233 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
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234 | } |
235 | |
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236 | #define CPUS_RUN CPUS_RUN_SIMPLE |
237 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
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238 | |
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239 | #include "../pico_cmn.c" |
240 | |
241 | void PicoFrame32x(void) |
242 | { |
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243 | pwm_frame_smp_cnt = 0; |
244 | |
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245 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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246 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
247 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
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248 | |
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249 | p32x_poll_event(3, 1); |
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250 | |
251 | PicoFrameStart(); |
252 | PicoFrameHints(); |
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253 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
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254 | } |
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255 | |