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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
4 | struct Pico32x Pico32x; |
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5 | SH2 sh2s[2]; |
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6 | |
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7 | static void sh2_irq_cb(int id, int level) |
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8 | { |
9 | // diagnostic for now |
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10 | elprintf(EL_32X, "%csh2 ack %d @ %08x", id ? 's' : 'm', level, sh2_pc(id)); |
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11 | } |
12 | |
13 | void p32x_update_irls(void) |
14 | { |
15 | int irqs, mlvl = 0, slvl = 0; |
16 | |
17 | // msh2 |
18 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
19 | while ((irqs >>= 1)) |
20 | mlvl++; |
21 | mlvl *= 2; |
22 | |
23 | // ssh2 |
24 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
25 | while ((irqs >>= 1)) |
26 | slvl++; |
27 | slvl *= 2; |
28 | |
29 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
30 | sh2_irl_irq(&msh2, mlvl); |
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31 | sh2_irl_irq(&ssh2, slvl); |
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32 | mlvl = mlvl ? 1 : 0; |
33 | slvl = slvl ? 1 : 0; |
34 | p32x_poll_event(mlvl | (slvl << 1), 0); |
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35 | } |
36 | |
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37 | void Pico32xStartup(void) |
38 | { |
39 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
40 | |
41 | PicoAHW |= PAHW_32X; |
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42 | sh2_init(&msh2, 0); |
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43 | msh2.irq_callback = sh2_irq_cb; |
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44 | sh2_init(&ssh2, 1); |
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45 | ssh2.irq_callback = sh2_irq_cb; |
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46 | |
47 | PicoMemSetup32x(); |
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48 | |
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49 | if (!Pico.m.pal) |
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50 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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51 | |
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52 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
53 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
54 | |
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55 | emu_32x_startup(); |
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56 | } |
57 | |
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58 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
59 | void p32x_reset_sh2s(void) |
60 | { |
61 | elprintf(EL_32X, "sh2 reset"); |
62 | |
63 | sh2_reset(&msh2); |
64 | sh2_reset(&ssh2); |
65 | |
66 | // if we don't have BIOS set, perform it's work here. |
67 | // MSH2 |
68 | if (p32x_bios_m == NULL) { |
69 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
70 | unsigned int vbr; |
71 | |
72 | // initial data |
73 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
74 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
75 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
76 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
77 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
78 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
79 | idl_src, idl_dst, idl_size); |
80 | } |
81 | else |
82 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
83 | |
84 | // GBR/VBR |
85 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
86 | sh2_set_gbr(0, 0x20004000); |
87 | sh2_set_vbr(0, vbr); |
88 | |
89 | // checksum and M_OK |
90 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
91 | // program will set M_OK |
92 | } |
93 | |
94 | // SSH2 |
95 | if (p32x_bios_s == NULL) { |
96 | unsigned int vbr; |
97 | |
98 | // GBR/VBR |
99 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
100 | sh2_set_gbr(1, 0x20004000); |
101 | sh2_set_vbr(1, vbr); |
102 | // program will set S_OK |
103 | } |
104 | } |
105 | |
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106 | void Pico32xInit(void) |
107 | { |
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108 | } |
109 | |
110 | void PicoPower32x(void) |
111 | { |
112 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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113 | |
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114 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
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115 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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116 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
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117 | } |
118 | |
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119 | void PicoUnload32x(void) |
120 | { |
121 | if (Pico32xMem != NULL) |
122 | free(Pico32xMem); |
123 | Pico32xMem = NULL; |
124 | |
125 | PicoAHW &= ~PAHW_32X; |
126 | } |
127 | |
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128 | void PicoReset32x(void) |
129 | { |
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130 | if (PicoAHW & PAHW_32X) { |
131 | Pico32x.sh2irqs |= P32XI_VRES; |
132 | p32x_update_irls(); |
133 | p32x_poll_event(3, 0); |
134 | } |
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135 | } |
136 | |
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137 | static void p32x_start_blank(void) |
138 | { |
139 | // enter vblank |
140 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
141 | |
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142 | // FB swap waits until vblank |
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143 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
144 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
145 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
146 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
147 | } |
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148 | |
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149 | Pico32x.sh2irqs |= P32XI_VINT; |
150 | p32x_update_irls(); |
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151 | p32x_poll_event(3, 1); |
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152 | } |
153 | |
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154 | static __inline void run_m68k(int cyc) |
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155 | { |
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156 | #if defined(EMU_C68K) |
157 | PicoCpuCM68k.cycles = cyc; |
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158 | CycloneRun(&PicoCpuCM68k); |
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159 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
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160 | #elif defined(EMU_M68K) |
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161 | SekCycleCnt += m68k_execute(cyc); |
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162 | #elif defined(EMU_F68K) |
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163 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
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164 | #endif |
165 | } |
166 | |
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167 | // ~1463.8, but due to cache misses and slow mem |
168 | // it's much lower than that |
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169 | //#define SH2_LINE_CYCLES 735 |
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170 | #define CYCLES_M68K2SH2(x) ((x) * 6 / 4) |
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171 | |
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172 | #define PICO_32X |
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173 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
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174 | { \ |
175 | int slice; \ |
176 | SekCycleAim += m68k_cycles; \ |
177 | while (SekCycleCnt < SekCycleAim) { \ |
178 | slice = SekCycleCnt; \ |
179 | run_m68k(SekCycleAim - SekCycleCnt); \ |
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180 | if (!(Pico32x.regs[0] & P32XS_nRES)) \ |
181 | continue; /* SH2s reseting */ \ |
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182 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
183 | if (SekCycleCnt < SekCycleAim) \ |
184 | elprintf(EL_32X, "slice %d", slice); \ |
185 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
186 | sh2_execute(&ssh2, CYCLES_M68K2SH2(slice)); \ |
187 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
188 | sh2_execute(&msh2, CYCLES_M68K2SH2(slice)); \ |
189 | } \ |
190 | } |
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191 | |
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192 | #define STEP_68K 24 |
193 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
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194 | { \ |
195 | int i; \ |
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196 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
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197 | run_m68k(STEP_68K); \ |
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198 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
199 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
200 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
201 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
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202 | } \ |
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203 | /* last step */ \ |
204 | i = (m68k_cycles) - i; \ |
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205 | run_m68k(i); \ |
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206 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
207 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
208 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
209 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
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210 | } |
211 | |
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212 | #define CPUS_RUN CPUS_RUN_SIMPLE |
213 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
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214 | |
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215 | #include "../pico_cmn.c" |
216 | |
217 | void PicoFrame32x(void) |
218 | { |
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219 | pwm_frame_smp_cnt = 0; |
220 | |
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221 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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222 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
223 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
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224 | |
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225 | p32x_poll_event(3, 1); |
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226 | |
227 | PicoFrameStart(); |
228 | PicoFrameHints(); |
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229 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
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230 | } |
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231 | |