cff531af |
1 | /* |
2 | * PicoDrive |
6a98f03e |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
51d86e55 |
10 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
11 | |
12 | struct Pico32x Pico32x; |
83ff19ec |
13 | SH2 sh2s[2]; |
be2c4208 |
14 | |
e05b81fc |
15 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
16 | { |
e05b81fc |
17 | if (sh2->pending_irl > sh2->pending_int_irq) { |
18 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
19 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
20 | return 64 + sh2->pending_irl / 2; |
21 | } else { |
22 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
23 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
24 | sh2->pending_int_irq = 0; // auto-clear |
25 | sh2->pending_level = sh2->pending_irl; |
26 | return sh2->pending_int_vector; |
27 | } |
4ea707e1 |
28 | } |
29 | |
a8fd6e37 |
30 | // if !nested_call, must sync CPUs before calling this |
1f1ff763 |
31 | void p32x_update_irls(int nested_call) |
4ea707e1 |
32 | { |
33 | int irqs, mlvl = 0, slvl = 0; |
a8fd6e37 |
34 | int mrun, srun; |
4ea707e1 |
35 | |
36 | // msh2 |
37 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
38 | while ((irqs >>= 1)) |
39 | mlvl++; |
40 | mlvl *= 2; |
41 | |
42 | // ssh2 |
43 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
44 | while ((irqs >>= 1)) |
45 | slvl++; |
46 | slvl *= 2; |
47 | |
a8fd6e37 |
48 | mrun = sh2_irl_irq(&msh2, mlvl, nested_call); |
49 | srun = sh2_irl_irq(&ssh2, slvl, nested_call); |
50 | p32x_poll_event(mrun | (srun << 1), 0); |
51 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
4ea707e1 |
52 | } |
53 | |
be2c4208 |
54 | void Pico32xStartup(void) |
55 | { |
56 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
57 | |
679af8a3 |
58 | // TODO: OOM handling |
be2c4208 |
59 | PicoAHW |= PAHW_32X; |
b78efee2 |
60 | sh2_init(&msh2, 0); |
4ea707e1 |
61 | msh2.irq_callback = sh2_irq_cb; |
b78efee2 |
62 | sh2_init(&ssh2, 1); |
4ea707e1 |
63 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
64 | |
65 | PicoMemSetup32x(); |
a8fd6e37 |
66 | p32x_timers_recalc(); |
acd35d4c |
67 | |
be2c4208 |
68 | if (!Pico.m.pal) |
974fdb5b |
69 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
70 | |
1d7a28a7 |
71 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
72 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
73 | |
2446536b |
74 | rendstatus_old = -1; |
75 | |
974fdb5b |
76 | emu_32x_startup(); |
be2c4208 |
77 | } |
78 | |
83ff19ec |
79 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
80 | void p32x_reset_sh2s(void) |
81 | { |
82 | elprintf(EL_32X, "sh2 reset"); |
83 | |
84 | sh2_reset(&msh2); |
85 | sh2_reset(&ssh2); |
86 | |
87 | // if we don't have BIOS set, perform it's work here. |
88 | // MSH2 |
89 | if (p32x_bios_m == NULL) { |
90 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
91 | unsigned int vbr; |
92 | |
93 | // initial data |
94 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
95 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
96 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
97 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
98 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
99 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
100 | idl_src, idl_dst, idl_size); |
101 | } |
102 | else |
103 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
104 | |
105 | // GBR/VBR |
106 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
107 | sh2_set_gbr(0, 0x20004000); |
108 | sh2_set_vbr(0, vbr); |
109 | |
110 | // checksum and M_OK |
111 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
112 | // program will set M_OK |
113 | } |
114 | |
115 | // SSH2 |
116 | if (p32x_bios_s == NULL) { |
117 | unsigned int vbr; |
118 | |
119 | // GBR/VBR |
120 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
121 | sh2_set_gbr(1, 0x20004000); |
122 | sh2_set_vbr(1, vbr); |
123 | // program will set S_OK |
124 | } |
ed4402a7 |
125 | |
126 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
83ff19ec |
127 | } |
128 | |
be2c4208 |
129 | void Pico32xInit(void) |
130 | { |
ed4402a7 |
131 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
132 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
133 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
134 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
135 | } |
136 | |
137 | void PicoPower32x(void) |
138 | { |
139 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
140 | |
83ff19ec |
141 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
974fdb5b |
142 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
87accdf7 |
143 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
be2c4208 |
144 | } |
145 | |
5e49c3a8 |
146 | void PicoUnload32x(void) |
147 | { |
148 | if (Pico32xMem != NULL) |
b081408f |
149 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
150 | Pico32xMem = NULL; |
e898de13 |
151 | sh2_finish(&msh2); |
152 | sh2_finish(&ssh2); |
5e49c3a8 |
153 | |
154 | PicoAHW &= ~PAHW_32X; |
155 | } |
156 | |
be2c4208 |
157 | void PicoReset32x(void) |
158 | { |
83ff19ec |
159 | if (PicoAHW & PAHW_32X) { |
160 | Pico32x.sh2irqs |= P32XI_VRES; |
1f1ff763 |
161 | p32x_update_irls(0); |
83ff19ec |
162 | p32x_poll_event(3, 0); |
a8fd6e37 |
163 | p32x_timers_recalc(); |
83ff19ec |
164 | } |
be2c4208 |
165 | } |
166 | |
974fdb5b |
167 | static void p32x_start_blank(void) |
168 | { |
7a961c19 |
169 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
5aec752d |
170 | int offs, lines; |
171 | |
172 | pprof_start(draw); |
173 | |
174 | offs = 8; lines = 224; |
7a961c19 |
175 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
176 | offs = 0; |
177 | lines = 240; |
178 | } |
179 | |
180 | // XXX: no proper handling of 32col mode.. |
5a681086 |
181 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
182 | (Pico.video.reg[12] & 1) && // 40col mode |
183 | (PicoDrawMask & PDRAW_32X_ON)) |
184 | { |
185 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
186 | |
187 | // we draw full layer (not line-by-line) |
188 | PicoDraw32xLayer(offs, lines, md_bg); |
189 | } |
7a961c19 |
190 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
191 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
192 | |
193 | pprof_end(draw); |
5a681086 |
194 | } |
195 | |
974fdb5b |
196 | // enter vblank |
197 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
198 | |
4ea707e1 |
199 | // FB swap waits until vblank |
974fdb5b |
200 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
201 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
202 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
203 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
204 | } |
4ea707e1 |
205 | |
97d3f47f |
206 | Pico32x.sh2irqs |= P32XI_VINT; |
1f1ff763 |
207 | p32x_update_irls(0); |
87accdf7 |
208 | p32x_poll_event(3, 1); |
974fdb5b |
209 | } |
210 | |
a8fd6e37 |
211 | /* events */ |
212 | static void pwm_irq_event(unsigned int now) |
213 | { |
214 | Pico32x.emu_flags &= ~P32XF_PWM_PEND; |
215 | p32x_pwm_schedule(now); |
216 | |
217 | Pico32x.sh2irqs |= P32XI_PWM; |
218 | p32x_update_irls(0); |
219 | } |
220 | |
221 | static void fillend_event(unsigned int now) |
222 | { |
223 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
224 | p32x_poll_event(3, 1); |
225 | } |
226 | |
227 | typedef void (event_cb)(unsigned int now); |
228 | |
6a98f03e |
229 | unsigned int event_times[P32X_EVENT_COUNT]; |
a8fd6e37 |
230 | static unsigned int event_time_next; |
231 | static event_cb *event_cbs[] = { |
232 | [P32X_EVENT_PWM] = pwm_irq_event, |
233 | [P32X_EVENT_FILLEND] = fillend_event, |
234 | }; |
235 | |
236 | // schedule event at some time (in m68k clocks) |
237 | void p32x_event_schedule(enum p32x_event event, unsigned int now, int after) |
238 | { |
239 | unsigned int when = (now + after) | 1; |
240 | |
241 | elprintf(EL_32X, "new event #%u %u->%u", event, now, when); |
242 | event_times[event] = when; |
243 | |
244 | if (event_time_next == 0 || (int)(event_time_next - now) > after) |
245 | event_time_next = when; |
246 | } |
247 | |
248 | static void run_events(unsigned int until) |
249 | { |
250 | int oldest, oldest_diff, time; |
251 | int i, diff; |
252 | |
253 | while (1) { |
254 | oldest = -1, oldest_diff = 0x7fffffff; |
255 | |
256 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
257 | if (event_times[i]) { |
258 | diff = event_times[i] - until; |
259 | if (diff < oldest_diff) { |
260 | oldest_diff = diff; |
261 | oldest = i; |
262 | } |
263 | } |
264 | } |
265 | |
266 | if (oldest_diff <= 0) { |
267 | time = event_times[oldest]; |
268 | event_times[oldest] = 0; |
269 | elprintf(EL_32X, "run event #%d %u", oldest, time); |
270 | event_cbs[oldest](time); |
271 | } |
272 | else if (oldest_diff < 0x7fffffff) { |
273 | event_time_next = event_times[oldest]; |
274 | break; |
275 | } |
276 | else { |
277 | event_time_next = 0; |
278 | break; |
279 | } |
280 | } |
281 | |
282 | if (oldest != -1) |
283 | elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next); |
284 | } |
285 | |
286 | // compare cycles, handling overflows |
287 | // check if a > b |
288 | #define CYCLES_GT(a, b) \ |
289 | ((int)((a) - (b)) > 0) |
290 | // check if a >= b |
291 | #define CYCLES_GE(a, b) \ |
292 | ((int)((a) - (b)) >= 0) |
293 | |
ed4402a7 |
294 | #define sync_sh2s_normal p32x_sync_sh2s |
295 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
296 | |
a8fd6e37 |
297 | /* most timing is in 68k clock */ |
ed4402a7 |
298 | void sync_sh2s_normal(unsigned int m68k_target) |
299 | { |
a8fd6e37 |
300 | unsigned int now, target, timer_cycles; |
301 | int cycles, done; |
ed4402a7 |
302 | |
a8fd6e37 |
303 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
ed4402a7 |
304 | |
27e26273 |
305 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
306 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
ed4402a7 |
307 | return; // rare |
27e26273 |
308 | } |
ed4402a7 |
309 | |
a8fd6e37 |
310 | now = msh2.m68krcycles_done; |
311 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
312 | now = ssh2.m68krcycles_done; |
313 | timer_cycles = now; |
314 | |
315 | while (CYCLES_GT(m68k_target, now)) |
ed4402a7 |
316 | { |
a8fd6e37 |
317 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
318 | run_events(now); |
ed4402a7 |
319 | |
a8fd6e37 |
320 | target = m68k_target; |
321 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
322 | target = event_time_next; |
323 | |
324 | while (CYCLES_GT(target, now)) |
325 | { |
326 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
327 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
328 | m68k_target - now, Pico32x.emu_flags); |
ed4402a7 |
329 | |
330 | if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) { |
331 | ssh2.m68krcycles_done = target; |
ed4402a7 |
332 | } |
a8fd6e37 |
333 | else { |
334 | cycles = target - ssh2.m68krcycles_done; |
335 | if (cycles > 0) { |
336 | done = sh2_execute(&ssh2, C_M68K_TO_SH2(ssh2, cycles)); |
337 | ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done); |
338 | |
339 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
340 | target = event_time_next; |
341 | } |
ed4402a7 |
342 | } |
343 | |
344 | if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) { |
345 | msh2.m68krcycles_done = target; |
ed4402a7 |
346 | } |
a8fd6e37 |
347 | else { |
348 | cycles = target - msh2.m68krcycles_done; |
349 | if (cycles > 0) { |
350 | done = sh2_execute(&msh2, C_M68K_TO_SH2(msh2, cycles)); |
351 | msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done); |
352 | |
353 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
354 | target = event_time_next; |
355 | } |
ed4402a7 |
356 | } |
a8fd6e37 |
357 | |
358 | now = msh2.m68krcycles_done; |
359 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
360 | now = ssh2.m68krcycles_done; |
ed4402a7 |
361 | } |
a8fd6e37 |
362 | |
363 | p32x_timers_do(now - timer_cycles); |
364 | timer_cycles = now; |
ed4402a7 |
365 | } |
236990cf |
366 | } |
acd35d4c |
367 | |
c987bb5c |
368 | #define STEP_68K 24 |
ed4402a7 |
369 | |
370 | void sync_sh2s_lockstep(unsigned int m68k_target) |
371 | { |
372 | unsigned int mcycles; |
373 | |
374 | mcycles = msh2.m68krcycles_done; |
375 | if (ssh2.m68krcycles_done < mcycles) |
376 | mcycles = ssh2.m68krcycles_done; |
377 | |
378 | while (mcycles < m68k_target) { |
379 | mcycles += STEP_68K; |
380 | sync_sh2s_normal(mcycles); |
381 | } |
87accdf7 |
382 | } |
383 | |
ed4402a7 |
384 | #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \ |
385 | SekRunM68k(m68k_cycles); \ |
a8fd6e37 |
386 | if (Pico32x.emu_flags & P32XF_68KPOLL) \ |
ed4402a7 |
387 | p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \ |
388 | } while (0) |
87accdf7 |
389 | |
ed4402a7 |
390 | #define PICO_32X |
974fdb5b |
391 | #include "../pico_cmn.c" |
392 | |
393 | void PicoFrame32x(void) |
394 | { |
4ea707e1 |
395 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
396 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
397 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
398 | |
87accdf7 |
399 | p32x_poll_event(3, 1); |
974fdb5b |
400 | |
401 | PicoFrameStart(); |
402 | PicoFrameHints(); |
51d86e55 |
403 | sh2_drc_frame(); |
404 | |
be20816c |
405 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
974fdb5b |
406 | } |
db1d3564 |
407 | |
ed4402a7 |
408 | // calculate multipliers against 68k clock (7670442) |
409 | // normally * 3, but effectively slower due to high latencies everywhere |
410 | // however using something lower breaks MK2 animations |
411 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
412 | { |
413 | float m68k_clk = (float)(OSC_NTSC / 7); |
414 | if (msh2_hz > 0) { |
415 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
416 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
417 | } |
418 | if (ssh2_hz > 0) { |
419 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
420 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
421 | } |
422 | } |
423 | |
27e26273 |
424 | void Pico32xStateLoaded(int is_early) |
425 | { |
426 | if (is_early) { |
427 | Pico32xMemStateLoaded(); |
428 | return; |
429 | } |
430 | |
431 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT; |
432 | p32x_update_irls(0); |
433 | p32x_poll_event(3, 0); |
434 | p32x_timers_recalc(); |
435 | run_events(SekCycleCntT); |
436 | } |
437 | |
ed4402a7 |
438 | // vim:shiftwidth=2:ts=2:expandtab |