cff531af |
1 | /* |
2 | * PicoDrive |
6a98f03e |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
51d86e55 |
10 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
11 | |
12 | struct Pico32x Pico32x; |
83ff19ec |
13 | SH2 sh2s[2]; |
be2c4208 |
14 | |
19886062 |
15 | #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP) |
16 | |
e05b81fc |
17 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
18 | { |
e05b81fc |
19 | if (sh2->pending_irl > sh2->pending_int_irq) { |
f8675e28 |
20 | elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x", |
21 | level, sh2_pc(sh2)); |
e05b81fc |
22 | return 64 + sh2->pending_irl / 2; |
23 | } else { |
f8675e28 |
24 | elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x", |
25 | level, sh2->pending_int_vector, sh2_pc(sh2)); |
e05b81fc |
26 | sh2->pending_int_irq = 0; // auto-clear |
27 | sh2->pending_level = sh2->pending_irl; |
28 | return sh2->pending_int_vector; |
29 | } |
4ea707e1 |
30 | } |
31 | |
c1931173 |
32 | // MUST specify active_sh2 when called from sh2 memhandlers |
4d5dfee8 |
33 | void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) |
4ea707e1 |
34 | { |
35 | int irqs, mlvl = 0, slvl = 0; |
a8fd6e37 |
36 | int mrun, srun; |
4ea707e1 |
37 | |
19886062 |
38 | if (active_sh2 != NULL) |
39 | m68k_cycles = sh2_cycles_done_m68k(active_sh2); |
40 | |
4ea707e1 |
41 | // msh2 |
9e1fa0a6 |
42 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0]; |
4ea707e1 |
43 | while ((irqs >>= 1)) |
44 | mlvl++; |
45 | mlvl *= 2; |
46 | |
47 | // ssh2 |
9e1fa0a6 |
48 | irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1]; |
4ea707e1 |
49 | while ((irqs >>= 1)) |
50 | slvl++; |
51 | slvl *= 2; |
52 | |
c1931173 |
53 | mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2); |
54 | if (mrun) { |
19886062 |
55 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
56 | if (active_sh2 == &msh2) |
57 | sh2_end_run(active_sh2, 1); |
58 | } |
19886062 |
59 | |
c1931173 |
60 | srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2); |
61 | if (srun) { |
19886062 |
62 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
63 | if (active_sh2 == &ssh2) |
64 | sh2_end_run(active_sh2, 1); |
65 | } |
19886062 |
66 | |
a8fd6e37 |
67 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
4ea707e1 |
68 | } |
69 | |
9e1fa0a6 |
70 | // the mask register is inconsistent, CMD is supposed to be a mask, |
71 | // while others are actually irq trigger enables? |
72 | // TODO: test on hw.. |
73 | void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask) |
74 | { |
75 | Pico32x.sh2irqs |= mask & P32XI_VRES; |
76 | Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3); |
77 | Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3); |
78 | |
79 | p32x_update_irls(sh2, m68k_cycles); |
80 | } |
81 | |
82 | void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles) |
83 | { |
84 | if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1)) |
85 | Pico32x.sh2irqi[0] |= P32XI_CMD; |
86 | else |
87 | Pico32x.sh2irqi[0] &= ~P32XI_CMD; |
88 | |
89 | if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2)) |
90 | Pico32x.sh2irqi[1] |= P32XI_CMD; |
91 | else |
92 | Pico32x.sh2irqi[1] &= ~P32XI_CMD; |
93 | |
94 | p32x_update_irls(sh2, m68k_cycles); |
95 | } |
96 | |
be2c4208 |
97 | void Pico32xStartup(void) |
98 | { |
99 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
100 | |
679af8a3 |
101 | // TODO: OOM handling |
be2c4208 |
102 | PicoAHW |= PAHW_32X; |
f81107f5 |
103 | sh2_init(&msh2, 0, &ssh2); |
4ea707e1 |
104 | msh2.irq_callback = sh2_irq_cb; |
f81107f5 |
105 | sh2_init(&ssh2, 1, &msh2); |
4ea707e1 |
106 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
107 | |
108 | PicoMemSetup32x(); |
045a4c52 |
109 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
110 | p32x_timers_recalc(); |
acd35d4c |
111 | |
be2c4208 |
112 | if (!Pico.m.pal) |
974fdb5b |
113 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
114 | |
2446536b |
115 | rendstatus_old = -1; |
116 | |
974fdb5b |
117 | emu_32x_startup(); |
be2c4208 |
118 | } |
119 | |
83ff19ec |
120 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
121 | void p32x_reset_sh2s(void) |
122 | { |
123 | elprintf(EL_32X, "sh2 reset"); |
124 | |
125 | sh2_reset(&msh2); |
126 | sh2_reset(&ssh2); |
cd0ace28 |
127 | sh2_peripheral_reset(&msh2); |
128 | sh2_peripheral_reset(&ssh2); |
83ff19ec |
129 | |
130 | // if we don't have BIOS set, perform it's work here. |
131 | // MSH2 |
132 | if (p32x_bios_m == NULL) { |
133 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
134 | unsigned int vbr; |
135 | |
136 | // initial data |
137 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
138 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
139 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
140 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
141 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
142 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
143 | idl_src, idl_dst, idl_size); |
144 | } |
145 | else |
146 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
147 | |
148 | // GBR/VBR |
149 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
150 | sh2_set_gbr(0, 0x20004000); |
151 | sh2_set_vbr(0, vbr); |
152 | |
153 | // checksum and M_OK |
154 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
155 | // program will set M_OK |
156 | } |
157 | |
158 | // SSH2 |
159 | if (p32x_bios_s == NULL) { |
160 | unsigned int vbr; |
161 | |
162 | // GBR/VBR |
163 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
164 | sh2_set_gbr(1, 0x20004000); |
165 | sh2_set_vbr(1, vbr); |
166 | // program will set S_OK |
167 | } |
ed4402a7 |
168 | |
169 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
83ff19ec |
170 | } |
171 | |
be2c4208 |
172 | void Pico32xInit(void) |
173 | { |
ed4402a7 |
174 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
175 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
176 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
177 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
178 | } |
179 | |
180 | void PicoPower32x(void) |
181 | { |
182 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
183 | |
83ff19ec |
184 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
4a1fb183 |
185 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN; |
87accdf7 |
186 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
be2c4208 |
187 | } |
188 | |
5e49c3a8 |
189 | void PicoUnload32x(void) |
190 | { |
191 | if (Pico32xMem != NULL) |
b081408f |
192 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
193 | Pico32xMem = NULL; |
e898de13 |
194 | sh2_finish(&msh2); |
195 | sh2_finish(&ssh2); |
5e49c3a8 |
196 | |
197 | PicoAHW &= ~PAHW_32X; |
198 | } |
199 | |
be2c4208 |
200 | void PicoReset32x(void) |
201 | { |
83ff19ec |
202 | if (PicoAHW & PAHW_32X) { |
61801d5b |
203 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
9e1fa0a6 |
204 | p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES); |
19886062 |
205 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); |
206 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); |
045a4c52 |
207 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
208 | p32x_timers_recalc(); |
83ff19ec |
209 | } |
be2c4208 |
210 | } |
211 | |
974fdb5b |
212 | static void p32x_start_blank(void) |
213 | { |
7a961c19 |
214 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
5aec752d |
215 | int offs, lines; |
216 | |
217 | pprof_start(draw); |
218 | |
219 | offs = 8; lines = 224; |
7a961c19 |
220 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
221 | offs = 0; |
222 | lines = 240; |
223 | } |
224 | |
225 | // XXX: no proper handling of 32col mode.. |
5a681086 |
226 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
227 | (Pico.video.reg[12] & 1) && // 40col mode |
228 | (PicoDrawMask & PDRAW_32X_ON)) |
229 | { |
230 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
231 | |
232 | // we draw full layer (not line-by-line) |
233 | PicoDraw32xLayer(offs, lines, md_bg); |
234 | } |
7a961c19 |
235 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
236 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
237 | |
238 | pprof_end(draw); |
5a681086 |
239 | } |
240 | |
974fdb5b |
241 | // enter vblank |
242 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
243 | |
4ea707e1 |
244 | // FB swap waits until vblank |
974fdb5b |
245 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
246 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
247 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
248 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
249 | } |
4ea707e1 |
250 | |
9e1fa0a6 |
251 | p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT); |
19886062 |
252 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
253 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
254 | } |
255 | |
5ac99d9a |
256 | void p32x_schedule_hint(SH2 *sh2, int m68k_cycles) |
257 | { |
258 | // rather rough, 32x hint is useless in practice |
259 | int after; |
260 | |
261 | if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4)) |
262 | return; // nobody cares |
263 | // note: when Pico.m.scanline is 224, SH2s might |
264 | // still be at scanline 93 (or so) |
265 | if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224) |
266 | return; |
267 | |
268 | after = (Pico32x.sh2_regs[4 / 2] + 1) * 488; |
269 | if (sh2 != NULL) |
270 | p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after); |
271 | else |
272 | p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after); |
273 | } |
274 | |
19886062 |
275 | // compare cycles, handling overflows |
276 | // check if a > b |
277 | #define CYCLES_GT(a, b) \ |
278 | ((int)((a) - (b)) > 0) |
279 | // check if a >= b |
280 | #define CYCLES_GE(a, b) \ |
281 | ((int)((a) - (b)) >= 0) |
282 | |
a8fd6e37 |
283 | /* events */ |
a8fd6e37 |
284 | static void fillend_event(unsigned int now) |
285 | { |
286 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
19886062 |
287 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now); |
288 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now); |
a8fd6e37 |
289 | } |
290 | |
5ac99d9a |
291 | static void hint_event(unsigned int now) |
292 | { |
9e1fa0a6 |
293 | p32x_trigger_irq(NULL, now, P32XI_HINT); |
5ac99d9a |
294 | p32x_schedule_hint(NULL, now); |
295 | } |
296 | |
a8fd6e37 |
297 | typedef void (event_cb)(unsigned int now); |
298 | |
6a98f03e |
299 | unsigned int event_times[P32X_EVENT_COUNT]; |
a8fd6e37 |
300 | static unsigned int event_time_next; |
301 | static event_cb *event_cbs[] = { |
df63f1a6 |
302 | [P32X_EVENT_PWM] = p32x_pwm_irq_event, |
a8fd6e37 |
303 | [P32X_EVENT_FILLEND] = fillend_event, |
5ac99d9a |
304 | [P32X_EVENT_HINT] = hint_event, |
a8fd6e37 |
305 | }; |
306 | |
19886062 |
307 | // schedule event at some time 'after', in m68k clocks |
308 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after) |
a8fd6e37 |
309 | { |
19886062 |
310 | unsigned int when; |
311 | |
312 | when = (now + after) | 1; |
a8fd6e37 |
313 | |
314 | elprintf(EL_32X, "new event #%u %u->%u", event, now, when); |
315 | event_times[event] = when; |
316 | |
19886062 |
317 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
a8fd6e37 |
318 | event_time_next = when; |
319 | } |
320 | |
19886062 |
321 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after) |
322 | { |
323 | unsigned int now = sh2_cycles_done_m68k(sh2); |
324 | int left_to_next; |
325 | |
326 | p32x_event_schedule(now, event, after); |
327 | |
328 | left_to_next = (event_time_next - now) * 3; |
c1931173 |
329 | sh2_end_run(sh2, left_to_next); |
19886062 |
330 | } |
331 | |
a8fd6e37 |
332 | static void run_events(unsigned int until) |
333 | { |
334 | int oldest, oldest_diff, time; |
335 | int i, diff; |
336 | |
337 | while (1) { |
338 | oldest = -1, oldest_diff = 0x7fffffff; |
339 | |
340 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
341 | if (event_times[i]) { |
342 | diff = event_times[i] - until; |
343 | if (diff < oldest_diff) { |
344 | oldest_diff = diff; |
345 | oldest = i; |
346 | } |
347 | } |
348 | } |
349 | |
350 | if (oldest_diff <= 0) { |
351 | time = event_times[oldest]; |
352 | event_times[oldest] = 0; |
353 | elprintf(EL_32X, "run event #%d %u", oldest, time); |
354 | event_cbs[oldest](time); |
355 | } |
356 | else if (oldest_diff < 0x7fffffff) { |
357 | event_time_next = event_times[oldest]; |
358 | break; |
359 | } |
360 | else { |
361 | event_time_next = 0; |
362 | break; |
363 | } |
364 | } |
365 | |
366 | if (oldest != -1) |
367 | elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next); |
368 | } |
369 | |
19886062 |
370 | static inline void run_sh2(SH2 *sh2, int m68k_cycles) |
371 | { |
372 | int cycles, done; |
373 | |
374 | pevt_log_sh2_o(sh2, EVT_RUN_START); |
375 | sh2->state |= SH2_STATE_RUN; |
376 | cycles = C_M68K_TO_SH2(*sh2, m68k_cycles); |
f8675e28 |
377 | elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x", |
378 | sh2->m68krcycles_done, cycles, sh2->pc); |
19886062 |
379 | |
380 | done = sh2_execute(sh2, cycles); |
381 | |
382 | sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done); |
383 | sh2->state &= ~SH2_STATE_RUN; |
384 | pevt_log_sh2_o(sh2, EVT_RUN_END); |
f8675e28 |
385 | elprintf_sh2(sh2, EL_32X, "-run %u %d", |
386 | sh2->m68krcycles_done, done); |
19886062 |
387 | } |
388 | |
389 | // sync other sh2 to this one |
390 | // note: recursive call |
391 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target) |
392 | { |
f81107f5 |
393 | SH2 *osh2 = sh2->other_sh2; |
19886062 |
394 | int left_to_event; |
395 | int m68k_cycles; |
396 | |
397 | if (osh2->state & SH2_STATE_RUN) |
398 | return; |
399 | |
400 | m68k_cycles = m68k_target - osh2->m68krcycles_done; |
401 | if (m68k_cycles < 200) |
402 | return; |
403 | |
404 | if (osh2->state & SH2_IDLE_STATES) { |
405 | osh2->m68krcycles_done = m68k_target; |
406 | return; |
407 | } |
408 | |
f8675e28 |
409 | elprintf_sh2(osh2, EL_32X, "sync to %u %d", |
410 | m68k_target, m68k_cycles); |
19886062 |
411 | |
412 | run_sh2(osh2, m68k_cycles); |
413 | |
414 | // there might be new event to schedule current sh2 to |
415 | if (event_time_next) { |
416 | left_to_event = event_time_next - m68k_target; |
417 | left_to_event *= 3; |
418 | if (sh2_cycles_left(sh2) > left_to_event) { |
419 | if (left_to_event < 1) |
420 | left_to_event = 1; |
421 | sh2_end_run(sh2, left_to_event); |
422 | } |
423 | } |
424 | } |
a8fd6e37 |
425 | |
ed4402a7 |
426 | #define sync_sh2s_normal p32x_sync_sh2s |
427 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
428 | |
a8fd6e37 |
429 | /* most timing is in 68k clock */ |
ed4402a7 |
430 | void sync_sh2s_normal(unsigned int m68k_target) |
431 | { |
a8fd6e37 |
432 | unsigned int now, target, timer_cycles; |
19886062 |
433 | int cycles; |
ed4402a7 |
434 | |
a8fd6e37 |
435 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
ed4402a7 |
436 | |
27e26273 |
437 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
438 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
ed4402a7 |
439 | return; // rare |
27e26273 |
440 | } |
ed4402a7 |
441 | |
a8fd6e37 |
442 | now = msh2.m68krcycles_done; |
443 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
444 | now = ssh2.m68krcycles_done; |
445 | timer_cycles = now; |
446 | |
447 | while (CYCLES_GT(m68k_target, now)) |
ed4402a7 |
448 | { |
a8fd6e37 |
449 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
450 | run_events(now); |
ed4402a7 |
451 | |
a8fd6e37 |
452 | target = m68k_target; |
453 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
454 | target = event_time_next; |
455 | |
456 | while (CYCLES_GT(target, now)) |
457 | { |
458 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
459 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
460 | m68k_target - now, Pico32x.emu_flags); |
ed4402a7 |
461 | |
19886062 |
462 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
463 | cycles = target - ssh2.m68krcycles_done; |
464 | if (cycles > 0) { |
19886062 |
465 | run_sh2(&ssh2, cycles); |
a8fd6e37 |
466 | |
467 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
468 | target = event_time_next; |
469 | } |
ed4402a7 |
470 | } |
471 | |
19886062 |
472 | if (!(msh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
473 | cycles = target - msh2.m68krcycles_done; |
474 | if (cycles > 0) { |
19886062 |
475 | run_sh2(&msh2, cycles); |
a8fd6e37 |
476 | |
477 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
478 | target = event_time_next; |
479 | } |
ed4402a7 |
480 | } |
a8fd6e37 |
481 | |
19886062 |
482 | now = target; |
483 | if (!(msh2.state & SH2_IDLE_STATES)) { |
484 | if (CYCLES_GT(now, msh2.m68krcycles_done)) |
485 | now = msh2.m68krcycles_done; |
486 | } |
487 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
488 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
489 | now = ssh2.m68krcycles_done; |
490 | } |
ed4402a7 |
491 | } |
a8fd6e37 |
492 | |
045a4c52 |
493 | p32x_timers_do(now - timer_cycles); |
a8fd6e37 |
494 | timer_cycles = now; |
ed4402a7 |
495 | } |
19886062 |
496 | |
497 | // advance idle CPUs |
498 | if (msh2.state & SH2_IDLE_STATES) { |
499 | if (CYCLES_GT(m68k_target, msh2.m68krcycles_done)) |
500 | msh2.m68krcycles_done = m68k_target; |
501 | } |
502 | if (ssh2.state & SH2_IDLE_STATES) { |
503 | if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done)) |
504 | ssh2.m68krcycles_done = m68k_target; |
505 | } |
236990cf |
506 | } |
acd35d4c |
507 | |
c987bb5c |
508 | #define STEP_68K 24 |
ed4402a7 |
509 | |
510 | void sync_sh2s_lockstep(unsigned int m68k_target) |
511 | { |
512 | unsigned int mcycles; |
513 | |
514 | mcycles = msh2.m68krcycles_done; |
515 | if (ssh2.m68krcycles_done < mcycles) |
516 | mcycles = ssh2.m68krcycles_done; |
517 | |
518 | while (mcycles < m68k_target) { |
519 | mcycles += STEP_68K; |
520 | sync_sh2s_normal(mcycles); |
521 | } |
87accdf7 |
522 | } |
523 | |
ed4402a7 |
524 | #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \ |
525 | SekRunM68k(m68k_cycles); \ |
19886062 |
526 | if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \ |
527 | p32x_sync_sh2s(SekCyclesDoneT2()); \ |
ed4402a7 |
528 | } while (0) |
87accdf7 |
529 | |
ed4402a7 |
530 | #define PICO_32X |
974fdb5b |
531 | #include "../pico_cmn.c" |
532 | |
533 | void PicoFrame32x(void) |
534 | { |
5ac99d9a |
535 | Pico.m.scanline = 0; |
536 | |
4ea707e1 |
537 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
538 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
539 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
540 | |
5ac99d9a |
541 | if (!(Pico32x.sh2_regs[0] & 0x80)) |
542 | p32x_schedule_hint(NULL, SekCyclesDoneT2()); |
19886062 |
543 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
544 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
545 | |
546 | PicoFrameStart(); |
547 | PicoFrameHints(); |
51d86e55 |
548 | sh2_drc_frame(); |
549 | |
19886062 |
550 | elprintf(EL_32X, "poll: %02x %02x %02x", |
551 | Pico32x.emu_flags & 3, msh2.state, ssh2.state); |
974fdb5b |
552 | } |
db1d3564 |
553 | |
ed4402a7 |
554 | // calculate multipliers against 68k clock (7670442) |
555 | // normally * 3, but effectively slower due to high latencies everywhere |
556 | // however using something lower breaks MK2 animations |
557 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
558 | { |
559 | float m68k_clk = (float)(OSC_NTSC / 7); |
560 | if (msh2_hz > 0) { |
561 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
562 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
563 | } |
564 | if (ssh2_hz > 0) { |
565 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
566 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
567 | } |
568 | } |
569 | |
27e26273 |
570 | void Pico32xStateLoaded(int is_early) |
571 | { |
572 | if (is_early) { |
573 | Pico32xMemStateLoaded(); |
574 | return; |
575 | } |
576 | |
19886062 |
577 | SekCycleCnt = 0; |
27e26273 |
578 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT; |
4d5dfee8 |
579 | p32x_update_irls(NULL, SekCycleCntT); |
df63f1a6 |
580 | p32x_pwm_state_loaded(); |
27e26273 |
581 | run_events(SekCycleCntT); |
582 | } |
583 | |
ed4402a7 |
584 | // vim:shiftwidth=2:ts=2:expandtab |