045a4c52 |
1 | /* |
2 | * SH2 peripherals/"system on chip" |
3 | * (C) notaz, 2013 |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | * |
8 | * rough fffffe00-ffffffff map: |
9 | * e00-e05 SCI serial communication interface |
10 | * e10-e1a FRT free-running timer |
11 | * e60-e68 VCRx irq vectors |
12 | * e71-e72 DRCR dma selection |
13 | * e80-e83 WDT watchdog timer |
14 | * e91 SBYCR standby control |
15 | * e92 CCR cache control |
16 | * ee0 ICR irq control |
17 | * ee2 IPRA irq priorities |
18 | * ee4 VCRWDT WDT irq vectors |
19 | * f00-f17 DIVU |
20 | * f40-f7b UBC user break controller |
21 | * f80-fb3 DMAC |
22 | * fe0-ffb BSC bus state controller |
23 | */ |
24 | |
25 | #include "../pico_int.h" |
26 | #include "../memory.h" |
27 | |
28 | // DMAC handling |
29 | struct dma_chan { |
30 | unsigned int sar, dar; // src, dst addr |
31 | unsigned int tcr; // transfer count |
32 | unsigned int chcr; // chan ctl |
33 | // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de |
34 | // ts - transfer size: 1, 2, 4, 16 bytes |
35 | // ar - auto request if 1, else dreq signal |
36 | // ie - irq enable |
37 | // te - transfer end |
38 | // de - dma enable |
39 | #define DMA_AR (1 << 9) |
40 | #define DMA_IE (1 << 2) |
41 | #define DMA_TE (1 << 1) |
42 | #define DMA_DE (1 << 0) |
43 | }; |
44 | |
45 | struct dmac { |
46 | struct dma_chan chan[2]; |
47 | unsigned int vcrdma0; |
48 | unsigned int unknown0; |
49 | unsigned int vcrdma1; |
50 | unsigned int unknown1; |
51 | unsigned int dmaor; |
52 | // -- pr ae nmif dme |
53 | // pr - priority: chan0 > chan1 or round-robin |
54 | // ae - address error |
55 | // nmif - nmi occurred |
56 | // dme - DMA master enable |
57 | #define DMA_DME (1 << 0) |
58 | }; |
59 | |
60 | static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan) |
61 | { |
f81107f5 |
62 | char *regs = (void *)sh2->peri_regs; |
045a4c52 |
63 | struct dmac *dmac = (void *)(regs + 0x180); |
64 | int level = PREG8(regs, 0xe2) & 0x0f; // IPRA |
65 | int vector = (chan == &dmac->chan[0]) ? |
66 | dmac->vcrdma0 : dmac->vcrdma1; |
67 | |
68 | elprintf(EL_32XP, "dmac irq %d %d", level, vector); |
69 | sh2_internal_irq(sh2, level, vector & 0x7f); |
70 | } |
71 | |
72 | static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan) |
73 | { |
74 | chan->chcr |= DMA_TE; // DMA has ended normally |
75 | |
ae214f1c |
76 | p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone()); |
045a4c52 |
77 | if (chan->chcr & DMA_IE) |
78 | dmac_te_irq(sh2, chan); |
79 | } |
80 | |
81 | static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan) |
82 | { |
83 | u32 size, d; |
84 | |
85 | size = (chan->chcr >> 10) & 3; |
86 | switch (size) { |
87 | case 0: |
88 | d = p32x_sh2_read8(chan->sar, sh2); |
89 | p32x_sh2_write8(chan->dar, d, sh2); |
90 | case 1: |
91 | d = p32x_sh2_read16(chan->sar, sh2); |
92 | p32x_sh2_write16(chan->dar, d, sh2); |
93 | break; |
94 | case 2: |
95 | d = p32x_sh2_read32(chan->sar, sh2); |
96 | p32x_sh2_write32(chan->dar, d, sh2); |
97 | break; |
98 | case 3: |
99 | d = p32x_sh2_read32(chan->sar + 0x00, sh2); |
100 | p32x_sh2_write32(chan->dar + 0x00, d, sh2); |
101 | d = p32x_sh2_read32(chan->sar + 0x04, sh2); |
102 | p32x_sh2_write32(chan->dar + 0x04, d, sh2); |
103 | d = p32x_sh2_read32(chan->sar + 0x08, sh2); |
104 | p32x_sh2_write32(chan->dar + 0x08, d, sh2); |
105 | d = p32x_sh2_read32(chan->sar + 0x0c, sh2); |
106 | p32x_sh2_write32(chan->dar + 0x0c, d, sh2); |
107 | chan->sar += 16; // always? |
108 | if (chan->chcr & (1 << 15)) |
109 | chan->dar -= 16; |
110 | if (chan->chcr & (1 << 14)) |
111 | chan->dar += 16; |
112 | chan->tcr -= 4; |
113 | return; |
114 | } |
115 | chan->tcr--; |
116 | |
117 | size = 1 << size; |
118 | if (chan->chcr & (1 << 15)) |
119 | chan->dar -= size; |
120 | if (chan->chcr & (1 << 14)) |
121 | chan->dar += size; |
122 | if (chan->chcr & (1 << 13)) |
123 | chan->sar -= size; |
124 | if (chan->chcr & (1 << 12)) |
125 | chan->sar += size; |
126 | } |
127 | |
128 | // DMA trigger by SH2 register write |
129 | static void dmac_trigger(SH2 *sh2, struct dma_chan *chan) |
130 | { |
f8675e28 |
131 | elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x", |
045a4c52 |
132 | chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); |
133 | chan->tcr &= 0xffffff; |
134 | |
135 | if (chan->chcr & DMA_AR) { |
136 | // auto-request transfer |
137 | while ((int)chan->tcr > 0) |
138 | dmac_transfer_one(sh2, chan); |
139 | dmac_transfer_complete(sh2, chan); |
140 | return; |
141 | } |
142 | |
143 | // DREQ0 is only sent after first 4 words are written. |
144 | // we do multiple of 4 words to avoid messing up alignment |
61801d5b |
145 | if ((chan->sar & ~0x20000000) == 0x00004012) { |
045a4c52 |
146 | if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) { |
147 | elprintf(EL_32XP, "68k -> sh2 DMA"); |
148 | p32x_dreq0_trigger(); |
149 | } |
150 | return; |
151 | } |
152 | |
1ac97cbb |
153 | // DREQ1 |
154 | if ((chan->dar & 0xc7fffff0) == 0x00004030) |
155 | return; |
156 | |
045a4c52 |
157 | elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: " |
158 | "%08x->%08x, cnt %d, chcr %04x @%06x", |
159 | chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); |
160 | } |
161 | |
162 | // timer state - FIXME |
163 | static int timer_cycles[2]; |
164 | static int timer_tick_cycles[2]; |
165 | |
166 | // timers |
167 | void p32x_timers_recalc(void) |
168 | { |
169 | int cycles; |
170 | int tmp, i; |
171 | |
172 | // SH2 timer step |
173 | for (i = 0; i < 2; i++) { |
f81107f5 |
174 | tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7; |
045a4c52 |
175 | // Sclk cycles per timer tick |
176 | if (tmp) |
177 | cycles = 0x20 << tmp; |
178 | else |
179 | cycles = 2; |
180 | timer_tick_cycles[i] = cycles; |
181 | timer_cycles[i] = 0; |
182 | elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles); |
183 | } |
184 | } |
185 | |
186 | void p32x_timers_do(unsigned int m68k_slice) |
187 | { |
188 | unsigned int cycles = m68k_slice * 3; |
189 | int cnt, i; |
190 | |
191 | // WDT timers |
192 | for (i = 0; i < 2; i++) { |
f81107f5 |
193 | void *pregs = sh2s[i].peri_regs; |
045a4c52 |
194 | if (PREG8(pregs, 0x80) & 0x20) { // TME |
195 | timer_cycles[i] += cycles; |
196 | cnt = PREG8(pregs, 0x81); |
197 | while (timer_cycles[i] >= timer_tick_cycles[i]) { |
198 | timer_cycles[i] -= timer_tick_cycles[i]; |
199 | cnt++; |
200 | } |
201 | if (cnt >= 0x100) { |
202 | int level = PREG8(pregs, 0xe3) >> 4; |
203 | int vector = PREG8(pregs, 0xe4) & 0x7f; |
204 | elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)", |
205 | i ? 's' : 'm', level, vector); |
206 | sh2_internal_irq(&sh2s[i], level, vector); |
207 | cnt &= 0xff; |
208 | } |
209 | PREG8(pregs, 0x81) = cnt; |
210 | } |
211 | } |
212 | } |
213 | |
cd0ace28 |
214 | void sh2_peripheral_reset(SH2 *sh2) |
215 | { |
216 | memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ? |
61801d5b |
217 | PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR |
218 | PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR |
219 | PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR |
220 | PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER |
221 | PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR |
cd0ace28 |
222 | } |
223 | |
045a4c52 |
224 | // ------------------------------------------------------------------ |
225 | // SH2 internal peripheral memhandlers |
226 | // we keep them in little endian format |
227 | |
f81107f5 |
228 | u32 sh2_peripheral_read8(u32 a, SH2 *sh2) |
045a4c52 |
229 | { |
f81107f5 |
230 | u8 *r = (void *)sh2->peri_regs; |
045a4c52 |
231 | u32 d; |
232 | |
233 | a &= 0x1ff; |
234 | d = PREG8(r, a); |
235 | |
61801d5b |
236 | elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x", |
237 | a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
238 | return d; |
239 | } |
240 | |
f81107f5 |
241 | u32 sh2_peripheral_read16(u32 a, SH2 *sh2) |
045a4c52 |
242 | { |
f81107f5 |
243 | u16 *r = (void *)sh2->peri_regs; |
045a4c52 |
244 | u32 d; |
245 | |
246 | a &= 0x1ff; |
247 | d = r[(a / 2) ^ 1]; |
248 | |
61801d5b |
249 | elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x", |
250 | a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
251 | return d; |
252 | } |
253 | |
f81107f5 |
254 | u32 sh2_peripheral_read32(u32 a, SH2 *sh2) |
045a4c52 |
255 | { |
256 | u32 d; |
257 | a &= 0x1fc; |
f81107f5 |
258 | d = sh2->peri_regs[a / 4]; |
045a4c52 |
259 | |
61801d5b |
260 | elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x", |
261 | a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
262 | return d; |
263 | } |
264 | |
61801d5b |
265 | static void sci_trigger(SH2 *sh2, u8 *r) |
266 | { |
267 | u8 *oregs; |
268 | |
269 | if (!(PREG8(r, 2) & 0x20)) |
270 | return; // transmitter not enabled |
271 | if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty |
272 | return; |
273 | |
274 | oregs = (u8 *)sh2->other_sh2->peri_regs; |
275 | if (!(PREG8(oregs, 2) & 0x10)) |
276 | return; // receiver not enabled |
277 | |
278 | PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR |
279 | PREG8(r, 4) |= 0x80; // TDRE - TDR empty |
280 | PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full |
281 | |
282 | // might need to delay these a bit.. |
283 | if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled |
284 | int level = PREG8(oregs, 0x60) >> 4; |
285 | int vector = PREG8(oregs, 0x64) & 0x7f; |
f8675e28 |
286 | elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)", |
61801d5b |
287 | level, vector); |
288 | sh2_internal_irq(sh2, level, vector); |
289 | } |
290 | // TODO: TEIE |
291 | if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled |
292 | int level = PREG8(oregs, 0x60) >> 4; |
293 | int vector = PREG8(oregs, 0x63) & 0x7f; |
f8675e28 |
294 | elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)", |
61801d5b |
295 | level, vector); |
296 | sh2_internal_irq(sh2->other_sh2, level, vector); |
297 | } |
298 | } |
299 | |
f81107f5 |
300 | void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
301 | { |
f81107f5 |
302 | u8 *r = (void *)sh2->peri_regs; |
61801d5b |
303 | u8 old; |
304 | |
f8675e28 |
305 | elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x", |
306 | a, d, sh2_pc(sh2)); |
045a4c52 |
307 | |
308 | a &= 0x1ff; |
61801d5b |
309 | old = PREG8(r, a); |
045a4c52 |
310 | |
61801d5b |
311 | switch (a) { |
312 | case 0x002: // SCR - serial control |
313 | if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set |
314 | PREG8(r, a) = d; |
315 | sci_trigger(sh2, r); |
045a4c52 |
316 | } |
61801d5b |
317 | break; |
318 | case 0x003: // TDR - transmit data |
319 | break; |
320 | case 0x004: // SSR - serial status |
321 | d = (old & (d | 0x06)) | (d & 1); |
322 | PREG8(r, a) = d; |
323 | sci_trigger(sh2, r); |
324 | return; |
325 | case 0x005: // RDR - receive data |
326 | break; |
327 | case 0x010: // TIER |
328 | if (d & 0x8e) |
329 | elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d); |
330 | d = (d & 0x8e) | 1; |
331 | break; |
332 | case 0x017: // TOCR |
333 | d |= 0xe0; |
334 | break; |
045a4c52 |
335 | } |
61801d5b |
336 | PREG8(r, a) = d; |
045a4c52 |
337 | } |
338 | |
f81107f5 |
339 | void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
340 | { |
f81107f5 |
341 | u16 *r = (void *)sh2->peri_regs; |
61801d5b |
342 | elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x", |
343 | a, d, sh2_pc(sh2)); |
045a4c52 |
344 | |
345 | a &= 0x1ff; |
346 | |
347 | // evil WDT |
348 | if (a == 0x80) { |
349 | if ((d & 0xff00) == 0xa500) { // WTCSR |
350 | PREG8(r, 0x80) = d; |
351 | p32x_timers_recalc(); |
352 | } |
353 | if ((d & 0xff00) == 0x5a00) // WTCNT |
354 | PREG8(r, 0x81) = d; |
f81107f5 |
355 | return; |
045a4c52 |
356 | } |
357 | |
358 | r[(a / 2) ^ 1] = d; |
045a4c52 |
359 | } |
360 | |
8b43bc73 |
361 | void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
362 | { |
f81107f5 |
363 | u32 *r = sh2->peri_regs; |
61801d5b |
364 | u32 old; |
365 | |
366 | elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x", |
367 | a, d, sh2_pc(sh2)); |
045a4c52 |
368 | |
369 | a &= 0x1fc; |
61801d5b |
370 | old = r[a / 4]; |
045a4c52 |
371 | r[a / 4] = d; |
372 | |
373 | switch (a) { |
374 | // division unit (TODO: verify): |
375 | case 0x104: // DVDNT: divident L, starts divide |
61801d5b |
376 | elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x", |
377 | d, r[0x100 / 4]); |
045a4c52 |
378 | if (r[0x100 / 4]) { |
379 | signed int divisor = r[0x100 / 4]; |
380 | r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; |
381 | r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; |
382 | } |
383 | else |
384 | r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? |
385 | break; |
386 | case 0x114: |
61801d5b |
387 | elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x", |
388 | r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2)); |
045a4c52 |
389 | if (r[0x100 / 4]) { |
390 | signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; |
391 | signed int divisor = r[0x100 / 4]; |
392 | // XXX: undocumented mirroring to 0x118,0x11c? |
393 | r[0x118 / 4] = r[0x110 / 4] = divident % divisor; |
394 | divident /= divisor; |
395 | r[0x11c / 4] = r[0x114 / 4] = divident; |
396 | divident >>= 31; |
397 | if ((unsigned long long)divident + 1 > 1) { |
61801d5b |
398 | //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2)); |
045a4c52 |
399 | r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow |
400 | } |
401 | } |
402 | else |
403 | r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? |
404 | break; |
405 | } |
406 | |
407 | // perhaps starting a DMA? |
408 | if (a == 0x1b0 || a == 0x18c || a == 0x19c) { |
f81107f5 |
409 | struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4]; |
61801d5b |
410 | if (a == 0x1b0 && !((old ^ d) & d & DMA_DME)) |
411 | return; |
045a4c52 |
412 | if (!(dmac->dmaor & DMA_DME)) |
413 | return; |
414 | |
415 | if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE) |
f81107f5 |
416 | dmac_trigger(sh2, &dmac->chan[0]); |
045a4c52 |
417 | if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE) |
f81107f5 |
418 | dmac_trigger(sh2, &dmac->chan[1]); |
045a4c52 |
419 | } |
420 | } |
421 | |
422 | /* 32X specific */ |
423 | static void dreq0_do(SH2 *sh2, struct dma_chan *chan) |
424 | { |
7eaa3812 |
425 | unsigned short dreqlen = Pico32x.regs[0x10 / 2]; |
045a4c52 |
426 | int i; |
427 | |
428 | // debug/sanity checks |
7eaa3812 |
429 | if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4) |
430 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d", |
431 | chan->tcr, dreqlen); |
045a4c52 |
432 | // note: DACK is not connected, single addr mode should not be used |
433 | if ((chan->chcr & 0x3f08) != 0x0400) |
434 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr); |
61801d5b |
435 | if ((chan->sar & ~0x20000000) != 0x00004012) |
436 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar); |
045a4c52 |
437 | |
438 | // HACK: assume bus is busy and SH2 is halted |
439 | sh2->state |= SH2_STATE_SLEEP; |
440 | |
441 | for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) { |
f8675e28 |
442 | elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d", |
7eaa3812 |
443 | chan->dar, Pico32x.dmac_fifo[i], dreqlen); |
045a4c52 |
444 | p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2); |
445 | chan->dar += 2; |
446 | chan->tcr--; |
045a4c52 |
447 | } |
448 | |
449 | if (Pico32x.dmac0_fifo_ptr != i) |
450 | memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i], |
451 | (Pico32x.dmac0_fifo_ptr - i) * 2); |
452 | Pico32x.dmac0_fifo_ptr -= i; |
453 | |
454 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
045a4c52 |
455 | if (chan->tcr == 0) |
456 | dmac_transfer_complete(sh2, chan); |
457 | else |
458 | sh2_end_run(sh2, 16); |
459 | } |
460 | |
461 | static void dreq1_do(SH2 *sh2, struct dma_chan *chan) |
462 | { |
463 | // debug/sanity checks |
464 | if ((chan->chcr & 0xc308) != 0x0000) |
465 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr); |
466 | if ((chan->dar & ~0xf) != 0x20004030) |
467 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar); |
468 | |
469 | dmac_transfer_one(sh2, chan); |
470 | if (chan->tcr == 0) |
471 | dmac_transfer_complete(sh2, chan); |
472 | } |
473 | |
474 | void p32x_dreq0_trigger(void) |
475 | { |
f81107f5 |
476 | struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4]; |
477 | struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4]; |
045a4c52 |
478 | |
479 | elprintf(EL_32XP, "dreq0_trigger"); |
480 | if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) { |
481 | dreq0_do(&msh2, &mdmac->chan[0]); |
482 | } |
483 | if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) { |
484 | dreq0_do(&ssh2, &sdmac->chan[0]); |
485 | } |
486 | } |
487 | |
488 | void p32x_dreq1_trigger(void) |
489 | { |
f81107f5 |
490 | struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4]; |
491 | struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4]; |
045a4c52 |
492 | int hit = 0; |
493 | |
494 | elprintf(EL_32XP, "dreq1_trigger"); |
495 | if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) { |
496 | dreq1_do(&msh2, &mdmac->chan[1]); |
497 | hit = 1; |
498 | } |
499 | if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) { |
500 | dreq1_do(&ssh2, &sdmac->chan[1]); |
501 | hit = 1; |
502 | } |
503 | |
1ac97cbb |
504 | // debug |
505 | #if (EL_LOGMASK & (EL_32XP|EL_ANOMALY)) |
506 | { |
507 | static int miss_count; |
508 | if (!hit) { |
509 | if (++miss_count == 4) |
510 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared"); |
511 | } |
512 | else |
513 | miss_count = 0; |
514 | } |
515 | #endif |
516 | (void)hit; |
045a4c52 |
517 | } |
518 | |
519 | // vim:shiftwidth=2:ts=2:expandtab |