65ca3034 |
1 | // SSP1601 to ARM recompiler |
2 | |
3 | // (c) Copyright 2008, Grazvydas "notaz" Ignotas |
4 | // Free for non-commercial use. |
726bbb3e |
5 | |
efcba75f |
6 | #include "../../pico_int.h" |
41397701 |
7 | #include "../../../cpu/drc/cmn.h" |
e807ac75 |
8 | #include "compiler.h" |
726bbb3e |
9 | |
679af8a3 |
10 | // FIXME: asm has these hardcoded |
11 | #define SSP_BLOCKTAB_ENTS (0x5090/2) |
12 | #define SSP_BLOCKTAB_IRAM_ONE (0x800/2) // table entries |
13 | #define SSP_BLOCKTAB_IRAM_ENTS (15*SSP_BLOCKTAB_IRAM_ONE) |
14 | |
15 | static u32 **ssp_block_table; // [0x5090/2]; |
16 | static u32 **ssp_block_table_iram; // [15][0x800/2]; |
71bb1b7b |
17 | |
71bb1b7b |
18 | static u32 *tcache_ptr = NULL; |
726bbb3e |
19 | |
726bbb3e |
20 | static int nblocks = 0; |
71bb1b7b |
21 | static int n_in_ops = 0; |
22 | |
23 | extern ssp1601_t *ssp; |
24 | |
25 | #define rPC ssp->gr[SSP_PC].h |
26 | #define rPMC ssp->gr[SSP_PMC] |
27 | |
28 | #define SSP_FLAG_Z (1<<0xd) |
29 | #define SSP_FLAG_N (1<<0xf) |
726bbb3e |
30 | |
5d817c91 |
31 | #ifndef ARM |
679af8a3 |
32 | //#define DUMP_BLOCK 0x0c9a |
45883918 |
33 | void ssp_drc_next(void){} |
34 | void ssp_drc_next_patch(void){} |
35 | void ssp_drc_end(void){} |
5d817c91 |
36 | #endif |
37 | |
553c3eaa |
38 | #define COUNT_OP |
65c75cb0 |
39 | #include "../../../cpu/drc/emit_arm.c" |
726bbb3e |
40 | |
41 | // ----------------------------------------------------- |
42 | |
71bb1b7b |
43 | static int get_inc(int mode) |
892b1dd2 |
44 | { |
71bb1b7b |
45 | int inc = (mode >> 11) & 7; |
46 | if (inc != 0) { |
47 | if (inc != 7) inc--; |
48 | inc = 1 << inc; // 0 1 2 4 8 16 32 128 |
49 | if (mode & 0x8000) inc = -inc; // decrement mode |
892b1dd2 |
50 | } |
71bb1b7b |
51 | return inc; |
892b1dd2 |
52 | } |
53 | |
ee9ee9fd |
54 | u32 ssp_pm_read(int reg) |
d5276282 |
55 | { |
56 | u32 d = 0, mode; |
57 | |
58 | if (ssp->emu_status & SSP_PMC_SET) |
59 | { |
60 | ssp->pmac_read[reg] = rPMC.v; |
61 | ssp->emu_status &= ~SSP_PMC_SET; |
d5276282 |
62 | return 0; |
63 | } |
64 | |
d5276282 |
65 | // just in case |
66 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
67 | |
68 | mode = ssp->pmac_read[reg]>>16; |
69 | if ((mode & 0xfff0) == 0x0800) // ROM |
70 | { |
71 | d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff]; |
72 | ssp->pmac_read[reg] += 1; |
73 | } |
74 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
75 | { |
76 | unsigned short *dram = (unsigned short *)svp->dram; |
77 | int inc = get_inc(mode); |
78 | d = dram[ssp->pmac_read[reg]&0xffff]; |
79 | ssp->pmac_read[reg] += inc; |
80 | } |
81 | |
82 | // PMC value corresponds to last PMR accessed |
83 | rPMC.v = ssp->pmac_read[reg]; |
84 | |
85 | return d; |
86 | } |
87 | |
71bb1b7b |
88 | #define overwrite_write(dst, d) \ |
89 | { \ |
90 | if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \ |
91 | if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \ |
92 | if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \ |
93 | if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \ |
94 | } |
95 | |
ee9ee9fd |
96 | void ssp_pm_write(u32 d, int reg) |
d5276282 |
97 | { |
98 | unsigned short *dram; |
99 | int mode, addr; |
100 | |
101 | if (ssp->emu_status & SSP_PMC_SET) |
102 | { |
103 | ssp->pmac_write[reg] = rPMC.v; |
104 | ssp->emu_status &= ~SSP_PMC_SET; |
105 | return; |
106 | } |
107 | |
108 | // just in case |
109 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
110 | |
111 | dram = (unsigned short *)svp->dram; |
112 | mode = ssp->pmac_write[reg]>>16; |
113 | addr = ssp->pmac_write[reg]&0xffff; |
114 | if ((mode & 0x43ff) == 0x0018) // DRAM |
115 | { |
116 | int inc = get_inc(mode); |
117 | if (mode & 0x0400) { |
118 | overwrite_write(dram[addr], d); |
119 | } else dram[addr] = d; |
120 | ssp->pmac_write[reg] += inc; |
121 | } |
122 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
123 | { |
124 | if (mode & 0x0400) { |
125 | overwrite_write(dram[addr], d); |
126 | } else dram[addr] = d; |
34e243f1 |
127 | ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1; |
d5276282 |
128 | } |
129 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
130 | { |
131 | int inc = get_inc(mode); |
132 | ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d; |
133 | ssp->pmac_write[reg] += inc; |
e122fae6 |
134 | ssp->drc.iram_dirty = 1; |
d5276282 |
135 | } |
136 | |
137 | rPMC.v = ssp->pmac_write[reg]; |
138 | } |
139 | |
140 | |
892b1dd2 |
141 | // ----------------------------------------------------- |
142 | |
0b5e8296 |
143 | // 14 IRAM blocks |
df143b36 |
144 | static unsigned char iram_context_map[] = |
145 | { |
146 | 0, 0, 0, 0, 1, 0, 0, 0, // 04 |
147 | 0, 0, 0, 0, 0, 0, 2, 0, // 0e |
148 | 0, 0, 0, 0, 0, 3, 0, 4, // 15 17 |
149 | 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d |
150 | 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25 |
151 | 0, 0, 0, 0, 0, 0, 0, 0, |
152 | 0, 0,11, 0, 0,12, 0, 0, // 32 35 |
153 | 13,14, 0, 0, 0, 0, 0, 0 // 38 39 |
154 | }; |
155 | |
71bb1b7b |
156 | int ssp_get_iram_context(void) |
df143b36 |
157 | { |
158 | unsigned char *ir = (unsigned char *)svp->iram_rom; |
159 | int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1]; |
df143b36 |
160 | val1 = iram_context_map[(val>>1)&0x3f]; |
161 | |
5c129565 |
162 | if (val1 == 0) { |
2d2247c2 |
163 | elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC); |
df143b36 |
164 | //debug_dump2file(name, svp->iram_rom, 0x800); |
2d2247c2 |
165 | //exit(1); |
df143b36 |
166 | } |
df143b36 |
167 | return val1; |
168 | } |
169 | |
5d817c91 |
170 | // ----------------------------------------------------- |
0b5e8296 |
171 | |
5d817c91 |
172 | /* regs with known values */ |
173 | static struct |
174 | { |
175 | ssp_reg_t gr[8]; |
176 | unsigned char r[8]; |
ede7220f |
177 | unsigned int pmac_read[5]; |
178 | unsigned int pmac_write[5]; |
d5276282 |
179 | ssp_reg_t pmc; |
ede7220f |
180 | unsigned int emu_status; |
bad5731d |
181 | } known_regs; |
182 | |
183 | #define KRREG_X (1 << SSP_X) |
184 | #define KRREG_Y (1 << SSP_Y) |
185 | #define KRREG_A (1 << SSP_A) /* AH only */ |
186 | #define KRREG_ST (1 << SSP_ST) |
187 | #define KRREG_STACK (1 << SSP_STACK) |
188 | #define KRREG_PC (1 << SSP_PC) |
189 | #define KRREG_P (1 << SSP_P) |
190 | #define KRREG_PR0 (1 << 8) |
191 | #define KRREG_PR4 (1 << 12) |
192 | #define KRREG_AL (1 << 16) |
d5276282 |
193 | #define KRREG_PMCM (1 << 18) /* only mode word of PMC */ |
194 | #define KRREG_PMC (1 << 19) |
ede7220f |
195 | #define KRREG_PM0R (1 << 20) |
196 | #define KRREG_PM1R (1 << 21) |
197 | #define KRREG_PM2R (1 << 22) |
198 | #define KRREG_PM3R (1 << 23) |
199 | #define KRREG_PM4R (1 << 24) |
200 | #define KRREG_PM0W (1 << 25) |
201 | #define KRREG_PM1W (1 << 26) |
202 | #define KRREG_PM2W (1 << 27) |
203 | #define KRREG_PM3W (1 << 28) |
204 | #define KRREG_PM4W (1 << 29) |
bad5731d |
205 | |
206 | /* bitfield of known register values */ |
207 | static u32 known_regb = 0; |
208 | |
209 | /* known vals, which need to be flushed |
d5276282 |
210 | * (only ST, P, r0-r7, PMCx, PMxR, PMxW) |
bad5731d |
211 | * ST means flags are being held in ARM PSR |
89fea1e9 |
212 | * P means that it needs to be recalculated |
bad5731d |
213 | */ |
214 | static u32 dirty_regb = 0; |
5d817c91 |
215 | |
216 | /* known values of host regs. |
d274c33b |
217 | * -1 - unknown |
218 | * 000000-00ffff - 16bit value |
219 | * 100000-10ffff - base reg (r7) + 16bit val |
6e39239f |
220 | * 0r0000 - means reg (low) eq gr[r].h, r != AL |
5d817c91 |
221 | */ |
222 | static int hostreg_r[4]; |
223 | |
224 | static void hostreg_clear(void) |
225 | { |
226 | int i; |
227 | for (i = 0; i < 4; i++) |
228 | hostreg_r[i] = -1; |
229 | } |
230 | |
6e39239f |
231 | static void hostreg_sspreg_changed(int sspreg) |
5d817c91 |
232 | { |
233 | int i; |
234 | for (i = 0; i < 4; i++) |
6e39239f |
235 | if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1; |
5d817c91 |
236 | } |
237 | |
726bbb3e |
238 | |
ede7220f |
239 | #define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x] |
240 | #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x)) |
726bbb3e |
241 | |
ee9ee9fd |
242 | void tr_unhandled(void) |
6e39239f |
243 | { |
2d2247c2 |
244 | //FILE *f = fopen("tcache.bin", "wb"); |
245 | //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f); |
246 | //fclose(f); |
247 | elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1); |
248 | //exit(1); |
6e39239f |
249 | } |
250 | |
0e4d7ba5 |
251 | /* update P, if needed. Trashes r0 */ |
d274c33b |
252 | static void tr_flush_dirty_P(void) |
253 | { |
254 | // TODO: const regs |
bad5731d |
255 | if (!(dirty_regb & KRREG_P)) return; |
d274c33b |
256 | EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16 |
0e4d7ba5 |
257 | EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16 |
258 | EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15 |
259 | EOP_MUL(10, 0, 10); // mul r10, r0, r10 |
bad5731d |
260 | dirty_regb &= ~KRREG_P; |
0e4d7ba5 |
261 | hostreg_r[0] = -1; |
d274c33b |
262 | } |
263 | |
89fea1e9 |
264 | /* write dirty pr to host reg. Nothing is trashed */ |
265 | static void tr_flush_dirty_pr(int r) |
266 | { |
267 | int ror = 0, reg; |
6e39239f |
268 | |
89fea1e9 |
269 | if (!(dirty_regb & (1 << (r+8)))) return; |
270 | |
271 | switch (r&3) { |
272 | case 0: ror = 0; break; |
273 | case 1: ror = 24/2; break; |
274 | case 2: ror = 16/2; break; |
275 | } |
276 | reg = (r < 4) ? 8 : 9; |
277 | EOP_BIC_IMM(reg,reg,ror,0xff); |
278 | if (known_regs.r[r] != 0) |
279 | EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]); |
280 | dirty_regb &= ~(1 << (r+8)); |
281 | } |
282 | |
283 | /* write all dirty pr0-pr7 to host regs. Nothing is trashed */ |
284 | static void tr_flush_dirty_prs(void) |
5d817c91 |
285 | { |
286 | int i, ror = 0, reg; |
bad5731d |
287 | int dirty = dirty_regb >> 8; |
2385f273 |
288 | if ((dirty&7) == 7) { |
65c75cb0 |
289 | emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16)); |
2385f273 |
290 | dirty &= ~7; |
291 | } |
292 | if ((dirty&0x70) == 0x70) { |
65c75cb0 |
293 | emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16)); |
2385f273 |
294 | dirty &= ~0x70; |
295 | } |
5d817c91 |
296 | /* r0-r7 */ |
bad5731d |
297 | for (i = 0; dirty && i < 8; i++, dirty >>= 1) |
5d817c91 |
298 | { |
bad5731d |
299 | if (!(dirty&1)) continue; |
5d817c91 |
300 | switch (i&3) { |
301 | case 0: ror = 0; break; |
302 | case 1: ror = 24/2; break; |
303 | case 2: ror = 16/2; break; |
304 | } |
305 | reg = (i < 4) ? 8 : 9; |
306 | EOP_BIC_IMM(reg,reg,ror,0xff); |
bad5731d |
307 | if (known_regs.r[i] != 0) |
308 | EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]); |
5d817c91 |
309 | } |
bad5731d |
310 | dirty_regb &= ~0xff00; |
311 | } |
312 | |
89fea1e9 |
313 | /* write dirty pr and "forget" it. Nothing is trashed. */ |
314 | static void tr_release_pr(int r) |
315 | { |
316 | tr_flush_dirty_pr(r); |
317 | known_regb &= ~(1 << (r+8)); |
318 | } |
319 | |
6e39239f |
320 | /* fush ARM PSR to r6. Trashes r1 */ |
bad5731d |
321 | static void tr_flush_dirty_ST(void) |
322 | { |
323 | if (!(dirty_regb & KRREG_ST)) return; |
324 | EOP_BIC_IMM(6,6,0,0x0f); |
6e39239f |
325 | EOP_MRS(1); |
326 | EOP_ORR_REG_LSR(6,6,1,28); |
bad5731d |
327 | dirty_regb &= ~KRREG_ST; |
6e39239f |
328 | hostreg_r[1] = -1; |
329 | } |
330 | |
331 | /* inverse of above. Trashes r1 */ |
332 | static void tr_make_dirty_ST(void) |
333 | { |
334 | if (dirty_regb & KRREG_ST) return; |
335 | if (known_regb & KRREG_ST) { |
336 | int flags = 0; |
337 | if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8; |
338 | if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4; |
339 | EOP_MSR_IMM(4/2, flags); |
340 | } else { |
341 | EOP_MOV_REG_LSL(1, 6, 28); |
342 | EOP_MSR_REG(1); |
343 | hostreg_r[1] = -1; |
344 | } |
345 | dirty_regb |= KRREG_ST; |
bad5731d |
346 | } |
347 | |
348 | /* load 16bit val into host reg r0-r3. Nothing is trashed */ |
349 | static void tr_mov16(int r, int val) |
350 | { |
351 | if (hostreg_r[r] != val) { |
65c75cb0 |
352 | emith_move_r_imm(r, val); |
bad5731d |
353 | hostreg_r[r] = val; |
354 | } |
355 | } |
356 | |
357 | static void tr_mov16_cond(int cond, int r, int val) |
358 | { |
80599a42 |
359 | emith_op_imm(cond, 0, A_OP_MOV, r, val); |
a6fb500b |
360 | hostreg_r[r] = -1; |
5d817c91 |
361 | } |
362 | |
45883918 |
363 | /* trashes r1 */ |
ede7220f |
364 | static void tr_flush_dirty_pmcrs(void) |
365 | { |
366 | u32 i, val = (u32)-1; |
d5276282 |
367 | if (!(dirty_regb & 0x3ff80000)) return; |
ede7220f |
368 | |
d5276282 |
369 | if (dirty_regb & KRREG_PMC) { |
370 | val = known_regs.pmc.v; |
65c75cb0 |
371 | emith_move_r_imm(1, val); |
e122fae6 |
372 | EOP_STR_IMM(1,7,0x400+SSP_PMC*4); |
ede7220f |
373 | |
d5276282 |
374 | if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) { |
2d2247c2 |
375 | elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n"); |
d5276282 |
376 | tr_unhandled(); |
377 | } |
ede7220f |
378 | } |
379 | for (i = 0; i < 5; i++) |
380 | { |
d5276282 |
381 | if (dirty_regb & (1 << (20+i))) { |
ede7220f |
382 | if (val != known_regs.pmac_read[i]) { |
383 | val = known_regs.pmac_read[i]; |
65c75cb0 |
384 | emith_move_r_imm(1, val); |
ede7220f |
385 | } |
e122fae6 |
386 | EOP_STR_IMM(1,7,0x454+i*4); // pmac_read |
ede7220f |
387 | } |
d5276282 |
388 | if (dirty_regb & (1 << (25+i))) { |
ede7220f |
389 | if (val != known_regs.pmac_write[i]) { |
390 | val = known_regs.pmac_write[i]; |
65c75cb0 |
391 | emith_move_r_imm(1, val); |
ede7220f |
392 | } |
e122fae6 |
393 | EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write |
ede7220f |
394 | } |
395 | } |
d5276282 |
396 | dirty_regb &= ~0x3ff80000; |
e122fae6 |
397 | hostreg_r[1] = -1; |
ede7220f |
398 | } |
399 | |
0e4d7ba5 |
400 | /* read bank word to r0 (upper bits zero). Thrashes r1. */ |
5d817c91 |
401 | static void tr_bank_read(int addr) /* word addr 0-0x1ff */ |
402 | { |
bad5731d |
403 | int breg = 7; |
404 | if (addr > 0x7f) { |
405 | if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) { |
406 | EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1) |
407 | hostreg_r[1] = 0x100000|((addr&0x180)<<1); |
5d817c91 |
408 | } |
bad5731d |
409 | breg = 1; |
5d817c91 |
410 | } |
bad5731d |
411 | EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1] |
5d817c91 |
412 | hostreg_r[0] = -1; |
413 | } |
414 | |
415 | /* write r0 to bank. Trashes r1. */ |
416 | static void tr_bank_write(int addr) |
417 | { |
418 | int breg = 7; |
419 | if (addr > 0x7f) { |
d274c33b |
420 | if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) { |
5d817c91 |
421 | EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1) |
d274c33b |
422 | hostreg_r[1] = 0x100000|((addr&0x180)<<1); |
5d817c91 |
423 | } |
424 | breg = 1; |
425 | } |
b9c1d012 |
426 | EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1] |
5d817c91 |
427 | } |
428 | |
89fea1e9 |
429 | /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */ |
430 | static void tr_ptrr_mod(int r, int mod, int need_modulo, int count) |
5d817c91 |
431 | { |
a6fb500b |
432 | int modulo_shift = -1; /* unknown */ |
5d817c91 |
433 | |
434 | if (mod == 0) return; |
435 | |
436 | if (!need_modulo || mod == 1) // +! |
437 | modulo_shift = 8; |
bad5731d |
438 | else if (need_modulo && (known_regb & KRREG_ST)) { |
439 | modulo_shift = known_regs.gr[SSP_ST].h & 7; |
5d817c91 |
440 | if (modulo_shift == 0) modulo_shift = 8; |
441 | } |
442 | |
89fea1e9 |
443 | if (modulo_shift == -1) |
444 | { |
a6fb500b |
445 | int reg = (r < 4) ? 8 : 9; |
89fea1e9 |
446 | tr_release_pr(r); |
0e4d7ba5 |
447 | if (dirty_regb & KRREG_ST) { |
448 | // avoid flushing ARM flags |
449 | EOP_AND_IMM(1, 6, 0, 0x70); |
450 | EOP_SUB_IMM(1, 1, 0, 0x10); |
451 | EOP_AND_IMM(1, 1, 0, 0x70); |
452 | EOP_ADD_IMM(1, 1, 0, 0x10); |
453 | } else { |
454 | EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70 |
455 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80 |
456 | } |
89fea1e9 |
457 | EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4 |
458 | EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8 |
459 | EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000 |
460 | if (r&3) |
461 | EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8 |
462 | EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1 |
463 | if (mod == 2) |
464 | EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2 |
465 | else EOP_ADD_REG2_LSL(reg,reg,3,2); |
466 | EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32 |
467 | EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1 |
468 | hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1; |
a6fb500b |
469 | } |
470 | else if (known_regb & (1 << (r + 8))) |
471 | { |
472 | int modulo = (1 << modulo_shift) - 1; |
5d817c91 |
473 | if (mod == 2) |
89fea1e9 |
474 | known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo); |
475 | else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo); |
a6fb500b |
476 | } |
477 | else |
478 | { |
5d817c91 |
479 | int reg = (r < 4) ? 8 : 9; |
480 | int ror = ((r&3) + 1)*8 - (8 - modulo_shift); |
481 | EOP_MOV_REG_ROR(reg,reg,ror); |
482 | // {add|sub} reg, reg, #1<<shift |
89fea1e9 |
483 | EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift)); |
5d817c91 |
484 | EOP_MOV_REG_ROR(reg,reg,32-ror); |
485 | } |
486 | } |
487 | |
bad5731d |
488 | /* handle writes r0 to (rX). Trashes r1. |
489 | * fortunately we can ignore modulo increment modes for writes. */ |
0e4d7ba5 |
490 | static void tr_rX_write(int op) |
bad5731d |
491 | { |
492 | if ((op&3) == 3) |
493 | { |
494 | int mod = (op>>2) & 3; // direct addressing |
495 | tr_bank_write((op & 0x100) + mod); |
496 | } |
497 | else |
498 | { |
499 | int r = (op&3) | ((op>>6)&4); |
500 | if (known_regb & (1 << (r + 8))) { |
501 | tr_bank_write((op&0x100) | known_regs.r[r]); |
502 | } else { |
503 | int reg = (r < 4) ? 8 : 9; |
504 | int ror = ((4 - (r&3))*8) & 0x1f; |
505 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
506 | if (r >= 4) |
507 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
508 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
509 | else EOP_ADD_REG_LSL(1,7,1,1); |
510 | EOP_STRH_SIMPLE(0,1); // strh r0, [r1] |
511 | hostreg_r[1] = -1; |
512 | } |
89fea1e9 |
513 | tr_ptrr_mod(r, (op>>2) & 3, 0, 1); |
514 | } |
515 | } |
516 | |
517 | /* read (rX) to r0. Trashes r1-r3. */ |
518 | static void tr_rX_read(int r, int mod) |
519 | { |
520 | if ((r&3) == 3) |
521 | { |
522 | tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing |
523 | } |
524 | else |
525 | { |
526 | if (known_regb & (1 << (r + 8))) { |
6e39239f |
527 | tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]); |
89fea1e9 |
528 | } else { |
529 | int reg = (r < 4) ? 8 : 9; |
530 | int ror = ((4 - (r&3))*8) & 0x1f; |
531 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
532 | if (r >= 4) |
533 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
534 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
535 | else EOP_ADD_REG_LSL(1,7,1,1); |
536 | EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1] |
0e4d7ba5 |
537 | hostreg_r[0] = hostreg_r[1] = -1; |
89fea1e9 |
538 | } |
539 | tr_ptrr_mod(r, mod, 1, 1); |
bad5731d |
540 | } |
541 | } |
542 | |
0e4d7ba5 |
543 | /* read ((rX)) to r0. Trashes r1,r2. */ |
544 | static void tr_rX_read2(int op) |
545 | { |
546 | int r = (op&3) | ((op>>6)&4); // src |
547 | |
548 | if ((r&3) == 3) { |
549 | tr_bank_read((op&0x100) | ((op>>2)&3)); |
550 | } else if (known_regb & (1 << (r+8))) { |
551 | tr_bank_read((op&0x100) | known_regs.r[r]); |
552 | } else { |
553 | int reg = (r < 4) ? 8 : 9; |
554 | int ror = ((4 - (r&3))*8) & 0x1f; |
555 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
556 | if (r >= 4) |
557 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
558 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
559 | else EOP_ADD_REG_LSL(1,7,1,1); |
560 | EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1] |
561 | } |
562 | EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom |
563 | EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1 |
564 | EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1 |
565 | if ((r&3) == 3) { |
566 | tr_bank_write((op&0x100) | ((op>>2)&3)); |
567 | } else if (known_regb & (1 << (r+8))) { |
568 | tr_bank_write((op&0x100) | known_regs.r[r]); |
569 | } else { |
570 | EOP_STRH_SIMPLE(0,1); // strh r0, [r1] |
571 | hostreg_r[1] = -1; |
572 | } |
573 | EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2] |
574 | hostreg_r[0] = hostreg_r[2] = -1; |
575 | } |
89fea1e9 |
576 | |
2385f273 |
577 | // check if AL is going to be used later in block |
578 | static int tr_predict_al_need(void) |
579 | { |
580 | int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h; |
581 | |
582 | while (1) |
583 | { |
584 | op = PROGRAM(pc); |
585 | switch (op >> 9) |
586 | { |
587 | // ld d, s |
588 | case 0x00: |
589 | tmpv2 = (op >> 4) & 0xf; // dst |
590 | tmpv = op & 0xf; // src |
591 | if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, * |
592 | return 0; |
593 | break; |
594 | |
595 | // ld (ri), s |
596 | case 0x02: |
597 | // ld ri, s |
598 | case 0x0a: |
599 | // OP a, s |
600 | case 0x10: case 0x30: case 0x40: case 0x60: case 0x70: |
601 | tmpv = op & 0xf; // src |
602 | if (tmpv == SSP_AL) // OP *, AL |
603 | return 1; |
604 | break; |
605 | |
606 | case 0x04: |
607 | case 0x06: |
608 | case 0x14: |
609 | case 0x34: |
610 | case 0x44: |
611 | case 0x64: |
612 | case 0x74: pc++; break; |
613 | |
614 | // call cond, addr |
615 | case 0x24: |
616 | // bra cond, addr |
617 | case 0x26: |
618 | // mod cond, op |
619 | case 0x48: |
620 | // mpys? |
621 | case 0x1b: |
622 | // mpya (rj), (ri), b |
623 | case 0x4b: return 1; |
624 | |
625 | // mld (rj), (ri), b |
626 | case 0x5b: return 0; // cleared anyway |
627 | |
628 | // and A, * |
629 | case 0x50: |
630 | tmpv = op & 0xf; // src |
631 | if (tmpv == SSP_AL) return 1; |
632 | case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c: |
633 | return 0; |
634 | } |
635 | pc++; |
636 | } |
637 | } |
638 | |
639 | |
bad5731d |
640 | /* get ARM cond which would mean that SSP cond is satisfied. No trash. */ |
641 | static int tr_cond_check(int op) |
642 | { |
6e39239f |
643 | int f = (op & 0x100) >> 8; |
bad5731d |
644 | switch (op&0xf0) { |
645 | case 0x00: return A_COND_AL; /* always true */ |
646 | case 0x50: /* Z matches f(?) bit */ |
647 | if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE; |
648 | EOP_TST_IMM(6, 0, 4); |
649 | return f ? A_COND_NE : A_COND_EQ; |
650 | case 0x70: /* N matches f(?) bit */ |
651 | if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL; |
652 | EOP_TST_IMM(6, 0, 8); |
653 | return f ? A_COND_NE : A_COND_EQ; |
654 | default: |
2d2247c2 |
655 | elprintf(EL_ANOMALY, "unimplemented cond?\n"); |
6e39239f |
656 | tr_unhandled(); |
bad5731d |
657 | return 0; |
658 | } |
659 | } |
660 | |
661 | static int tr_neg_cond(int cond) |
662 | { |
663 | switch (cond) { |
2d2247c2 |
664 | case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1); |
bad5731d |
665 | case A_COND_EQ: return A_COND_NE; |
666 | case A_COND_NE: return A_COND_EQ; |
667 | case A_COND_MI: return A_COND_PL; |
668 | case A_COND_PL: return A_COND_MI; |
2d2247c2 |
669 | default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1); |
bad5731d |
670 | } |
671 | return 0; |
672 | } |
673 | |
ede7220f |
674 | static int tr_aop_ssp2arm(int op) |
675 | { |
676 | switch (op) { |
677 | case 1: return A_OP_SUB; |
678 | case 3: return A_OP_CMP; |
679 | case 4: return A_OP_ADD; |
680 | case 5: return A_OP_AND; |
681 | case 6: return A_OP_ORR; |
682 | case 7: return A_OP_EOR; |
683 | } |
684 | |
685 | tr_unhandled(); |
686 | return 0; |
687 | } |
688 | |
689 | // ----------------------------------------------------- |
690 | |
b9c1d012 |
691 | //@ r4: XXYY |
692 | //@ r5: A |
693 | //@ r6: STACK and emu flags |
694 | //@ r7: SSP context |
695 | //@ r10: P |
696 | |
bad5731d |
697 | // read general reg to r0. Trashes r1 |
d5276282 |
698 | static void tr_GR0_to_r0(int op) |
d274c33b |
699 | { |
700 | tr_mov16(0, 0xffff); |
701 | } |
702 | |
d5276282 |
703 | static void tr_X_to_r0(int op) |
d274c33b |
704 | { |
705 | if (hostreg_r[0] != (SSP_X<<16)) { |
706 | EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16 |
707 | hostreg_r[0] = SSP_X<<16; |
708 | } |
709 | } |
710 | |
d5276282 |
711 | static void tr_Y_to_r0(int op) |
d274c33b |
712 | { |
d274c33b |
713 | if (hostreg_r[0] != (SSP_Y<<16)) { |
714 | EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4 |
715 | hostreg_r[0] = SSP_Y<<16; |
716 | } |
717 | } |
718 | |
d5276282 |
719 | static void tr_A_to_r0(int op) |
d274c33b |
720 | { |
721 | if (hostreg_r[0] != (SSP_A<<16)) { |
722 | EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH |
723 | hostreg_r[0] = SSP_A<<16; |
724 | } |
725 | } |
726 | |
d5276282 |
727 | static void tr_ST_to_r0(int op) |
d274c33b |
728 | { |
729 | // VR doesn't need much accuracy here.. |
730 | EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4 |
731 | EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67 |
732 | hostreg_r[0] = -1; |
733 | } |
734 | |
d5276282 |
735 | static void tr_STACK_to_r0(int op) |
d274c33b |
736 | { |
737 | // 448 |
738 | EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29 |
739 | EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400 |
740 | EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048 |
741 | EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28 |
742 | EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1] |
743 | hostreg_r[0] = hostreg_r[1] = -1; |
744 | } |
745 | |
d5276282 |
746 | static void tr_PC_to_r0(int op) |
d274c33b |
747 | { |
bad5731d |
748 | tr_mov16(0, known_regs.gr[SSP_PC].h); |
d274c33b |
749 | } |
750 | |
d5276282 |
751 | static void tr_P_to_r0(int op) |
d274c33b |
752 | { |
753 | tr_flush_dirty_P(); |
754 | EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16 |
755 | hostreg_r[0] = -1; |
756 | } |
d5276282 |
757 | |
758 | static void tr_AL_to_r0(int op) |
ede7220f |
759 | { |
d5276282 |
760 | if (op == 0x000f) { |
761 | if (known_regb & KRREG_PMC) { |
762 | known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); |
763 | } else { |
764 | EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
765 | EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR); |
766 | EOP_STR_IMM(0,7,0x484); |
767 | } |
768 | } |
769 | |
770 | if (hostreg_r[0] != (SSP_AL<<16)) { |
771 | EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5 |
772 | hostreg_r[0] = SSP_AL<<16; |
773 | } |
ede7220f |
774 | } |
ede7220f |
775 | |
d5276282 |
776 | static void tr_PMX_to_r0(int reg) |
ede7220f |
777 | { |
ede7220f |
778 | if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) |
779 | { |
d5276282 |
780 | known_regs.pmac_read[reg] = known_regs.pmc.v; |
ede7220f |
781 | known_regs.emu_status &= ~SSP_PMC_SET; |
0336d643 |
782 | known_regb |= 1 << (20+reg); |
d5276282 |
783 | dirty_regb |= 1 << (20+reg); |
784 | return; |
ede7220f |
785 | } |
786 | |
d5276282 |
787 | if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg)))) |
ede7220f |
788 | { |
d5276282 |
789 | u32 pmcv = known_regs.pmac_read[reg]; |
790 | int mode = pmcv>>16; |
791 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
792 | |
ede7220f |
793 | if ((mode & 0xfff0) == 0x0800) |
794 | { |
ede7220f |
795 | EOP_LDR_IMM(1,7,0x488); // rom_ptr |
65c75cb0 |
796 | emith_move_r_imm(0, (pmcv&0xfffff)<<1); |
ede7220f |
797 | EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] |
d5276282 |
798 | known_regs.pmac_read[reg] += 1; |
ede7220f |
799 | } |
800 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
801 | { |
802 | int inc = get_inc(mode); |
ede7220f |
803 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
65c75cb0 |
804 | emith_move_r_imm(0, (pmcv&0xffff)<<1); |
ede7220f |
805 | EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] |
d5276282 |
806 | if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection |
ede7220f |
807 | { |
808 | int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08; |
809 | tr_flush_dirty_ST(); |
810 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
811 | EOP_TST_REG_SIMPLE(0,0); |
71bb1b7b |
812 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024 |
d5276282 |
813 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08 |
ede7220f |
814 | EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status |
815 | } |
d5276282 |
816 | known_regs.pmac_read[reg] += inc; |
ede7220f |
817 | } |
818 | else |
819 | { |
820 | tr_unhandled(); |
821 | } |
d5276282 |
822 | known_regs.pmc.v = known_regs.pmac_read[reg]; |
823 | //known_regb |= KRREG_PMC; |
824 | dirty_regb |= KRREG_PMC; |
825 | dirty_regb |= 1 << (20+reg); |
826 | hostreg_r[0] = hostreg_r[1] = -1; |
827 | return; |
828 | } |
ede7220f |
829 | |
d5276282 |
830 | known_regb &= ~KRREG_PMC; |
831 | dirty_regb &= ~KRREG_PMC; |
832 | known_regb &= ~(1 << (20+reg)); |
833 | dirty_regb &= ~(1 << (20+reg)); |
834 | |
835 | // call the C code to handle this |
836 | tr_flush_dirty_ST(); |
837 | //tr_flush_dirty_pmcrs(); |
838 | tr_mov16(0, reg); |
65c75cb0 |
839 | emith_call(ssp_pm_read); |
d5276282 |
840 | hostreg_clear(); |
841 | } |
842 | |
843 | static void tr_PM0_to_r0(int op) |
844 | { |
845 | tr_PMX_to_r0(0); |
846 | } |
847 | |
848 | static void tr_PM1_to_r0(int op) |
849 | { |
850 | tr_PMX_to_r0(1); |
851 | } |
852 | |
853 | static void tr_PM2_to_r0(int op) |
854 | { |
855 | tr_PMX_to_r0(2); |
856 | } |
857 | |
858 | static void tr_XST_to_r0(int op) |
859 | { |
860 | EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400 |
861 | EOP_LDRH_IMM(0, 0, SSP_XST*4+2); |
862 | } |
863 | |
864 | static void tr_PM4_to_r0(int op) |
865 | { |
866 | tr_PMX_to_r0(4); |
867 | } |
868 | |
869 | static void tr_PMC_to_r0(int op) |
870 | { |
871 | if (known_regb & KRREG_PMC) |
872 | { |
873 | if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { |
874 | known_regs.emu_status |= SSP_PMC_SET; |
875 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
876 | // do nothing - this is handled elsewhere |
877 | } else { |
878 | tr_mov16(0, known_regs.pmc.l); |
879 | known_regs.emu_status |= SSP_PMC_HAVE_ADDR; |
880 | } |
881 | } |
882 | else |
883 | { |
884 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
885 | tr_flush_dirty_ST(); |
886 | if (op != 0x000e) |
887 | EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4); |
888 | EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); |
889 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. |
890 | EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. |
891 | EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. |
892 | EOP_STR_IMM(1,7,0x484); |
893 | hostreg_r[0] = hostreg_r[1] = -1; |
ede7220f |
894 | } |
ede7220f |
895 | } |
896 | |
d274c33b |
897 | |
d5276282 |
898 | typedef void (tr_read_func)(int op); |
d274c33b |
899 | |
d5276282 |
900 | static tr_read_func *tr_read_funcs[16] = |
d274c33b |
901 | { |
902 | tr_GR0_to_r0, |
903 | tr_X_to_r0, |
904 | tr_Y_to_r0, |
905 | tr_A_to_r0, |
906 | tr_ST_to_r0, |
907 | tr_STACK_to_r0, |
908 | tr_PC_to_r0, |
d5276282 |
909 | tr_P_to_r0, |
910 | tr_PM0_to_r0, |
911 | tr_PM1_to_r0, |
912 | tr_PM2_to_r0, |
913 | tr_XST_to_r0, |
914 | tr_PM4_to_r0, |
915 | (tr_read_func *)tr_unhandled, |
916 | tr_PMC_to_r0, |
917 | tr_AL_to_r0 |
d274c33b |
918 | }; |
919 | |
920 | |
b9c1d012 |
921 | // write r0 to general reg handlers. Trashes r1 |
6e39239f |
922 | #define TR_WRITE_R0_TO_REG(reg) \ |
923 | { \ |
924 | hostreg_sspreg_changed(reg); \ |
925 | hostreg_r[0] = (reg)<<16; \ |
926 | if (const_val != -1) { \ |
927 | known_regs.gr[reg].h = const_val; \ |
928 | known_regb |= 1 << (reg); \ |
929 | } else { \ |
930 | known_regb &= ~(1 << (reg)); \ |
931 | } \ |
b9c1d012 |
932 | } |
933 | |
6e39239f |
934 | static void tr_r0_to_GR0(int const_val) |
b9c1d012 |
935 | { |
936 | // do nothing |
937 | } |
938 | |
6e39239f |
939 | static void tr_r0_to_X(int const_val) |
b9c1d012 |
940 | { |
941 | EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16 |
942 | EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16 |
943 | EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16 |
6e39239f |
944 | dirty_regb |= KRREG_P; // touching X or Y makes P dirty. |
945 | TR_WRITE_R0_TO_REG(SSP_X); |
b9c1d012 |
946 | } |
947 | |
6e39239f |
948 | static void tr_r0_to_Y(int const_val) |
b9c1d012 |
949 | { |
950 | EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16 |
951 | EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16 |
952 | EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16 |
bad5731d |
953 | dirty_regb |= KRREG_P; |
6e39239f |
954 | TR_WRITE_R0_TO_REG(SSP_Y); |
b9c1d012 |
955 | } |
956 | |
6e39239f |
957 | static void tr_r0_to_A(int const_val) |
b9c1d012 |
958 | { |
2385f273 |
959 | if (tr_predict_al_need()) { |
960 | EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16 |
961 | EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL |
962 | EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16 |
963 | } |
964 | else |
965 | EOP_MOV_REG_LSL(5, 0, 16); |
6e39239f |
966 | TR_WRITE_R0_TO_REG(SSP_A); |
b9c1d012 |
967 | } |
968 | |
6e39239f |
969 | static void tr_r0_to_ST(int const_val) |
b9c1d012 |
970 | { |
971 | // VR doesn't need much accuracy here.. |
972 | EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67 |
973 | EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK |
974 | EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4 |
6e39239f |
975 | TR_WRITE_R0_TO_REG(SSP_ST); |
b9c1d012 |
976 | hostreg_r[1] = -1; |
6e39239f |
977 | dirty_regb &= ~KRREG_ST; |
b9c1d012 |
978 | } |
979 | |
6e39239f |
980 | static void tr_r0_to_STACK(int const_val) |
b9c1d012 |
981 | { |
982 | // 448 |
983 | EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400 |
984 | EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048 |
d274c33b |
985 | EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28 |
b9c1d012 |
986 | EOP_STRH_SIMPLE(0, 1); // strh r0, [r1] |
d274c33b |
987 | EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29 |
b9c1d012 |
988 | hostreg_r[1] = -1; |
989 | } |
990 | |
6e39239f |
991 | static void tr_r0_to_PC(int const_val) |
b9c1d012 |
992 | { |
45883918 |
993 | /* |
994 | * do nothing - dispatcher will take care of this |
b9c1d012 |
995 | EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16 |
d274c33b |
996 | EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)] |
b9c1d012 |
997 | hostreg_r[1] = -1; |
45883918 |
998 | */ |
b9c1d012 |
999 | } |
1000 | |
d5276282 |
1001 | static void tr_r0_to_AL(int const_val) |
1002 | { |
1003 | EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 |
1004 | EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16 |
1005 | EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16 |
1006 | hostreg_sspreg_changed(SSP_AL); |
1007 | if (const_val != -1) { |
1008 | known_regs.gr[SSP_A].l = const_val; |
1009 | known_regb |= 1 << SSP_AL; |
1010 | } else |
1011 | known_regb &= ~(1 << SSP_AL); |
1012 | } |
1013 | |
1014 | static void tr_r0_to_PMX(int reg) |
1015 | { |
d5276282 |
1016 | if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) |
1017 | { |
1018 | known_regs.pmac_write[reg] = known_regs.pmc.v; |
1019 | known_regs.emu_status &= ~SSP_PMC_SET; |
1020 | known_regb |= 1 << (25+reg); |
1021 | dirty_regb |= 1 << (25+reg); |
1022 | return; |
1023 | } |
0b5e8296 |
1024 | |
d5276282 |
1025 | if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg)))) |
1026 | { |
1027 | int mode, addr; |
1028 | |
1029 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
1030 | |
1031 | mode = known_regs.pmac_write[reg]>>16; |
1032 | addr = known_regs.pmac_write[reg]&0xffff; |
1033 | if ((mode & 0x43ff) == 0x0018) // DRAM |
1034 | { |
1035 | int inc = get_inc(mode); |
1036 | if (mode & 0x0400) tr_unhandled(); |
1037 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
65c75cb0 |
1038 | emith_move_r_imm(2, addr << 1); |
d5276282 |
1039 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
1040 | known_regs.pmac_write[reg] += inc; |
1041 | } |
1042 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
1043 | { |
1044 | if (mode & 0x0400) tr_unhandled(); |
1045 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
65c75cb0 |
1046 | emith_move_r_imm(2, addr << 1); |
d5276282 |
1047 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
1048 | known_regs.pmac_write[reg] += (addr&1) ? 31 : 1; |
1049 | } |
1050 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
1051 | { |
1052 | int inc = get_inc(mode); |
1053 | EOP_LDR_IMM(1,7,0x48c); // iram_ptr |
65c75cb0 |
1054 | emith_move_r_imm(2, (addr&0x3ff) << 1); |
d5276282 |
1055 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
e122fae6 |
1056 | EOP_MOV_IMM(1,0,1); |
1057 | EOP_STR_IMM(1,7,0x494); // iram_dirty |
d5276282 |
1058 | known_regs.pmac_write[reg] += inc; |
1059 | } |
1060 | else |
1061 | tr_unhandled(); |
1062 | |
1063 | known_regs.pmc.v = known_regs.pmac_write[reg]; |
1064 | //known_regb |= KRREG_PMC; |
1065 | dirty_regb |= KRREG_PMC; |
1066 | dirty_regb |= 1 << (25+reg); |
1067 | hostreg_r[1] = hostreg_r[2] = -1; |
e122fae6 |
1068 | return; |
d5276282 |
1069 | } |
1070 | |
1071 | known_regb &= ~KRREG_PMC; |
1072 | dirty_regb &= ~KRREG_PMC; |
1073 | known_regb &= ~(1 << (25+reg)); |
1074 | dirty_regb &= ~(1 << (25+reg)); |
d5276282 |
1075 | |
1076 | // call the C code to handle this |
1077 | tr_flush_dirty_ST(); |
1078 | //tr_flush_dirty_pmcrs(); |
1079 | tr_mov16(1, reg); |
65c75cb0 |
1080 | emith_call(ssp_pm_write); |
d5276282 |
1081 | hostreg_clear(); |
1082 | } |
1083 | |
1084 | static void tr_r0_to_PM0(int const_val) |
1085 | { |
1086 | tr_r0_to_PMX(0); |
1087 | } |
1088 | |
1089 | static void tr_r0_to_PM1(int const_val) |
1090 | { |
1091 | tr_r0_to_PMX(1); |
1092 | } |
1093 | |
1094 | static void tr_r0_to_PM2(int const_val) |
1095 | { |
1096 | tr_r0_to_PMX(2); |
1097 | } |
1098 | |
1099 | static void tr_r0_to_PM4(int const_val) |
1100 | { |
1101 | tr_r0_to_PMX(4); |
1102 | } |
1103 | |
1104 | static void tr_r0_to_PMC(int const_val) |
1105 | { |
1106 | if ((known_regb & KRREG_PMC) && const_val != -1) |
1107 | { |
1108 | if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { |
1109 | known_regs.emu_status |= SSP_PMC_SET; |
1110 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
1111 | known_regs.pmc.h = const_val; |
1112 | } else { |
1113 | known_regs.emu_status |= SSP_PMC_HAVE_ADDR; |
1114 | known_regs.pmc.l = const_val; |
1115 | } |
1116 | } |
1117 | else |
1118 | { |
1119 | tr_flush_dirty_ST(); |
1120 | if (known_regb & KRREG_PMC) { |
65c75cb0 |
1121 | emith_move_r_imm(1, known_regs.pmc.v); |
d5276282 |
1122 | EOP_STR_IMM(1,7,0x400+SSP_PMC*4); |
1123 | known_regb &= ~KRREG_PMC; |
1124 | dirty_regb &= ~KRREG_PMC; |
1125 | } |
1126 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
1127 | EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400 |
1128 | EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); |
1129 | EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC] |
1130 | EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2); |
1131 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. |
1132 | EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. |
1133 | EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. |
1134 | EOP_STR_IMM(1,7,0x484); |
1135 | hostreg_r[1] = hostreg_r[2] = -1; |
1136 | } |
1137 | } |
1138 | |
6e39239f |
1139 | typedef void (tr_write_func)(int const_val); |
b9c1d012 |
1140 | |
d5276282 |
1141 | static tr_write_func *tr_write_funcs[16] = |
b9c1d012 |
1142 | { |
1143 | tr_r0_to_GR0, |
1144 | tr_r0_to_X, |
1145 | tr_r0_to_Y, |
1146 | tr_r0_to_A, |
1147 | tr_r0_to_ST, |
1148 | tr_r0_to_STACK, |
1149 | tr_r0_to_PC, |
d5276282 |
1150 | (tr_write_func *)tr_unhandled, |
1151 | tr_r0_to_PM0, |
1152 | tr_r0_to_PM1, |
1153 | tr_r0_to_PM2, |
1154 | (tr_write_func *)tr_unhandled, |
1155 | tr_r0_to_PM4, |
1156 | (tr_write_func *)tr_unhandled, |
1157 | tr_r0_to_PMC, |
1158 | tr_r0_to_AL |
b9c1d012 |
1159 | }; |
1160 | |
0e4d7ba5 |
1161 | static void tr_mac_load_XY(int op) |
1162 | { |
1163 | tr_rX_read(op&3, (op>>2)&3); // X |
1164 | EOP_MOV_REG_LSL(4, 0, 16); |
1165 | tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y |
1166 | EOP_ORR_REG_SIMPLE(4, 0); |
1167 | dirty_regb |= KRREG_P; |
1168 | hostreg_sspreg_changed(SSP_X); |
1169 | hostreg_sspreg_changed(SSP_Y); |
1170 | known_regb &= ~KRREG_X; |
1171 | known_regb &= ~KRREG_Y; |
1172 | } |
1173 | |
ede7220f |
1174 | // ----------------------------------------------------- |
1175 | |
ede7220f |
1176 | static int tr_detect_set_pm(unsigned int op, int *pc, int imm) |
0e4d7ba5 |
1177 | { |
ede7220f |
1178 | u32 pmcv, tmpv; |
1179 | if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0; |
1180 | |
1181 | // programming PMC: |
1182 | // ldi PMC, imm1 |
1183 | // ldi PMC, imm2 |
1184 | (*pc)++; |
1185 | pmcv = imm | (PROGRAM((*pc)++) << 16); |
d5276282 |
1186 | known_regs.pmc.v = pmcv; |
ede7220f |
1187 | known_regb |= KRREG_PMC; |
d5276282 |
1188 | dirty_regb |= KRREG_PMC; |
ede7220f |
1189 | known_regs.emu_status |= SSP_PMC_SET; |
71bb1b7b |
1190 | n_in_ops++; |
ede7220f |
1191 | |
1192 | // check for possible reg programming |
1193 | tmpv = PROGRAM(*pc); |
1194 | if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80) |
1195 | { |
1196 | int is_write = (tmpv & 0xff8f) == 0x80; |
1197 | int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7); |
1198 | if (reg > 4) tr_unhandled(); |
d5276282 |
1199 | if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled(); |
ede7220f |
1200 | known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv; |
1201 | known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); |
d5276282 |
1202 | dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); |
ede7220f |
1203 | known_regs.emu_status &= ~SSP_PMC_SET; |
1204 | (*pc)++; |
71bb1b7b |
1205 | n_in_ops++; |
ede7220f |
1206 | return 5; |
0e4d7ba5 |
1207 | } |
1208 | |
d5276282 |
1209 | tr_unhandled(); |
ede7220f |
1210 | return 4; |
1211 | } |
1212 | |
1213 | static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 }; |
1214 | |
1215 | static int tr_detect_pm0_block(unsigned int op, int *pc, int imm) |
1216 | { |
1217 | // ldi ST, 0 |
1218 | // ldi PM0, 0 |
1219 | // ldi PM0, 0 |
1220 | // ldi ST, 60h |
1221 | unsigned short *pp; |
1222 | if (op != 0x0840 || imm != 0) return 0; |
1223 | pp = PROGRAM_P(*pc); |
1224 | if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0; |
1225 | |
1226 | EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK |
1227 | EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600 |
1228 | hostreg_sspreg_changed(SSP_ST); |
1229 | known_regs.gr[SSP_ST].h = 0x60; |
1230 | known_regb |= 1 << SSP_ST; |
1231 | dirty_regb &= ~KRREG_ST; |
1232 | (*pc) += 3*2; |
71bb1b7b |
1233 | n_in_ops += 3; |
ede7220f |
1234 | return 4*2; |
0e4d7ba5 |
1235 | } |
5d817c91 |
1236 | |
d5276282 |
1237 | static int tr_detect_rotate(unsigned int op, int *pc, int imm) |
1238 | { |
1239 | // @ 3DA2 and 426A |
1240 | // ld PMC, (r3|00) |
1241 | // ld (r3|00), PMC |
1242 | // ld -, AL |
1243 | if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0; |
1244 | |
1245 | tr_bank_read(0); |
1246 | EOP_MOV_REG_LSL(0, 0, 4); |
1247 | EOP_ORR_REG_LSR(0, 0, 0, 16); |
1248 | tr_bank_write(0); |
1249 | (*pc) += 2; |
71bb1b7b |
1250 | n_in_ops += 2; |
d5276282 |
1251 | return 3; |
1252 | } |
1253 | |
ede7220f |
1254 | // ----------------------------------------------------- |
1255 | |
45883918 |
1256 | static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc) |
5d817c91 |
1257 | { |
0e4d7ba5 |
1258 | u32 tmpv, tmpv2, tmpv3; |
5d817c91 |
1259 | int ret = 0; |
bad5731d |
1260 | known_regs.gr[SSP_PC].h = *pc; |
5d817c91 |
1261 | |
e807ac75 |
1262 | switch (op >> 9) |
1263 | { |
1264 | // ld d, s |
f48f5e3b |
1265 | case 0x00: |
5d817c91 |
1266 | if (op == 0) { ret++; break; } // nop |
d274c33b |
1267 | tmpv = op & 0xf; // src |
1268 | tmpv2 = (op >> 4) & 0xf; // dst |
d274c33b |
1269 | if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P |
1270 | tr_flush_dirty_P(); |
1271 | EOP_MOV_REG_SIMPLE(5, 10); |
d5276282 |
1272 | hostreg_sspreg_changed(SSP_A); |
bad5731d |
1273 | known_regb &= ~(KRREG_A|KRREG_AL); |
d274c33b |
1274 | ret++; break; |
1275 | } |
d5276282 |
1276 | tr_read_funcs[tmpv](op); |
6e39239f |
1277 | tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1); |
45883918 |
1278 | if (tmpv2 == SSP_PC) { |
1279 | ret |= 0x10000; |
1280 | *end_cond = -A_COND_AL; |
1281 | } |
bad5731d |
1282 | ret++; break; |
1283 | |
1284 | // ld d, (ri) |
89fea1e9 |
1285 | case 0x01: { |
89fea1e9 |
1286 | int r = (op&3) | ((op>>6)&4); |
1287 | int mod = (op>>2)&3; |
1288 | tmpv = (op >> 4) & 0xf; // dst |
d5276282 |
1289 | ret = tr_detect_rotate(op, pc, imm); |
1290 | if (ret > 0) break; |
89fea1e9 |
1291 | if (tmpv != 0) |
2385f273 |
1292 | tr_rX_read(r, mod); |
1293 | else { |
1294 | int cnt = 1; |
1295 | while (PROGRAM(*pc) == op) { |
1296 | (*pc)++; cnt++; ret++; |
1297 | n_in_ops++; |
1298 | } |
1299 | tr_ptrr_mod(r, mod, 1, cnt); // skip |
1300 | } |
6e39239f |
1301 | tr_write_funcs[tmpv](-1); |
45883918 |
1302 | if (tmpv == SSP_PC) { |
1303 | ret |= 0x10000; |
1304 | *end_cond = -A_COND_AL; |
1305 | } |
89fea1e9 |
1306 | ret++; break; |
1307 | } |
bad5731d |
1308 | |
1309 | // ld (ri), s |
1310 | case 0x02: |
1311 | tmpv = (op >> 4) & 0xf; // src |
d5276282 |
1312 | tr_read_funcs[tmpv](op); |
0e4d7ba5 |
1313 | tr_rX_write(op); |
d274c33b |
1314 | ret++; break; |
f48f5e3b |
1315 | |
1316 | // ld a, adr |
1317 | case 0x03: |
5d817c91 |
1318 | tr_bank_read(op&0x1ff); |
6e39239f |
1319 | tr_r0_to_A(-1); |
5d817c91 |
1320 | ret++; break; |
1321 | |
b9c1d012 |
1322 | // ldi d, imm |
1323 | case 0x04: |
ede7220f |
1324 | tmpv = (op & 0xf0) >> 4; // dst |
1325 | ret = tr_detect_pm0_block(op, pc, imm); |
1326 | if (ret > 0) break; |
ede7220f |
1327 | ret = tr_detect_set_pm(op, pc, imm); |
1328 | if (ret > 0) break; |
0b5e8296 |
1329 | tr_mov16(0, imm); |
1330 | tr_write_funcs[tmpv](imm); |
45883918 |
1331 | if (tmpv == SSP_PC) { |
1332 | ret |= 0x10000; |
1333 | *jump_pc = imm; |
1334 | } |
0b5e8296 |
1335 | ret += 2; break; |
b9c1d012 |
1336 | |
bad5731d |
1337 | // ld d, ((ri)) |
0e4d7ba5 |
1338 | case 0x05: |
bad5731d |
1339 | tmpv2 = (op >> 4) & 0xf; // dst |
0e4d7ba5 |
1340 | tr_rX_read2(op); |
6e39239f |
1341 | tr_write_funcs[tmpv2](-1); |
45883918 |
1342 | if (tmpv2 == SSP_PC) { |
1343 | ret |= 0x10000; |
1344 | *end_cond = -A_COND_AL; |
1345 | } |
0e4d7ba5 |
1346 | ret += 3; break; |
b9c1d012 |
1347 | |
5d817c91 |
1348 | // ldi (ri), imm |
1349 | case 0x06: |
5d817c91 |
1350 | tr_mov16(0, imm); |
0e4d7ba5 |
1351 | tr_rX_write(op); |
a6fb500b |
1352 | ret += 2; break; |
f48f5e3b |
1353 | |
1354 | // ld adr, a |
1355 | case 0x07: |
d5276282 |
1356 | tr_A_to_r0(op); |
5d817c91 |
1357 | tr_bank_write(op&0x1ff); |
1358 | ret++; break; |
1359 | |
d274c33b |
1360 | // ld d, ri |
1361 | case 0x09: { |
bad5731d |
1362 | int r; |
d274c33b |
1363 | r = (op&3) | ((op>>6)&4); // src |
bad5731d |
1364 | tmpv2 = (op >> 4) & 0xf; // dst |
bad5731d |
1365 | if ((r&3) == 3) tr_unhandled(); |
d274c33b |
1366 | |
bad5731d |
1367 | if (known_regb & (1 << (r+8))) { |
1368 | tr_mov16(0, known_regs.r[r]); |
6e39239f |
1369 | tr_write_funcs[tmpv2](known_regs.r[r]); |
d274c33b |
1370 | } else { |
bad5731d |
1371 | int reg = (r < 4) ? 8 : 9; |
d274c33b |
1372 | if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr |
1373 | EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask> |
1374 | hostreg_r[0] = -1; |
6e39239f |
1375 | tr_write_funcs[tmpv2](-1); |
d274c33b |
1376 | } |
d274c33b |
1377 | ret++; break; |
1378 | } |
1379 | |
bad5731d |
1380 | // ld ri, s |
1381 | case 0x0a: { |
1382 | int r; |
1383 | r = (op&3) | ((op>>6)&4); // dst |
1384 | tmpv = (op >> 4) & 0xf; // src |
bad5731d |
1385 | if ((r&3) == 3) tr_unhandled(); |
1386 | |
1387 | if (known_regb & (1 << tmpv)) { |
1388 | known_regs.r[r] = known_regs.gr[tmpv].h; |
1389 | known_regb |= 1 << (r + 8); |
1390 | dirty_regb |= 1 << (r + 8); |
1391 | } else { |
1392 | int reg = (r < 4) ? 8 : 9; |
1393 | int ror = ((4 - (r&3))*8) & 0x1f; |
d5276282 |
1394 | tr_read_funcs[tmpv](op); |
bad5731d |
1395 | EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask> |
1396 | EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff |
1397 | EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl |
1398 | hostreg_r[0] = -1; |
1399 | known_regb &= ~(1 << (r+8)); |
1400 | dirty_regb &= ~(1 << (r+8)); |
1401 | } |
1402 | ret++; break; |
1403 | } |
1404 | |
5d817c91 |
1405 | // ldi ri, simm |
67c81ee2 |
1406 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: |
5d817c91 |
1407 | tmpv = (op>>8)&7; |
bad5731d |
1408 | known_regs.r[tmpv] = op; |
1409 | known_regb |= 1 << (tmpv + 8); |
5d817c91 |
1410 | dirty_regb |= 1 << (tmpv + 8); |
1411 | ret++; break; |
bad5731d |
1412 | |
a6fb500b |
1413 | // call cond, addr |
6e39239f |
1414 | case 0x24: { |
1415 | u32 *jump_op = NULL; |
a6fb500b |
1416 | tmpv = tr_cond_check(op); |
6e39239f |
1417 | if (tmpv != A_COND_AL) { |
1418 | jump_op = tcache_ptr; |
1419 | EOP_MOV_IMM(0, 0, 0); // placeholder for branch |
1420 | } |
1421 | tr_mov16(0, *pc); |
1422 | tr_r0_to_STACK(*pc); |
1423 | if (tmpv != A_COND_AL) { |
1424 | u32 *real_ptr = tcache_ptr; |
1425 | tcache_ptr = jump_op; |
1426 | EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2); |
1427 | tcache_ptr = real_ptr; |
1428 | } |
a6fb500b |
1429 | tr_mov16_cond(tmpv, 0, imm); |
45883918 |
1430 | if (tmpv != A_COND_AL) |
a6fb500b |
1431 | tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); |
6e39239f |
1432 | tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); |
ede7220f |
1433 | ret |= 0x10000; |
45883918 |
1434 | *end_cond = tmpv; |
1435 | *jump_pc = imm; |
a6fb500b |
1436 | ret += 2; break; |
6e39239f |
1437 | } |
a6fb500b |
1438 | |
bad5731d |
1439 | // ld d, (a) |
1440 | case 0x25: |
bad5731d |
1441 | tmpv2 = (op >> 4) & 0xf; // dst |
d5276282 |
1442 | tr_A_to_r0(op); |
bad5731d |
1443 | EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom |
1444 | EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1 |
1445 | EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0] |
1446 | hostreg_r[0] = hostreg_r[1] = -1; |
6e39239f |
1447 | tr_write_funcs[tmpv2](-1); |
45883918 |
1448 | if (tmpv2 == SSP_PC) { |
1449 | ret |= 0x10000; |
1450 | *end_cond = -A_COND_AL; |
1451 | } |
a6fb500b |
1452 | ret += 3; break; |
bad5731d |
1453 | |
1454 | // bra cond, addr |
a6fb500b |
1455 | case 0x26: |
bad5731d |
1456 | tmpv = tr_cond_check(op); |
1457 | tr_mov16_cond(tmpv, 0, imm); |
45883918 |
1458 | if (tmpv != A_COND_AL) |
bad5731d |
1459 | tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); |
6e39239f |
1460 | tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); |
ede7220f |
1461 | ret |= 0x10000; |
45883918 |
1462 | *end_cond = tmpv; |
1463 | *jump_pc = imm; |
a6fb500b |
1464 | ret += 2; break; |
bad5731d |
1465 | |
89fea1e9 |
1466 | // mod cond, op |
89fea1e9 |
1467 | case 0x48: { |
1468 | // check for repeats of this op |
1469 | tmpv = 1; // count |
1470 | while (PROGRAM(*pc) == op && (op & 7) != 6) { |
1471 | (*pc)++; tmpv++; |
71bb1b7b |
1472 | n_in_ops++; |
89fea1e9 |
1473 | } |
6e39239f |
1474 | if ((op&0xf0) != 0) // !always |
1475 | tr_make_dirty_ST(); |
1476 | |
89fea1e9 |
1477 | tmpv2 = tr_cond_check(op); |
1478 | switch (op & 7) { |
1479 | case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic) |
1480 | case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl |
1481 | case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg |
6e39239f |
1482 | case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31 |
1483 | EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31 |
89fea1e9 |
1484 | hostreg_r[1] = -1; break; // abs |
1485 | default: tr_unhandled(); |
1486 | } |
6e39239f |
1487 | |
1488 | hostreg_sspreg_changed(SSP_A); |
1489 | dirty_regb |= KRREG_ST; |
1490 | known_regb &= ~KRREG_ST; |
1491 | known_regb &= ~(KRREG_A|KRREG_AL); |
89fea1e9 |
1492 | ret += tmpv; break; |
1493 | } |
0e4d7ba5 |
1494 | |
bad5731d |
1495 | // mpys? |
1496 | case 0x1b: |
0e4d7ba5 |
1497 | tr_flush_dirty_P(); |
1498 | tr_mac_load_XY(op); |
1499 | tr_make_dirty_ST(); |
1500 | EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10 |
1501 | hostreg_sspreg_changed(SSP_A); |
1502 | known_regb &= ~(KRREG_A|KRREG_AL); |
1503 | dirty_regb |= KRREG_ST; |
1504 | ret++; break; |
bad5731d |
1505 | |
1506 | // mpya (rj), (ri), b |
1507 | case 0x4b: |
0e4d7ba5 |
1508 | tr_flush_dirty_P(); |
1509 | tr_mac_load_XY(op); |
1510 | tr_make_dirty_ST(); |
1511 | EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10 |
1512 | hostreg_sspreg_changed(SSP_A); |
1513 | known_regb &= ~(KRREG_A|KRREG_AL); |
1514 | dirty_regb |= KRREG_ST; |
1515 | ret++; break; |
bad5731d |
1516 | |
1517 | // mld (rj), (ri), b |
1518 | case 0x5b: |
0e4d7ba5 |
1519 | EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0 |
1520 | hostreg_sspreg_changed(SSP_A); |
1521 | known_regs.gr[SSP_A].v = 0; |
bad5731d |
1522 | known_regb |= (KRREG_A|KRREG_AL); |
0e4d7ba5 |
1523 | dirty_regb |= KRREG_ST; |
1524 | tr_mac_load_XY(op); |
1525 | ret++; break; |
1526 | |
1527 | // OP a, s |
1528 | case 0x10: |
1529 | case 0x30: |
1530 | case 0x40: |
1531 | case 0x50: |
1532 | case 0x60: |
1533 | case 0x70: |
1534 | tmpv = op & 0xf; // src |
1535 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1536 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
0e4d7ba5 |
1537 | if (tmpv == SSP_P) { |
1538 | tr_flush_dirty_P(); |
1539 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10 |
1540 | } else if (tmpv == SSP_A) { |
1541 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5 |
1542 | } else { |
d5276282 |
1543 | tr_read_funcs[tmpv](op); |
0e4d7ba5 |
1544 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16 |
1545 | } |
1546 | hostreg_sspreg_changed(SSP_A); |
1547 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1548 | dirty_regb |= KRREG_ST; |
1549 | ret++; break; |
1550 | |
1551 | // OP a, (ri) |
1552 | case 0x11: |
1553 | case 0x31: |
1554 | case 0x41: |
1555 | case 0x51: |
1556 | case 0x61: |
1557 | case 0x71: |
1558 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1559 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1560 | tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3); |
1561 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1562 | hostreg_sspreg_changed(SSP_A); |
1563 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1564 | dirty_regb |= KRREG_ST; |
1565 | ret++; break; |
1566 | |
1567 | // OP a, adr |
1568 | case 0x13: |
1569 | case 0x33: |
1570 | case 0x43: |
1571 | case 0x53: |
1572 | case 0x63: |
1573 | case 0x73: |
1574 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1575 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1576 | tr_bank_read(op&0x1ff); |
1577 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1578 | hostreg_sspreg_changed(SSP_A); |
1579 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1580 | dirty_regb |= KRREG_ST; |
1581 | ret++; break; |
1582 | |
1583 | // OP a, imm |
1584 | case 0x14: |
1585 | case 0x34: |
1586 | case 0x44: |
1587 | case 0x54: |
1588 | case 0x64: |
1589 | case 0x74: |
1590 | tmpv = (op & 0xf0) >> 4; |
1591 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1592 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1593 | tr_mov16(0, imm); |
1594 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1595 | hostreg_sspreg_changed(SSP_A); |
1596 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1597 | dirty_regb |= KRREG_ST; |
1598 | ret += 2; break; |
1599 | |
1600 | // OP a, ((ri)) |
1601 | case 0x15: |
1602 | case 0x35: |
1603 | case 0x45: |
1604 | case 0x55: |
1605 | case 0x65: |
1606 | case 0x75: |
1607 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1608 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1609 | tr_rX_read2(op); |
1610 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1611 | hostreg_sspreg_changed(SSP_A); |
1612 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1613 | dirty_regb |= KRREG_ST; |
1614 | ret += 3; break; |
1615 | |
1616 | // OP a, ri |
1617 | case 0x19: |
1618 | case 0x39: |
1619 | case 0x49: |
1620 | case 0x59: |
1621 | case 0x69: |
1622 | case 0x79: { |
1623 | int r; |
1624 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1625 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1626 | r = (op&3) | ((op>>6)&4); // src |
1627 | if ((r&3) == 3) tr_unhandled(); |
1628 | |
1629 | if (known_regb & (1 << (r+8))) { |
1630 | EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16 |
1631 | } else { |
1632 | int reg = (r < 4) ? 8 : 9; |
1633 | if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr |
1634 | EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask> |
1635 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1636 | hostreg_r[0] = -1; |
1637 | } |
1638 | hostreg_sspreg_changed(SSP_A); |
1639 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1640 | dirty_regb |= KRREG_ST; |
1641 | ret++; break; |
1642 | } |
1643 | |
1644 | // OP simm |
1645 | case 0x1c: |
1646 | case 0x3c: |
1647 | case 0x4c: |
1648 | case 0x5c: |
1649 | case 0x6c: |
1650 | case 0x7c: |
1651 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1652 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1653 | EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16 |
1654 | hostreg_sspreg_changed(SSP_A); |
1655 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1656 | dirty_regb |= KRREG_ST; |
bad5731d |
1657 | ret++; break; |
e807ac75 |
1658 | } |
1659 | |
71bb1b7b |
1660 | n_in_ops++; |
1661 | |
5d817c91 |
1662 | return ret; |
e807ac75 |
1663 | } |
1664 | |
45883918 |
1665 | static void emit_block_prologue(void) |
1666 | { |
1667 | // check if there are enough cycles.. |
1668 | // note: r0 must contain PC of current block |
1669 | EOP_CMP_IMM(11,0,0); // cmp r11, #0 |
65c75cb0 |
1670 | emith_jump_cond(A_COND_LE, ssp_drc_end); |
45883918 |
1671 | } |
1672 | |
1673 | /* cond: |
1674 | * >0: direct (un)conditional jump |
1675 | * <0: indirect jump |
1676 | */ |
1677 | static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc) |
1678 | { |
2d2247c2 |
1679 | if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; } |
45883918 |
1680 | EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles |
1681 | |
1682 | if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) { |
1683 | // indirect jump, or rom -> iram jump, must use dispatcher |
65c75cb0 |
1684 | emith_jump(ssp_drc_next); |
45883918 |
1685 | } |
1686 | else if (cond == A_COND_AL) { |
679af8a3 |
1687 | u32 *target = (pc < 0x400) ? |
1688 | ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] : |
1689 | ssp_block_table[pc]; |
45883918 |
1690 | if (target != NULL) |
65c75cb0 |
1691 | emith_jump(target); |
45883918 |
1692 | else { |
65c75cb0 |
1693 | int ops = emith_jump(ssp_drc_next); |
f8af9634 |
1694 | // cause the next block to be emitted over jump instruction |
1695 | tcache_ptr -= ops; |
45883918 |
1696 | } |
1697 | } |
1698 | else { |
679af8a3 |
1699 | u32 *target1 = (pc < 0x400) ? |
1700 | ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] : |
1701 | ssp_block_table[pc]; |
1702 | u32 *target2 = (end_pc < 0x400) ? |
1703 | ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] : |
1704 | ssp_block_table[end_pc]; |
45883918 |
1705 | if (target1 != NULL) |
65c75cb0 |
1706 | emith_jump_cond(cond, target1); |
45883918 |
1707 | if (target2 != NULL) |
65c75cb0 |
1708 | emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed |
f8af9634 |
1709 | #ifndef __EPOC32__ |
1710 | // emit patchable branches |
1711 | if (target1 == NULL) |
65c75cb0 |
1712 | emith_call_cond(cond, ssp_drc_next_patch); |
f8af9634 |
1713 | if (target2 == NULL) |
65c75cb0 |
1714 | emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch); |
f8af9634 |
1715 | #else |
1716 | // won't patch indirect jumps |
1717 | if (target1 == NULL || target2 == NULL) |
65c75cb0 |
1718 | emith_jump(ssp_drc_next); |
f8af9634 |
1719 | #endif |
45883918 |
1720 | } |
1721 | } |
1722 | |
71bb1b7b |
1723 | void *ssp_translate_block(int pc) |
726bbb3e |
1724 | { |
e807ac75 |
1725 | unsigned int op, op1, imm, ccount = 0; |
5c129565 |
1726 | unsigned int *block_start; |
45883918 |
1727 | int ret, end_cond = A_COND_AL, jump_pc = -1; |
5c129565 |
1728 | |
2d2247c2 |
1729 | //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2); |
f8af9634 |
1730 | |
5c129565 |
1731 | block_start = tcache_ptr; |
bad5731d |
1732 | known_regb = 0; |
1733 | dirty_regb = KRREG_P; |
d5276282 |
1734 | known_regs.emu_status = 0; |
5d817c91 |
1735 | hostreg_clear(); |
5c129565 |
1736 | |
1737 | emit_block_prologue(); |
726bbb3e |
1738 | |
e807ac75 |
1739 | for (; ccount < 100;) |
726bbb3e |
1740 | { |
1741 | op = PROGRAM(pc++); |
1742 | op1 = op >> 9; |
e807ac75 |
1743 | imm = (u32)-1; |
5c129565 |
1744 | |
e807ac75 |
1745 | if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6) |
1746 | imm = PROGRAM(pc++); // immediate |
5c129565 |
1747 | |
45883918 |
1748 | ret = translate_op(op, &pc, imm, &end_cond, &jump_pc); |
e807ac75 |
1749 | if (ret <= 0) |
1750 | { |
2d2247c2 |
1751 | elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1); |
1752 | //exit(1); |
892b1dd2 |
1753 | } |
ede7220f |
1754 | |
45883918 |
1755 | ccount += ret & 0xffff; |
1756 | if (ret & 0x10000) break; |
726bbb3e |
1757 | } |
5c129565 |
1758 | |
45883918 |
1759 | if (ccount >= 100) { |
1760 | end_cond = A_COND_AL; |
1761 | jump_pc = pc; |
65c75cb0 |
1762 | emith_move_r_imm(0, pc); |
45883918 |
1763 | } |
0b5e8296 |
1764 | |
89fea1e9 |
1765 | tr_flush_dirty_prs(); |
1766 | tr_flush_dirty_ST(); |
ede7220f |
1767 | tr_flush_dirty_pmcrs(); |
45883918 |
1768 | emit_block_epilogue(ccount, end_cond, jump_pc, pc); |
726bbb3e |
1769 | |
f4bb5d6b |
1770 | if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) { |
f8af9634 |
1771 | elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n"); |
726bbb3e |
1772 | fflush(stdout); |
1773 | exit(1); |
1774 | } |
1775 | |
1776 | // stats |
1777 | nblocks++; |
2d2247c2 |
1778 | //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4, |
1779 | // (double)(tcache_ptr - tcache) / (double)n_in_ops); |
df143b36 |
1780 | |
5d817c91 |
1781 | #ifdef DUMP_BLOCK |
5c129565 |
1782 | { |
1783 | FILE *f = fopen("tcache.bin", "wb"); |
1784 | fwrite(tcache, 1, (tcache_ptr - tcache)*4, f); |
1785 | fclose(f); |
1786 | } |
43e6eaad |
1787 | printf("dumped tcache.bin\n"); |
5c129565 |
1788 | exit(0); |
1789 | #endif |
259ed0ea |
1790 | |
553c3eaa |
1791 | #ifdef ARM |
1792 | cache_flush_d_inval_i(tcache, tcache_ptr); |
1793 | #endif |
259ed0ea |
1794 | |
5c129565 |
1795 | return block_start; |
726bbb3e |
1796 | } |
1797 | |
1798 | |
1799 | |
1800 | // ----------------------------------------------------- |
1801 | |
fad24893 |
1802 | static void ssp1601_state_load(void) |
1803 | { |
1804 | ssp->drc.iram_dirty = 1; |
1805 | ssp->drc.iram_context = 0; |
1806 | } |
1807 | |
679af8a3 |
1808 | void ssp1601_dyn_exit(void) |
1809 | { |
1810 | free(ssp_block_table); |
1811 | free(ssp_block_table_iram); |
1812 | ssp_block_table = ssp_block_table_iram = NULL; |
1813 | |
1814 | drc_cmn_cleanup(); |
1815 | } |
1816 | |
e807ac75 |
1817 | int ssp1601_dyn_startup(void) |
726bbb3e |
1818 | { |
41397701 |
1819 | drc_cmn_init(); |
1820 | |
679af8a3 |
1821 | ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS); |
1822 | if (ssp_block_table == NULL) |
1823 | return -1; |
1824 | ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS); |
1825 | if (ssp_block_table_iram == NULL) { |
1826 | free(ssp_block_table); |
1827 | return -1; |
1828 | } |
1829 | |
1830 | memset(tcache, 0, DRC_TCACHE_SIZE); |
f4bb5d6b |
1831 | tcache_ptr = (void *)tcache; |
726bbb3e |
1832 | |
fad24893 |
1833 | PicoLoadStateHook = ssp1601_state_load; |
1834 | |
f5d1115f |
1835 | n_in_ops = 0; |
d5276282 |
1836 | #ifdef ARM |
1837 | // hle'd blocks |
1ca2ea4f |
1838 | ssp_block_table[0x800/2] = (void *) ssp_hle_800; |
1839 | ssp_block_table[0x902/2] = (void *) ssp_hle_902; |
72f63cf0 |
1840 | ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x030/2] = (void *) ssp_hle_07_030; |
1841 | ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x036/2] = (void *) ssp_hle_07_036; |
1842 | ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x6d6/2] = (void *) ssp_hle_07_6d6; |
1843 | ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x12c/2] = (void *) ssp_hle_11_12c; |
1844 | ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x384/2] = (void *) ssp_hle_11_384; |
1845 | ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x38a/2] = (void *) ssp_hle_11_38a; |
d5276282 |
1846 | #endif |
1847 | |
726bbb3e |
1848 | return 0; |
1849 | } |
1850 | |
1851 | |
1852 | void ssp1601_dyn_reset(ssp1601_t *ssp) |
1853 | { |
71bb1b7b |
1854 | ssp1601_reset(ssp); |
1855 | ssp->drc.iram_dirty = 1; |
1856 | ssp->drc.iram_context = 0; |
1857 | // must do this here because ssp is not available @ startup() |
1858 | ssp->drc.ptr_rom = (u32) Pico.rom; |
1859 | ssp->drc.ptr_iram_rom = (u32) svp->iram_rom; |
1860 | ssp->drc.ptr_dram = (u32) svp->dram; |
1ca2ea4f |
1861 | ssp->drc.ptr_btable = (u32) ssp_block_table; |
1862 | ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram; |
45883918 |
1863 | |
1864 | // prevent new versions of IRAM from appearing |
1865 | memset(svp->iram_rom, 0, 0x800); |
726bbb3e |
1866 | } |
1867 | |
f8af9634 |
1868 | |
726bbb3e |
1869 | void ssp1601_dyn_run(int cycles) |
1870 | { |
b9c1d012 |
1871 | if (ssp->emu_status & SSP_WAIT_MASK) return; |
b9c1d012 |
1872 | |
fad24893 |
1873 | #ifdef DUMP_BLOCK |
1874 | ssp_translate_block(DUMP_BLOCK >> 1); |
1875 | #endif |
1876 | #ifdef ARM |
71bb1b7b |
1877 | ssp_drc_entry(cycles); |
fad24893 |
1878 | #endif |
726bbb3e |
1879 | } |
1880 | |