random fixes (root path and mmap svp tcache)
[picodrive.git] / pico / carthw / svp / ssp16.h
CommitLineData
d4ca252d 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3// (c) Copyright 2008, Grazvydas "notaz" Ignotas
4// Free for non-commercial use.
5
6// For commercial use, separate licencing terms must be obtained.
7
f8ef8ff7 8
9// register names
10enum {
11 SSP_GR0, SSP_X, SSP_Y, SSP_A,
12 SSP_ST, SSP_STACK, SSP_PC, SSP_P,
13 SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
14 SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
15};
16
17typedef union
18{
19 unsigned int v;
20 struct {
21 unsigned short l;
22 unsigned short h;
23 };
24} ssp_reg_t;
25
26typedef struct
27{
28 union {
5c129565 29 unsigned short RAM[256*2]; // 000 2 internal RAM banks
f8ef8ff7 30 struct {
31 unsigned short RAM0[256];
32 unsigned short RAM1[256];
33 };
34 };
5c129565 35 ssp_reg_t gr[16]; // 400 general registers
f8ef8ff7 36 union {
5c129565 37 unsigned char r[8]; // 440 BANK pointers
f8ef8ff7 38 struct {
39 unsigned char r0[4];
40 unsigned char r1[4];
41 };
42 };
5c129565 43 unsigned short stack[6]; // 448
44 unsigned int pmac_read[6]; // 454 read modes/addrs for PM0-PM5
45 unsigned int pmac_write[6]; // 46c write ...
f8ef8ff7 46 //
30752975 47 #define SSP_PMC_HAVE_ADDR 0x0001 // address written to PMAC, waiting for mode
48 #define SSP_PMC_SET 0x0002 // PMAC is set
d26dc685 49 #define SSP_WAIT_PM0 0x2000 // bit1 in PM0
b9c1d012 50 #define SSP_WAIT_30FE06 0x4000 // ssp tight loops on 30FE06 to become non-zero
6e39239f 51 #define SSP_WAIT_30FE08 0x8000 // same for 30FE06
d26dc685 52 #define SSP_WAIT_MASK 0xe000
5c129565 53 unsigned int emu_status; // 484
d274c33b 54 /* used by recompiler only: */
e122fae6 55 struct {
56 unsigned int ptr_rom; // 488
57 unsigned int ptr_iram_rom; // 48c
58 unsigned int ptr_dram; // 490
59 unsigned int iram_dirty; // 494
71bb1b7b 60 unsigned int iram_context; // 498
61 unsigned int ptr_btable; // 49c
62 unsigned int ptr_btable_iram; // 4a0
63 unsigned int tmp0; // 4a4
45883918 64 unsigned int tmp1; // 4a8
65 unsigned int tmp2; // 4ac
e122fae6 66 } drc;
f8ef8ff7 67} ssp1601_t;
68
69
70void ssp1601_reset(ssp1601_t *ssp);
017512f2 71void ssp1601_run(int cycles);
f8ef8ff7 72