[picodrive.git] / pico / carthw / svp / stub_arm.S

@ vim:filetype=armasm

@ Compiler helper functions and some SVP HLE code

@ (c) Copyright 2008, Grazvydas "notaz" Ignotas
@ Free for non-commercial use.

.global ssp_drc_entry
.global ssp_drc_next
.global ssp_drc_next_patch
.global ssp_drc_end
.global ssp_hle_800
.global ssp_hle_902
.global ssp_hle_07_030
.global ssp_hle_07_036
.global ssp_hle_07_6d6
.global ssp_hle_11_12c
.global ssp_hle_11_384
.global ssp_hle_11_38a

.text
.align 2

@       SSP_GR0, SSP_X,     SSP_Y,   SSP_A,
@       SSP_ST,  SSP_STACK, SSP_PC,  SSP_P,
@       SSP_PM0, SSP_PM1,   SSP_PM2, SSP_XST,
@       SSP_PM4, SSP_gr13,  SSP_PMC, SSP_AL

@ register map:
@ r4:  XXYY
@ r5:  A
@ r6:  STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
@ r7:  SSP context
@ r8:  r0-r2 (.210)
@ r9:  r4-r6 (.654)
@ r10: P
@ r11: cycles
@ r12: tmp


#define SSP_OFFS_GR         0x400
#define SSP_PC                  6
#define SSP_P                   7
#define SSP_PM0                 8
#define SSP_PMC                14
#define SSP_OFFS_PM_WRITE   0x46c // pmac_write[]
#define SSP_OFFS_EMUSTAT    0x484 // emu_status
#define SSP_OFFS_IRAM_ROM   0x48c // ptr_iram_rom
#define SSP_OFFS_DRAM       0x490 // ptr_dram
#define SSP_OFFS_IRAM_DIRTY 0x494
#define SSP_OFFS_IRAM_CTX   0x498 // iram_context
#define SSP_OFFS_BLTAB      0x49c // block_table
#define SSP_OFFS_BLTAB_IRAM 0x4a0
#define SSP_OFFS_TMP0       0x4a4 // for entry PC
#define SSP_OFFS_TMP1       0x4a8
#define SSP_OFFS_TMP2       0x4ac
#define SSP_WAIT_PM0       0x2000


.macro ssp_drc_do_next patch_jump=0
.if \patch_jump
    str     lr, [r7, #SSP_OFFS_TMP2]		@ jump instr. (actually call) address + 4
.endif
    mov     r0, r0, lsl #16
    mov     r0, r0, lsr #16
    str     r0, [r7, #SSP_OFFS_TMP0]
    cmp     r0, #0x400
    blt     0f @ ssp_de_iram

    ldr     r2, [r7, #SSP_OFFS_BLTAB]
    ldr     r2, [r2, r0, lsl #2]
    tst     r2, r2
.if \patch_jump
    bne     ssp_drc_do_patch
.else
    bxne    r2
.endif
    bl      ssp_translate_block
    mov     r2, r0
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    ldr     r1, [r7, #SSP_OFFS_BLTAB]
    str     r2, [r1, r0, lsl #2]
.if \patch_jump
    b       ssp_drc_do_patch
.else
    bx      r2
.endif

0: @ ssp_de_iram:
    ldr     r1, [r7, #SSP_OFFS_IRAM_DIRTY]
    tst     r1, r1
    ldreq   r1, [r7, #SSP_OFFS_IRAM_CTX]
    beq     1f @ ssp_de_iram_ctx

    bl      ssp_get_iram_context
    mov     r1, #0
    str     r1, [r7, #SSP_OFFS_IRAM_DIRTY]
    mov     r1, r0
    str     r1, [r7, #SSP_OFFS_IRAM_CTX]
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    
1: @ ssp_de_iram_ctx:
    ldr     r2, [r7, #SSP_OFFS_BLTAB_IRAM]
    add     r2, r2, r1, lsl #12			@ block_tab_iram + iram_context * 0x800/2*4
    add     r1, r2, r0, lsl #2
    ldr     r2, [r1]
    tst     r2, r2
.if \patch_jump
    bne     ssp_drc_do_patch
.else
    bxne    r2
.endif
    str     r1, [r7, #SSP_OFFS_TMP1]
    bl      ssp_translate_block
    mov     r2, r0
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    ldr     r1, [r7, #SSP_OFFS_TMP1]		@ &block_table_iram[iram_context][rPC]
    str     r2, [r1]
.if \patch_jump
    b       ssp_drc_do_patch
.else
    bx      r2
.endif
.endm @ ssp_drc_do_next


ssp_drc_entry:
    stmfd   sp!, {r4-r11, lr}
    mov     r11, r0
ssp_regfile_load:
    ldr     r7, =ssp
    ldr     r7, [r7]
    add     r2, r7, #0x400
    add     r2, r2, #4
    ldmia   r2, {r3,r4,r5,r6,r8}
    mov     r3, r3, lsr #16
    mov     r3, r3, lsl #16
    orr     r4, r3, r4, lsr #16         @ XXYY

    and     r8, r8, #0x0f0000
    mov     r8, r8, lsl #13             @ sss0 *
    and     r9, r6, #0x670000
    tst     r6,     #0x80000000
    orrne   r8, r8, #0x8
    tst     r6,     #0x20000000
    orrne   r8, r8, #0x4                @ sss0 *           NZ..
    orr     r6, r8, r9, lsr #12         @ sss0 * .uu. .lll NZ..

    ldr     r8, [r7, #0x440]            @ r0-r2
    ldr     r9, [r7, #0x444]            @ r4-r6
    ldr     r10,[r7, #(0x400+SSP_P*4)]  @ P

    ldr     r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
    mov     r0, r0, lsr #16


ssp_drc_next:
    ssp_drc_do_next 0


ssp_drc_next_patch:
    ssp_drc_do_next 1

ssp_drc_do_patch:
    ldr     r1, [r7, #SSP_OFFS_TMP2]	@ jump instr. (actually call) address + 4
    subs    r12,r2, r1
    moveq   r3,     #0xe1000000
    orreq   r3, r3, #0x00a00000		@ nop
    streq   r3, [r1, #-4]
    beq     ssp_drc_dp_end

    cmp     r12,#4
    ldreq   r3, [r1]
    addeq   r3, r3, #1
    streq   r3, [r1, #-4]               @ move the other cond up
    moveq   r3,     #0xe1000000
    orreq   r3, r3, #0x00a00000
    streq   r3, [r1]                    @ fill it's place with nop
    beq     ssp_drc_dp_end

    ldr     r3, [r1, #-4]
    sub     r12,r12,#4
    mov     r3, r3, lsr #24
    bic     r3, r3, #1			@ L bit
    orr     r3, r3, r12,lsl #6
    mov     r3, r3, ror #8              @ patched branch instruction
    str     r3, [r1, #-4]               @ patch the bl/b to jump directly to another handler

ssp_drc_dp_end:
    str     r2, [r7, #SSP_OFFS_TMP1]
    sub     r0, r1, #4
    add     r1, r1, #4
    bl      cache_flush_d_inval_i
    ldr     r2, [r7, #SSP_OFFS_TMP1]
    ldr     r0, [r7, #SSP_OFFS_TMP0]
    bx      r2


ssp_drc_end:
    mov     r0, r0, lsl #16
    str     r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]

ssp_regfile_store:
    str     r10,[r7, #(0x400+SSP_P*4)]  @ P
    str     r8, [r7, #0x440]            @ r0-r2
    str     r9, [r7, #0x444]            @ r4-r6

    mov     r9, r6, lsr #13
    and     r9, r9, #(7<<16)            @ STACK
    mov     r3, r6, lsl #28
    msr     cpsr_flg, r3                @ to to ARM PSR
    and     r6, r6, #0x670
    mov     r6, r6, lsl #12
    orrmi   r6, r6, #0x80000000         @ N
    orreq   r6, r6, #0x20000000         @ Z

    mov     r3, r4, lsl #16             @ Y
    mov     r2, r4, lsr #16
    mov     r2, r2, lsl #16             @ X
    add     r8, r7, #0x400
    add     r8, r8, #4
    stmia   r8, {r2,r3,r5,r6,r9}

    mov     r0, r11
    ldmfd   sp!, {r4-r11, lr}
    bx      lr


@ ld      A, PM0
@ andi    2
@ bra     z=1, gloc_0800
ssp_hle_800:
    ldr     r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
    ldr     r1, [r7, #SSP_OFFS_EMUSTAT]
    tst     r0, #0x20000
    orreq   r1, r1,  #SSP_WAIT_PM0
    subeq   r11,r11, #1024
    streq   r1, [r7, #SSP_OFFS_EMUSTAT]
    mov     r0,     #0x400
    beq     ssp_drc_end
    orrne   r0, r0, #0x004
    b       ssp_drc_next


.macro hle_flushflags
    bic     r6, r6, #0xf
    mrs     r1, cpsr
    orr     r6, r6, r1, lsr #28 
.endm

.macro hle_popstack
    sub     r6, r6, #0x20000000
    add     r1, r7, #0x400
    add     r1, r1, #0x048			@ stack
    add     r1, r1, r6, lsr #28
    ldrh    r0, [r1]
.endm

ssp_hle_902:
    cmp     r11, #0
    ble     ssp_drc_end

    add     r1, r7, #0x200
    ldrh    r0, [r1]
    ldr     r3, [r7, #SSP_OFFS_IRAM_ROM]
    add     r2, r3, r0, lsl #1			@ (r7|00)
    ldrh    r0, [r2], #2
    mov     r5, r5, lsl #16
    mov     r5, r5, lsr #16
    bic     r0, r0, #0xfc00
    add     r3, r3, r0, lsl #1 			@ IRAM dest
    ldrh    r12,[r2], #2			@ length
    bic     r3, r3, #3				@ always seen aligned
@    orr     r5, r5, #0x08000000
@    orr     r5, r5, #0x00880000
@    sub     r5, r5, r12, lsl #16
    bic     r6, r6, #0xf
    add     r12,r12,#1
    mov     r0, #1
    str     r0, [r7, #SSP_OFFS_IRAM_DIRTY]
    sub     r11,r11,r12,lsl #1
    sub     r11,r11,r12				@ -= length*3

ssp_hle_902_loop:
    ldrh    r0, [r2], #2
    ldrh    r1, [r2], #2
    subs    r12,r12,#2
    orr     r0, r0, r1, lsl #16
    str     r0, [r3], #4
    bgt     ssp_hle_902_loop

    tst     r12, #1
    ldrneh  r0, [r2], #2
    strneh  r0, [r3], #2

    ldr     r0, [r7, #SSP_OFFS_IRAM_ROM]
    add     r1, r7, #0x200
    sub     r2, r2, r0
    mov     r2, r2, lsr #1
    strh    r2, [r1]				@ (r7|00)

    sub     r0, r3, r0
    mov     r0, r0, lsr #1
    orr     r0, r0, #0x08000000
    orr     r0, r0, #0x001c8000
    str     r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
    str     r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]

    hle_popstack
    subs    r11,r11,#16				@ timeslice is likely to end
    ble     ssp_drc_end
    b       ssp_drc_next


@ this one is car rendering related
.macro hle_11_12c_mla offs_in
    ldrsh   r5, [r7, #(\offs_in+0)]
    ldrsh   r0, [r7, #(\offs_in+2)]
    ldrsh   r1, [r7, #(\offs_in+4)]
    mul     r5, r2, r5
    ldrsh   r12,[r7, #(\offs_in+6)]
    mla     r5, r3, r0, r5
    mla     r5, r4, r1, r5
    add     r5, r5, r12,lsl #11

    movs    r5, r5, lsr #13
    add     r1, r7, r8, lsr #23
    strh    r5, [r1]
    add     r8, r8, #(1<<24)
.endm

ssp_hle_11_12c:
    cmp     r11, #0
    ble     ssp_drc_end

    mov     r0, #0
    bl      ssp_pm_read
    mov     r4, r0

    mov     r0, #0
    bl      ssp_pm_read
    mov     r5, r0

    mov     r0, #0
    bl      ssp_pm_read

    mov     r2, r4, lsl #16
    mov     r2, r2, asr #15			@ (r7|00) << 1
    mov     r3, r5, lsl #16
    mov     r3, r3, asr #15			@ (r7|01) << 1
    mov     r4, r0, lsl #16
    mov     r4, r4, asr #15			@ (r7|10) << 1

    bic     r8, r8, #0xff
    mov     r8, r8, ror #16

    hle_11_12c_mla 0x20
    hle_11_12c_mla 0x28
    hle_11_12c_mla 0x30

    mov     r8, r8, ror #16
    orr     r8, r8, #0x1c
@    hle_flushflags
    hle_popstack
    sub     r11,r11,#33
    b       ssp_drc_next


ssp_hle_11_384:
    mov     r3, #2
    b       ssp_hle_11_38x

ssp_hle_11_38a:
    mov     r3, #3		@ r5

ssp_hle_11_38x:
    cmp     r11, #0
    ble     ssp_drc_end

    mov     r2, #0		@ EFh, EEh
    mov     r1, #1		@ r4
    add     r0, r7, #0x1c0	@ r0 (based)

ssp_hle_11_38x_loop:
    ldrh    r5, [r0], #2
    ldr     r12,[r7, #0x224]
    mov     r5, r5, lsl #16
    eor     r5, r5, r5, asr #31
    add     r5, r5, r5, lsr #31	@ abs(r5)
    cmp     r5, r12,lsl #16
    orrpl   r2, r2, r1,lsl #16	@ EFh |= r4

    ldrh    r5, [r0, #2]!
    ldr     r12,[r7, #0x220]
    cmp     r5, r12,lsr #16
    orrpl   r2, r2, r1,lsl #16	@ EFh |= r4

    ldr     r12,[r7, #0x1e8]
    add     r0, r0, #2
    mov     r12,r12,lsl #16
    cmp     r5, r12,lsr #16
    orrmi   r2, r2, r1

    mov     r1, r1, lsl #1
    subs    r3, r3, #1
    bpl     ssp_hle_11_38x_loop

    str     r2, [r7, #0x1dc]
    sub     r0, r0, r7
    bic     r8, r8, #0xff
    orr     r8, r8, r0, lsr #1
    bic     r9, r9, #0xff
    orr     r9, r9, r1

@    hle_flushflags
    hle_popstack
    sub     r11,r11,#(9+30*4)
    b       ssp_drc_next


ssp_hle_07_6d6:
    cmp     r11, #0
    ble     ssp_drc_end

    ldr     r1, [r7, #0x20c]
    and     r0, r8, #0xff	@ assuming alignment
    add     r0, r7, r0, lsl #1
    mov     r2, r1, lsr #16
    mov     r1, r1, lsl #16	@ 106h << 16
    mov     r2, r2, lsl #16	@ 107h << 16

ssp_hle_07_6d6_loop:
    ldr     r5, [r0], #4
    tst     r5, r5
    bmi     ssp_hle_07_6d6_end
    mov     r5, r5, lsl #16
    cmp     r5, r1
    movmi   r1, r5
    cmp     r5, r2
    sub     r11,r11,#16
    bmi     ssp_hle_07_6d6_loop
    mov     r2, r5
    b       ssp_hle_07_6d6_loop

ssp_hle_07_6d6_end:
    sub     r0, r0, r7
    mov     r0, r0, lsr #1
    bic     r8, r8, #0xff
    orr     r8, r8, r0
    orr     r1, r2, r1, lsr #16
    str     r1, [r7, #0x20c]
    hle_popstack
    sub     r11,r11,#6
    b       ssp_drc_next


ssp_hle_07_030:
    ldrh    r0, [r7]
    mov     r0, r0, lsl #4
    orr     r0, r0, r0, lsr #16
    strh    r0, [r7]
    sub     r11,r11,#3

ssp_hle_07_036:
    ldr     r1, [r7, #0x1e0]	@ F1h F0h
    rsb     r5, r1, r1, lsr #16
    mov     r5, r5, lsl #16	@ AL not needed
    cmp     r5, #(4<<16)
    sub     r11,r11,#5
    bmi     hle_07_036_ending2
    ldr     r1, [r7, #0x1dc]	@ EEh
    cmp     r5, r1, lsl #16
    sub     r11,r11,#5
    bpl     hle_07_036_ret

    mov     r0, r5, lsr #16
    add     r1, r7, #0x100
    strh    r0, [r1, #0xea]	@ F5h
    ldr     r0, [r7, #0x1e0]	@ F0h
    and     r0, r0, #3
    strh    r0, [r1, #0xf0]	@ F8h
    add     r2, r0, #0xc0	@ r2
    add     r2, r7, r2, lsl #1
    ldrh    r2, [r2]
    ldr     r0, [r7]
    mov     r1, #4
    and     r0, r0, r2
    bl      ssp_pm_write
    @ will handle PMC later
    ldr     r0, [r7, #0x1e8]	@ F5h << 16
    ldr     r1, [r7, #0x1f0]	@ F8h
    ldr     r2, [r7, #0x1d4]	@ EAh
    sub     r0, r0, #(3<<16)
    add     r0, r0, r1, lsl #16
    sub     r0, r2, r0, asr #18
    and     r0, r0, #0x7f
    rsbs    r0, r0, #0x78	@ length
    ble     hle_07_036_ending1

    sub     r11,r11,r0

    @ copy part
    ldr     r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
    ldr     r2, [r7, #SSP_OFFS_DRAM]
    mov     r1, r1, lsl #16
    add     r1, r2, r1, lsr #15	@ addr (based)
    ldrh    r2, [r7, #0]	@ pattern
    ldrh    r3, [r7, #6]	@ mode

    mov     r12,    #0x4000
    orr     r12,r12,#0x0018
    subs    r12,r3, r12
    subnes  r12,r12,#0x0400
    blne    tr_unhandled

    orr     r2, r2, r2, lsl #16
    tst     r3, #0x400
    bne     hle_07_036_ovrwr

hle_07_036_no_ovrwr:
    tst     r1, #2
    strneh  r2, [r1], #0x3e	@ align
    subne   r0, r0, #1
    subs    r0, r0, #4
    blt     hle_07_036_l2

hle_07_036_l1:
    subs    r0, r0, #4
    str     r2, [r1], #0x40
    str     r2, [r1], #0x40
    bge     hle_07_036_l1

hle_07_036_l2:
    tst     r0, #2
    strne   r2, [r1], #0x40
    tst     r0, #1
    strneh  r2, [r1], #2
    b       hle_07_036_end_copy

hle_07_036_ovrwr:
    tst     r2,     #0x000f
    orreq   r12,r12,#0x000f
    tst     r2,     #0x00f0
    orreq   r12,r12,#0x00f0
    tst     r2,     #0x0f00
    orreq   r12,r12,#0x0f00
    tst     r2,     #0xf000
    orreq   r12,r12,#0xf000
    orrs    r12,r12,r12,lsl #16
    beq     hle_07_036_no_ovrwr

    tst     r1, #2
    beq     hle_07_036_ol0
    ldrh    r3, [r1]
    and     r3, r3, r12
    orr     r3, r3, r2
    strh    r3, [r1], #0x3e	@ align
    sub     r0, r0, #1

hle_07_036_ol0:
    subs    r0, r0, #2
    blt     hle_07_036_ol2

hle_07_036_ol1:
    subs    r0, r0, #2
    ldr     r3, [r1]
    and     r3, r3, r12
    orr     r3, r3, r2
    str     r3, [r1], #0x40
    bge     hle_07_036_ol1

hle_07_036_ol2:
    tst     r0, #1
    ldrneh  r3, [r1]
    andne   r3, r3, r12
    orrne   r3, r3, r2
    strneh  r3, [r1], #2

hle_07_036_end_copy:
    ldr     r2, [r7, #SSP_OFFS_DRAM]
    add     r3, r7, #0x400
    sub     r0, r1, r2          @ new addr
    mov     r0, r0, lsr #1
    strh    r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)

hle_07_036_ending1:
    ldr     r0, [r7, #0x1e0]	@ F1h << 16
    add     r0, r0, #(1<<16)
    and     r0, r0, #(3<<16)
    add     r0, r0, #(0xc4<<16)
    bic     r8, r8, #0xff0000
    orr     r8, r8, r0		@ r2
    add     r0, r7, r0, lsr #15
    ldrh    r0, [r0]
    ldr     r2, [r7]
    and     r0, r0, r2
    movs    r5, r0, lsl #16

    ldr     r1, [r7, #4]	@ new mode
    add     r2, r7, #0x400
    strh    r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
    mov     r1, #4
    bl      ssp_pm_write
    sub     r11,r11,#35

hle_07_036_ret:
    hle_popstack
    b       ssp_drc_next

hle_07_036_ending2:
    sub     r11,r11,#3
    movs    r5, r5, lsl #1
    bmi     hle_07_036_ret
    mov     r0, #0x87
    b       ssp_drc_next	@ let the dispatcher finish this
Commit	Line	Data
e807ac75	1	@ vim:filetype=armasm
e807ac75	2
65ca3034	3	@ Compiler helper functions and some SVP HLE code
	4
	5	@ (c) Copyright 2008, Grazvydas "notaz" Ignotas
	6	@ Free for non-commercial use.
	7
71bb1b7b	8	.global ssp_drc_entry
71bb1b7b	9	.global ssp_drc_next
45883918	10	.global ssp_drc_next_patch
45883918	11	.global ssp_drc_end
d5276282	12	.global ssp_hle_800
f5d1115f	13	.global ssp_hle_902
ee9ee9fd	14	.global ssp_hle_07_030
	15	.global ssp_hle_07_036
	16	.global ssp_hle_07_6d6
	17	.global ssp_hle_11_12c
	18	.global ssp_hle_11_384
	19	.global ssp_hle_11_38a
e807ac75	20
e807ac75	21	.text
	22	.align 2
	23
e807ac75	24	@ SSP_GR0, SSP_X, SSP_Y, SSP_A,
	25	@ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
	26	@ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
	27	@ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
	28
	29	@ register map:
	30	@ r4: XXYY
	31	@ r5: A
b9c1d012	32	@ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
e807ac75	33	@ r7: SSP context
5d817c91	34	@ r8: r0-r2 (.210)
5d817c91	35	@ r9: r4-r6 (.654)
e807ac75	36	@ r10: P
e807ac75	37	@ r11: cycles
f8af9634	38	@ r12: tmp
e807ac75	39
e807ac75	40
45883918	41	#define SSP_OFFS_GR 0x400
	42	#define SSP_PC 6
	43	#define SSP_P 7
	44	#define SSP_PM0 8
f5d1115f	45	#define SSP_PMC 14
f5d1115f	46	#define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
45883918	47	#define SSP_OFFS_EMUSTAT 0x484 // emu_status
f5d1115f	48	#define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
ee9ee9fd	49	#define SSP_OFFS_DRAM 0x490 // ptr_dram
45883918	50	#define SSP_OFFS_IRAM_DIRTY 0x494
	51	#define SSP_OFFS_IRAM_CTX 0x498 // iram_context
	52	#define SSP_OFFS_BLTAB 0x49c // block_table
	53	#define SSP_OFFS_BLTAB_IRAM 0x4a0
	54	#define SSP_OFFS_TMP0 0x4a4 // for entry PC
	55	#define SSP_OFFS_TMP1 0x4a8
	56	#define SSP_OFFS_TMP2 0x4ac
	57	#define SSP_WAIT_PM0 0x2000
	58
	59
	60	.macro ssp_drc_do_next patch_jump=0
	61	.if \patch_jump
	62	str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
	63	.endif
	64	mov r0, r0, lsl #16
	65	mov r0, r0, lsr #16
	66	str r0, [r7, #SSP_OFFS_TMP0]
	67	cmp r0, #0x400
	68	blt 0f @ ssp_de_iram
	69
	70	ldr r2, [r7, #SSP_OFFS_BLTAB]
	71	ldr r2, [r2, r0, lsl #2]
	72	tst r2, r2
	73	.if \patch_jump
	74	bne ssp_drc_do_patch
	75	.else
	76	bxne r2
	77	.endif
	78	bl ssp_translate_block
	79	mov r2, r0
	80	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
	81	ldr r1, [r7, #SSP_OFFS_BLTAB]
	82	str r2, [r1, r0, lsl #2]
	83	.if \patch_jump
	84	b ssp_drc_do_patch
	85	.else
	86	bx r2
	87	.endif
	88
	89	0: @ ssp_de_iram:
	90	ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
	91	tst r1, r1
	92	ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
	93	beq 1f @ ssp_de_iram_ctx
	94
	95	bl ssp_get_iram_context
	96	mov r1, #0
	97	str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
	98	mov r1, r0
	99	str r1, [r7, #SSP_OFFS_IRAM_CTX]
	100	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
	101
	102	1: @ ssp_de_iram_ctx:
	103	ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
	104	add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
	105	add r1, r2, r0, lsl #2
	106	ldr r2, [r1]
	107	tst r2, r2
	108	.if \patch_jump
	109	bne ssp_drc_do_patch
	110	.else
	111	bxne r2
	112	.endif
	113	str r1, [r7, #SSP_OFFS_TMP1]
114	bl ssp_translate_block
115	mov r2, r0
116	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
117	ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
118	str r2, [r1]
119	.if \patch_jump
120	b ssp_drc_do_patch
121	.else
122	bx r2
123	.endif
124	.endm @ ssp_drc_do_next
125
126
127	ssp_drc_entry:
128	stmfd sp!, {r4-r11, lr}
129	mov r11, r0
71bb1b7b	130	ssp_regfile_load:
e807ac75	131	ldr r7, =ssp
	132	ldr r7, [r7]
	133	add r2, r7, #0x400
	134	add r2, r2, #4
	135	ldmia r2, {r3,r4,r5,r6,r8}
	136	mov r3, r3, lsr #16
	137	mov r3, r3, lsl #16
	138	orr r4, r3, r4, lsr #16 @ XXYY
b9c1d012	139
	140	and r8, r8, #0x0f0000
	141	mov r8, r8, lsl #13 @ sss0 *
	142	and r9, r6, #0x670000
	143	tst r6, #0x80000000
	144	orrne r8, r8, #0x8
	145	tst r6, #0x20000000
	146	orrne r8, r8, #0x4 @ sss0 * NZ..
a6fb500b	147	orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
b9c1d012	148
e807ac75	149	ldr r8, [r7, #0x440] @ r0-r2
e807ac75	150	ldr r9, [r7, #0x444] @ r4-r6
45883918	151	ldr r10,[r7, #(0x400+SSP_P*4)] @ P
	152
	153	ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
	154	mov r0, r0, lsr #16
	155
	156
	157	ssp_drc_next:
	158	ssp_drc_do_next 0
	159
	160
	161	ssp_drc_next_patch:
	162	ssp_drc_do_next 1
	163
	164	ssp_drc_do_patch:
	165	ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
	166	subs r12,r2, r1
	167	moveq r3, #0xe1000000
	168	orreq r3, r3, #0x00a00000 @ nop
	169	streq r3, [r1, #-4]
	170	beq ssp_drc_dp_end
	171
	172	cmp r12,#4
	173	ldreq r3, [r1]
	174	addeq r3, r3, #1
	175	streq r3, [r1, #-4] @ move the other cond up
	176	moveq r3, #0xe1000000
	177	orreq r3, r3, #0x00a00000
	178	streq r3, [r1] @ fill it's place with nop
	179	beq ssp_drc_dp_end
	180
	181	ldr r3, [r1, #-4]
	182	sub r12,r12,#4
	183	mov r3, r3, lsr #24
	184	bic r3, r3, #1 @ L bit
	185	orr r3, r3, r12,lsl #6
	186	mov r3, r3, ror #8 @ patched branch instruction
f8af9634	187	str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
45883918	188
	189	ssp_drc_dp_end:
	190	str r2, [r7, #SSP_OFFS_TMP1]
	191	sub r0, r1, #4
	192	add r1, r1, #4
84100c0f	193	bl cache_flush_d_inval_i
45883918	194	ldr r2, [r7, #SSP_OFFS_TMP1]
	195	ldr r0, [r7, #SSP_OFFS_TMP0]
	196	bx r2
e807ac75	197
e807ac75	198
45883918	199	ssp_drc_end:
	200	mov r0, r0, lsl #16
	201	str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
	202
71bb1b7b	203	ssp_regfile_store:
45883918	204	str r10,[r7, #(0x400+SSP_P*4)] @ P
e807ac75	205	str r8, [r7, #0x440] @ r0-r2
e807ac75	206	str r9, [r7, #0x444] @ r4-r6
b9c1d012	207
b9c1d012	208	mov r9, r6, lsr #13
e807ac75	209	and r9, r9, #(7<<16) @ STACK
b9c1d012	210	mov r3, r6, lsl #28
	211	msr cpsr_flg, r3 @ to to ARM PSR
	212	and r6, r6, #0x670
	213	mov r6, r6, lsl #12
	214	orrmi r6, r6, #0x80000000 @ N
	215	orreq r6, r6, #0x20000000 @ Z
	216
e807ac75	217	mov r3, r4, lsl #16 @ Y
	218	mov r2, r4, lsr #16
	219	mov r2, r2, lsl #16 @ X
	220	add r8, r7, #0x400
	221	add r8, r8, #4
	222	stmia r8, {r2,r3,r5,r6,r9}
71bb1b7b	223
71bb1b7b	224	mov r0, r11
	225	ldmfd sp!, {r4-r11, lr}
	226	bx lr
	227
	228
d5276282	229
	230	@ ld A, PM0
	231	@ andi 2
	232	@ bra z=1, gloc_0800
	233	ssp_hle_800:
d5276282	234	ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
71bb1b7b	235	ldr r1, [r7, #SSP_OFFS_EMUSTAT]
d5276282	236	tst r0, #0x20000
f5d1115f	237	orreq r1, r1, #SSP_WAIT_PM0
45883918	238	subeq r11,r11, #1024
71bb1b7b	239	streq r1, [r7, #SSP_OFFS_EMUSTAT]
45883918	240	mov r0, #0x400
	241	beq ssp_drc_end
	242	orrne r0, r0, #0x004
45883918	243	b ssp_drc_next
d5276282	244
e807ac75	245
ee9ee9fd	246	.macro hle_flushflags
	247	bic r6, r6, #0xf
	248	mrs r1, cpsr
	249	orr r6, r6, r1, lsr #28
	250	.endm
	251
	252	.macro hle_popstack
	253	sub r6, r6, #0x20000000
	254	add r1, r7, #0x400
	255	add r1, r1, #0x048 @ stack
	256	add r1, r1, r6, lsr #28
	257	ldrh r0, [r1]
	258	.endm
	259
f5d1115f	260	ssp_hle_902:
	261	cmp r11, #0
	262	ble ssp_drc_end
	263
	264	add r1, r7, #0x200
	265	ldrh r0, [r1]
	266	ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
	267	add r2, r3, r0, lsl #1 @ (r7\|00)
	268	ldrh r0, [r2], #2
	269	mov r5, r5, lsl #16
	270	mov r5, r5, lsr #16
	271	bic r0, r0, #0xfc00
	272	add r3, r3, r0, lsl #1 @ IRAM dest
	273	ldrh r12,[r2], #2 @ length
	274	bic r3, r3, #3 @ always seen aligned
	275	@ orr r5, r5, #0x08000000
	276	@ orr r5, r5, #0x00880000
	277	@ sub r5, r5, r12, lsl #16
	278	bic r6, r6, #0xf
	279	add r12,r12,#1
	280	mov r0, #1
	281	str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
	282	sub r11,r11,r12,lsl #1
	283	sub r11,r11,r12 @ -= length*3
	284
	285	ssp_hle_902_loop:
	286	ldrh r0, [r2], #2
	287	ldrh r1, [r2], #2
	288	subs r12,r12,#2
	289	orr r0, r0, r1, lsl #16
	290	str r0, [r3], #4
	291	bgt ssp_hle_902_loop
	292
	293	tst r12, #1
	294	ldrneh r0, [r2], #2
	295	strneh r0, [r3], #2
	296
	297	ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
	298	add r1, r7, #0x200
	299	sub r2, r2, r0
	300	mov r2, r2, lsr #1
	301	strh r2, [r1] @ (r7\|00)
	302
	303	sub r0, r3, r0
	304	mov r0, r0, lsr #1
	305	orr r0, r0, #0x08000000
	306	orr r0, r0, #0x001c8000
	307	str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
	308	str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
	309
ee9ee9fd	310	hle_popstack
f5d1115f	311	subs r11,r11,#16 @ timeslice is likely to end
	312	ble ssp_drc_end
	313	b ssp_drc_next
	314
ee9ee9fd	315
	316	@ this one is car rendering related
	317	.macro hle_11_12c_mla offs_in
	318	ldrsh r5, [r7, #(\offs_in+0)]
	319	ldrsh r0, [r7, #(\offs_in+2)]
	320	ldrsh r1, [r7, #(\offs_in+4)]
	321	mul r5, r2, r5
	322	ldrsh r12,[r7, #(\offs_in+6)]
	323	mla r5, r3, r0, r5
	324	mla r5, r4, r1, r5
	325	add r5, r5, r12,lsl #11
	326
	327	movs r5, r5, lsr #13
	328	add r1, r7, r8, lsr #23
	329	strh r5, [r1]
	330	add r8, r8, #(1<<24)
	331	.endm
	332
	333	ssp_hle_11_12c:
	334	cmp r11, #0
	335	ble ssp_drc_end
	336
	337	mov r0, #0
	338	bl ssp_pm_read
	339	mov r4, r0
	340
	341	mov r0, #0
	342	bl ssp_pm_read
	343	mov r5, r0
	344
	345	mov r0, #0
	346	bl ssp_pm_read
	347
	348	mov r2, r4, lsl #16
	349	mov r2, r2, asr #15 @ (r7\|00) << 1
	350	mov r3, r5, lsl #16
	351	mov r3, r3, asr #15 @ (r7\|01) << 1
	352	mov r4, r0, lsl #16
	353	mov r4, r4, asr #15 @ (r7\|10) << 1
	354
	355	bic r8, r8, #0xff
	356	mov r8, r8, ror #16
	357
	358	hle_11_12c_mla 0x20
	359	hle_11_12c_mla 0x28
	360	hle_11_12c_mla 0x30
	361
	362	mov r8, r8, ror #16
	363	orr r8, r8, #0x1c
	364	@ hle_flushflags
	365	hle_popstack
	366	sub r11,r11,#33
	367	b ssp_drc_next
	368
	369
	370	ssp_hle_11_384:
	371	mov r3, #2
	372	b ssp_hle_11_38x
	373
	374	ssp_hle_11_38a:
	375	mov r3, #3 @ r5
	376
	377	ssp_hle_11_38x:
	378	cmp r11, #0
379	ble ssp_drc_end
380
381	mov r2, #0 @ EFh, EEh
382	mov r1, #1 @ r4
383	add r0, r7, #0x1c0 @ r0 (based)
384
385	ssp_hle_11_38x_loop:
386	ldrh r5, [r0], #2
387	ldr r12,[r7, #0x224]
388	mov r5, r5, lsl #16
389	eor r5, r5, r5, asr #31
390	add r5, r5, r5, lsr #31 @ abs(r5)
391	cmp r5, r12,lsl #16
392	orrpl r2, r2, r1,lsl #16 @ EFh \|= r4
393
394	ldrh r5, [r0, #2]!
395	ldr r12,[r7, #0x220]
396	cmp r5, r12,lsr #16
397	orrpl r2, r2, r1,lsl #16 @ EFh \|= r4
398
399	ldr r12,[r7, #0x1e8]
400	add r0, r0, #2
401	mov r12,r12,lsl #16
402	cmp r5, r12,lsr #16
403	orrmi r2, r2, r1
404
405	mov r1, r1, lsl #1
406	subs r3, r3, #1
407	bpl ssp_hle_11_38x_loop
408
409	str r2, [r7, #0x1dc]
410	sub r0, r0, r7
411	bic r8, r8, #0xff
412	orr r8, r8, r0, lsr #1
413	bic r9, r9, #0xff
414	orr r9, r9, r1
415
416	@ hle_flushflags
417	hle_popstack
418	sub r11,r11,#(9+30*4)
419	b ssp_drc_next
420
421
422	ssp_hle_07_6d6:
423	cmp r11, #0
424	ble ssp_drc_end
425
426	ldr r1, [r7, #0x20c]
427	and r0, r8, #0xff @ assuming alignment
428	add r0, r7, r0, lsl #1
429	mov r2, r1, lsr #16
430	mov r1, r1, lsl #16 @ 106h << 16
431	mov r2, r2, lsl #16 @ 107h << 16
432
433	ssp_hle_07_6d6_loop:
434	ldr r5, [r0], #4
435	tst r5, r5
436	bmi ssp_hle_07_6d6_end
437	mov r5, r5, lsl #16
438	cmp r5, r1
439	movmi r1, r5
440	cmp r5, r2
441	sub r11,r11,#16
442	bmi ssp_hle_07_6d6_loop
443	mov r2, r5
444	b ssp_hle_07_6d6_loop
445
446	ssp_hle_07_6d6_end:
447	sub r0, r0, r7
448	mov r0, r0, lsr #1
449	bic r8, r8, #0xff
450	orr r8, r8, r0
451	orr r1, r2, r1, lsr #16
452	str r1, [r7, #0x20c]
453	hle_popstack
454	sub r11,r11,#6
455	b ssp_drc_next
456
457
458	ssp_hle_07_030:
459	ldrh r0, [r7]
460	mov r0, r0, lsl #4
461	orr r0, r0, r0, lsr #16
462	strh r0, [r7]
463	sub r11,r11,#3
464
465	ssp_hle_07_036:
34e243f1	466	ldr r1, [r7, #0x1e0] @ F1h F0h
ee9ee9fd	467	rsb r5, r1, r1, lsr #16
34e243f1	468	mov r5, r5, lsl #16 @ AL not needed
ee9ee9fd	469	cmp r5, #(4<<16)
	470	sub r11,r11,#5
	471	bmi hle_07_036_ending2
34e243f1	472	ldr r1, [r7, #0x1dc] @ EEh
ee9ee9fd	473	cmp r5, r1, lsl #16
34e243f1	474	sub r11,r11,#5
ee9ee9fd	475	bpl hle_07_036_ret
34e243f1	476
34e243f1	477	mov r0, r5, lsr #16
ee9ee9fd	478	add r1, r7, #0x100
34e243f1	479	strh r0, [r1, #0xea] @ F5h
34e243f1	480	ldr r0, [r7, #0x1e0] @ F0h
ee9ee9fd	481	and r0, r0, #3
34e243f1	482	strh r0, [r1, #0xf0] @ F8h
34e243f1	483	add r2, r0, #0xc0 @ r2
ee9ee9fd	484	add r2, r7, r2, lsl #1
	485	ldrh r2, [r2]
	486	ldr r0, [r7]
	487	mov r1, #4
	488	and r0, r0, r2
	489	bl ssp_pm_write
	490	@ will handle PMC later
34e243f1	491	ldr r0, [r7, #0x1e8] @ F5h << 16
	492	ldr r1, [r7, #0x1f0] @ F8h
	493	ldr r2, [r7, #0x1d4] @ EAh
ee9ee9fd	494	sub r0, r0, #(3<<16)
ee9ee9fd	495	add r0, r0, r1, lsl #16
34e243f1	496	sub r0, r2, r0, asr #18
ee9ee9fd	497	and r0, r0, #0x7f
	498	rsbs r0, r0, #0x78 @ length
	499	ble hle_07_036_ending1
	500
34e243f1	501	sub r11,r11,r0
	502
	503	@ copy part
ee9ee9fd	504	ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
	505	ldr r2, [r7, #SSP_OFFS_DRAM]
	506	mov r1, r1, lsl #16
	507	add r1, r2, r1, lsr #15 @ addr (based)
	508	ldrh r2, [r7, #0] @ pattern
	509	ldrh r3, [r7, #6] @ mode
	510
	511	mov r12, #0x4000
	512	orr r12,r12,#0x0018
34e243f1	513	subs r12,r3, r12
	514	subnes r12,r12,#0x0400
	515	blne tr_unhandled
ee9ee9fd	516
	517	orr r2, r2, r2, lsl #16
	518	tst r3, #0x400
	519	bne hle_07_036_ovrwr
	520
34e243f1	521	hle_07_036_no_ovrwr:
ee9ee9fd	522	tst r1, #2
34e243f1	523	strneh r2, [r1], #0x3e @ align
ee9ee9fd	524	subne r0, r0, #1
34e243f1	525	subs r0, r0, #4
ee9ee9fd	526	blt hle_07_036_l2
	527
	528	hle_07_036_l1:
	529	subs r0, r0, #4
34e243f1	530	str r2, [r1], #0x40
	531	str r2, [r1], #0x40
	532	bge hle_07_036_l1
ee9ee9fd	533
	534	hle_07_036_l2:
	535	tst r0, #2
34e243f1	536	strne r2, [r1], #0x40
ee9ee9fd	537	tst r0, #1
ee9ee9fd	538	strneh r2, [r1], #2
34e243f1	539	b hle_07_036_end_copy
ee9ee9fd	540
ee9ee9fd	541	hle_07_036_ovrwr:
34e243f1	542	tst r2, #0x000f
	543	orreq r12,r12,#0x000f
	544	tst r2, #0x00f0
	545	orreq r12,r12,#0x00f0
	546	tst r2, #0x0f00
	547	orreq r12,r12,#0x0f00
	548	tst r2, #0xf000
	549	orreq r12,r12,#0xf000
	550	orrs r12,r12,r12,lsl #16
	551	beq hle_07_036_no_ovrwr
	552
	553	tst r1, #2
	554	beq hle_07_036_ol0
	555	ldrh r3, [r1]
	556	and r3, r3, r12
	557	orr r3, r3, r2
	558	strh r3, [r1], #0x3e @ align
	559	sub r0, r0, #1
	560
	561	hle_07_036_ol0:
	562	subs r0, r0, #2
	563	blt hle_07_036_ol2
	564
	565	hle_07_036_ol1:
	566	subs r0, r0, #2
	567	ldr r3, [r1]
	568	and r3, r3, r12
	569	orr r3, r3, r2
	570	str r3, [r1], #0x40
	571	bge hle_07_036_ol1
	572
	573	hle_07_036_ol2:
	574	tst r0, #1
	575	ldrneh r3, [r1]
	576	andne r3, r3, r12
	577	orrne r3, r3, r2
	578	strneh r3, [r1], #2
	579
	580	hle_07_036_end_copy:
	581	ldr r2, [r7, #SSP_OFFS_DRAM]
	582	add r3, r7, #0x400
	583	sub r0, r1, r2 @ new addr
	584	mov r0, r0, lsr #1
	585	strh r0, [r3, #(0x6c+44)] @ SSP_OFFS_PM_WRITE+44 (low)
ee9ee9fd	586
ee9ee9fd	587	hle_07_036_ending1:
34e243f1	588	ldr r0, [r7, #0x1e0] @ F1h << 16
ee9ee9fd	589	add r0, r0, #(1<<16)
	590	and r0, r0, #(3<<16)
	591	add r0, r0, #(0xc4<<16)
	592	bic r8, r8, #0xff0000
34e243f1	593	orr r8, r8, r0 @ r2
34e243f1	594	add r0, r7, r0, lsr #15
ee9ee9fd	595	ldrh r0, [r0]
ee9ee9fd	596	ldr r2, [r7]
34e243f1	597	and r0, r0, r2
34e243f1	598	movs r5, r0, lsl #16
ee9ee9fd	599
34e243f1	600	ldr r1, [r7, #4] @ new mode
	601	add r2, r7, #0x400
	602	strh r1, [r2, #(0x6c+44+2)] @ SSP_OFFS_PM_WRITE+44 (high)
ee9ee9fd	603	mov r1, #4
ee9ee9fd	604	bl ssp_pm_write
34e243f1	605	sub r11,r11,#35
ee9ee9fd	606
	607	hle_07_036_ret:
	608	hle_popstack
	609	b ssp_drc_next
	610
	611	hle_07_036_ending2:
	612	sub r11,r11,#3
	613	movs r5, r5, lsl #1
	614	bmi hle_07_036_ret
34e243f1	615	mov r0, #0x87
ee9ee9fd	616	b ssp_drc_next @ let the dispatcher finish this
ee9ee9fd	617