[picodrive.git] / pico / carthw / svp / stub_arm.S

@*
@* Compiler helper functions and some SVP HLE code
@* (C) notaz, 2008,2009
@*
@* This work is licensed under the terms of MAME license.
@* See COPYING file in the top-level directory.
@*

#include "../../arm_features.h"

.syntax unified
.text
.align 2

@ externals
#define cache_flush_d_inval_i ESYM(cache_flush_d_inval_i)
#define ssp_get_iram_context  ESYM(ssp_get_iram_context)
#define ssp_pm_read           ESYM(ssp_pm_read)
#define ssp_pm_write          ESYM(ssp_pm_write)
#define ssp_translate_block   ESYM(ssp_translate_block)
#define tr_unhandled          ESYM(tr_unhandled)

@       SSP_GR0, SSP_X,     SSP_Y,   SSP_A,
@       SSP_ST,  SSP_STACK, SSP_PC,  SSP_P,
@       SSP_PM0, SSP_PM1,   SSP_PM2, SSP_XST,
@       SSP_PM4, SSP_gr13,  SSP_PMC, SSP_AL

@ register map:
@ r4:  XXYY
@ r5:  A
@ r6:  STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
@ r7:  SSP context
@ r8:  r0-r2 (.210)
@ r9:  r4-r6 (.654)
@ r10: P
@ r11: cycles
@ r12: tmp


#define SSP_OFFS_GR         0x400
#define SSP_PC                  6
#define SSP_P                   7
#define SSP_PM0                 8
#define SSP_PMC                14
#define SSP_OFFS_PM_WRITE   0x46c // pmac_write[]
#define SSP_OFFS_EMUSTAT    0x484 // emu_status
#define SSP_OFFS_IRAM_ROM   0x48c // ptr_iram_rom
#define SSP_OFFS_DRAM       0x490 // ptr_dram
#define SSP_OFFS_IRAM_DIRTY 0x494
#define SSP_OFFS_IRAM_CTX   0x498 // iram_context
#define SSP_OFFS_BLTAB      0x49c // block_table
#define SSP_OFFS_BLTAB_IRAM 0x4a0
#define SSP_OFFS_TMP0       0x4a4 // for entry PC
#define SSP_OFFS_TMP1       0x4a8
#define SSP_OFFS_TMP2       0x4ac
#define SSP_WAIT_PM0       0x2000


.macro ssp_drc_do_next patch_jump=0
.if \patch_jump
    str     lr, [r7, #SSP_OFFS_TMP2]		@ jump instr. (actually call) address + 4
.endif
    mov     r0, r0, lsl #16
    mov     r0, r0, lsr #16
    str     r0, [r7, #SSP_OFFS_TMP0]
    cmp     r0, #0x400
    blt     0f @ ssp_de_iram

    ldr     r2, [r7, #SSP_OFFS_BLTAB]
    ldr     r2, [r2, r0, lsl #2]
    tst     r2, r2
.if \patch_jump
    bne     ssp_drc_do_patch
.else
    bxne    r2
.endif
    bl      ssp_translate_block
    mov     r2, r0
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    ldr     r1, [r7, #SSP_OFFS_BLTAB]
    str     r2, [r1, r0, lsl #2]
.if \patch_jump
    b       ssp_drc_do_patch
.else
    bx      r2
.endif

0: @ ssp_de_iram:
    ldr     r1, [r7, #SSP_OFFS_IRAM_DIRTY]
    tst     r1, r1
    ldreq   r1, [r7, #SSP_OFFS_IRAM_CTX]
    beq     1f @ ssp_de_iram_ctx

    bl      ssp_get_iram_context
    mov     r1, #0
    str     r1, [r7, #SSP_OFFS_IRAM_DIRTY]
    mov     r1, r0
    str     r1, [r7, #SSP_OFFS_IRAM_CTX]
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    
1: @ ssp_de_iram_ctx:
    ldr     r2, [r7, #SSP_OFFS_BLTAB_IRAM]
    add     r2, r2, r1, lsl #12			@ block_tab_iram + iram_context * 0x800/2*4
    add     r1, r2, r0, lsl #2
    ldr     r2, [r1]
    tst     r2, r2
.if \patch_jump
    bne     ssp_drc_do_patch
.else
    bxne    r2
.endif
    str     r1, [r7, #SSP_OFFS_TMP1]
    bl      ssp_translate_block
    mov     r2, r0
    ldr     r0, [r7, #SSP_OFFS_TMP0]		@ entry PC
    ldr     r1, [r7, #SSP_OFFS_TMP1]		@ &block_table_iram[iram_context][rPC]
    str     r2, [r1]
.if \patch_jump
    b       ssp_drc_do_patch
.else
    bx      r2
.endif
.endm @ ssp_drc_do_next


FUNCTION(ssp_drc_entry):
    stmfd   sp!, {r4-r11, lr}
    mov     r7, r0                      @ ssp
    mov     r11, r1
ssp_regfile_load:
    add     r2, r7, #0x400
    add     r2, r2, #4
    ldmia   r2, {r3,r4,r5,r6,r8}
    mov     r3, r3, lsr #16
    mov     r3, r3, lsl #16
    orr     r4, r3, r4, lsr #16         @ XXYY

    and     r8, r8, #0x0f0000
    mov     r8, r8, lsl #13             @ sss0 *
    and     r9, r6, #0x670000
    tst     r6,     #0x80000000
    orrne   r8, r8, #0x8
    tst     r6,     #0x20000000
    orrne   r8, r8, #0x4                @ sss0 *           NZ..
    orr     r6, r8, r9, lsr #12         @ sss0 * .uu. .lll NZ..

    ldr     r8, [r7, #0x440]            @ r0-r2
    ldr     r9, [r7, #0x444]            @ r4-r6
    ldr     r10,[r7, #(0x400+SSP_P*4)]  @ P

    ldr     r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
    mov     r0, r0, lsr #16


FUNCTION(ssp_drc_next):
    ssp_drc_do_next 0


FUNCTION(ssp_drc_next_patch):
    ssp_drc_do_next 1

ssp_drc_do_patch:
    ldr     r1, [r7, #SSP_OFFS_TMP2]	@ jump instr. (actually call) address + 4
    subs    r12,r2, r1
    moveq   r3,     #0xe1000000
    orreq   r3, r3, #0x00a00000		@ nop
    streq   r3, [r1, #-4]
    beq     ssp_drc_dp_end

    cmp     r12,#4
    ldreq   r3, [r1]
    addeq   r3, r3, #1
    streq   r3, [r1, #-4]               @ move the other cond up
    moveq   r3,     #0xe1000000
    orreq   r3, r3, #0x00a00000
    streq   r3, [r1]                    @ fill it's place with nop
    beq     ssp_drc_dp_end

    ldr     r3, [r1, #-4]
    sub     r12,r12,#4
    mov     r3, r3, lsr #24
    bic     r3, r3, #1			@ L bit
    orr     r3, r3, r12,lsl #6
    mov     r3, r3, ror #8              @ patched branch instruction
    str     r3, [r1, #-4]               @ patch the bl/b to jump directly to another handler

ssp_drc_dp_end:
    str     r2, [r7, #SSP_OFFS_TMP1]
    sub     r0, r1, #4
    add     r1, r1, #4
    bl      cache_flush_d_inval_i
    ldr     r2, [r7, #SSP_OFFS_TMP1]
    ldr     r0, [r7, #SSP_OFFS_TMP0]
    bx      r2


FUNCTION(ssp_drc_end):
    mov     r0, r0, lsl #16
    str     r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]

ssp_regfile_store:
    str     r10,[r7, #(0x400+SSP_P*4)]  @ P
    str     r8, [r7, #0x440]            @ r0-r2
    str     r9, [r7, #0x444]            @ r4-r6

    mov     r9, r6, lsr #13
    and     r9, r9, #(7<<16)            @ STACK
    mov     r3, r6, lsl #28
    msr     cpsr_f, r3                  @ to to ARM PSR
    and     r6, r6, #0x670
    mov     r6, r6, lsl #12
    orrmi   r6, r6, #0x80000000         @ N
    orreq   r6, r6, #0x20000000         @ Z

    mov     r3, r4, lsl #16             @ Y
    mov     r2, r4, lsr #16
    mov     r2, r2, lsl #16             @ X
    add     r8, r7, #0x400
    add     r8, r8, #4
    stmia   r8, {r2,r3,r5,r6,r9}

    mov     r0, r11
    ldmfd   sp!, {r4-r11, lr}
    bx      lr


@ ld      A, PM0
@ andi    2
@ bra     z=1, gloc_0800
FUNCTION(ssp_hle_800):
    ldr     r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
    ldr     r1, [r7, #SSP_OFFS_EMUSTAT]
    tst     r0, #0x20000
    orreq   r1, r1,  #SSP_WAIT_PM0
    subeq   r11,r11, #1024
    streq   r1, [r7, #SSP_OFFS_EMUSTAT]
    mov     r0,     #0x400
    beq     ssp_drc_end
    orrne   r0, r0, #0x004
    b       ssp_drc_next


.macro hle_flushflags
    bic     r6, r6, #0xf
    mrs     r1, cpsr
    orr     r6, r6, r1, lsr #28 
.endm

.macro hle_popstack
    sub     r6, r6, #0x20000000
    add     r1, r7, #0x400
    add     r1, r1, #0x048			@ stack
    add     r1, r1, r6, lsr #28
    ldrh    r0, [r1]
.endm

FUNCTION(ssp_hle_902):
    cmp     r11, #0
    ble     ssp_drc_end

    add     r1, r7, #0x200
    ldrh    r0, [r1]
    ldr     r3, [r7, #SSP_OFFS_IRAM_ROM]
    add     r2, r3, r0, lsl #1			@ (r7|00)
    ldrh    r0, [r2], #2
    mov     r5, r5, lsl #16
    mov     r5, r5, lsr #16
    bic     r0, r0, #0xfc00
    add     r3, r3, r0, lsl #1 			@ IRAM dest
    ldrh    r12,[r2], #2			@ length
    bic     r3, r3, #3				@ always seen aligned
@    orr     r5, r5, #0x08000000
@    orr     r5, r5, #0x00880000
@    sub     r5, r5, r12, lsl #16
    bic     r6, r6, #0xf
    add     r12,r12,#1
    mov     r0, #1
    str     r0, [r7, #SSP_OFFS_IRAM_DIRTY]
    sub     r11,r11,r12,lsl #1
    sub     r11,r11,r12				@ -= length*3

ssp_hle_902_loop:
    ldrh    r0, [r2], #2
    ldrh    r1, [r2], #2
    subs    r12,r12,#2
    orr     r0, r0, r1, lsl #16
    str     r0, [r3], #4
    bgt     ssp_hle_902_loop

    tst     r12, #1
    ldrhne  r0, [r2], #2
    strhne  r0, [r3], #2

    ldr     r0, [r7, #SSP_OFFS_IRAM_ROM]
    add     r1, r7, #0x200
    sub     r2, r2, r0
    mov     r2, r2, lsr #1
    strh    r2, [r1]				@ (r7|00)

    sub     r0, r3, r0
    mov     r0, r0, lsr #1
    orr     r0, r0, #0x08000000
    orr     r0, r0, #0x001c8000
    str     r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
    str     r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]

    hle_popstack
    subs    r11,r11,#16				@ timeslice is likely to end
    ble     ssp_drc_end
    b       ssp_drc_next


@ this one is car rendering related
.macro hle_11_12c_mla offs_in
    ldrsh   r5, [r7, #(\offs_in+0)]
    ldrsh   r0, [r7, #(\offs_in+2)]
    ldrsh   r1, [r7, #(\offs_in+4)]
    mul     r5, r2, r5
    ldrsh   r12,[r7, #(\offs_in+6)]
    mla     r5, r3, r0, r5
    mla     r5, r4, r1, r5
    add     r5, r5, r12,lsl #11

    movs    r5, r5, lsr #13
    add     r1, r7, r8, lsr #23
    strh    r5, [r1]
    add     r8, r8, #(1<<24)
.endm

FUNCTION(ssp_hle_11_12c):
    cmp     r11, #0
    ble     ssp_drc_end

    mov     r0, #0
    bl      ssp_pm_read
    mov     r4, r0

    mov     r0, #0
    bl      ssp_pm_read
    mov     r5, r0

    mov     r0, #0
    bl      ssp_pm_read

    mov     r2, r4, lsl #16
    mov     r2, r2, asr #15			@ (r7|00) << 1
    mov     r3, r5, lsl #16
    mov     r3, r3, asr #15			@ (r7|01) << 1
    mov     r4, r0, lsl #16
    mov     r4, r4, asr #15			@ (r7|10) << 1

    bic     r8, r8, #0xff
    mov     r8, r8, ror #16

    hle_11_12c_mla 0x20
    hle_11_12c_mla 0x28
    hle_11_12c_mla 0x30

    mov     r8, r8, ror #16
    orr     r8, r8, #0x1c
@    hle_flushflags
    hle_popstack
    sub     r11,r11,#33
    b       ssp_drc_next


FUNCTION(ssp_hle_11_384):
    mov     r3, #2
    b       ssp_hle_11_38x

FUNCTION(ssp_hle_11_38a):
    mov     r3, #3		@ r5

ssp_hle_11_38x:
    cmp     r11, #0
    ble     ssp_drc_end

    mov     r2, #0		@ EFh, EEh
    mov     r1, #1		@ r4
    add     r0, r7, #0x1c0	@ r0 (based)

ssp_hle_11_38x_loop:
    ldrh    r5, [r0], #2
    ldr     r12,[r7, #0x224]
    mov     r5, r5, lsl #16
    eor     r5, r5, r5, asr #31
    add     r5, r5, r5, lsr #31	@ abs(r5)
    cmp     r5, r12,lsl #16
    orrpl   r2, r2, r1,lsl #16	@ EFh |= r4

    ldrh    r5, [r0, #2]!
    ldr     r12,[r7, #0x220]
    cmp     r5, r12,lsr #16
    orrpl   r2, r2, r1,lsl #16	@ EFh |= r4

    ldr     r12,[r7, #0x1e8]
    add     r0, r0, #2
    mov     r12,r12,lsl #16
    cmp     r5, r12,lsr #16
    orrmi   r2, r2, r1

    mov     r1, r1, lsl #1
    subs    r3, r3, #1
    bpl     ssp_hle_11_38x_loop

    str     r2, [r7, #0x1dc]
    sub     r0, r0, r7
    bic     r8, r8, #0xff
    orr     r8, r8, r0, lsr #1
    bic     r9, r9, #0xff
    orr     r9, r9, r1

@    hle_flushflags
    hle_popstack
    sub     r11,r11,#(9+30*4)
    b       ssp_drc_next


FUNCTION(ssp_hle_07_6d6):
    cmp     r11, #0
    ble     ssp_drc_end

    ldr     r1, [r7, #0x20c]
    and     r0, r8, #0xff	@ assuming alignment
    add     r0, r7, r0, lsl #1
    mov     r2, r1, lsr #16
    mov     r1, r1, lsl #16	@ 106h << 16
    mov     r2, r2, lsl #16	@ 107h << 16

ssp_hle_07_6d6_loop:
    ldr     r5, [r0], #4
    tst     r5, r5
    bmi     ssp_hle_07_6d6_end
    mov     r5, r5, lsl #16
    cmp     r5, r1
    movmi   r1, r5
    cmp     r5, r2
    sub     r11,r11,#16
    bmi     ssp_hle_07_6d6_loop
    mov     r2, r5
    b       ssp_hle_07_6d6_loop

ssp_hle_07_6d6_end:
    sub     r0, r0, r7
    mov     r0, r0, lsr #1
    bic     r8, r8, #0xff
    orr     r8, r8, r0
    orr     r1, r2, r1, lsr #16
    str     r1, [r7, #0x20c]
    hle_popstack
    sub     r11,r11,#6
    b       ssp_drc_next


FUNCTION(ssp_hle_07_030):
    ldrh    r0, [r7]
    mov     r0, r0, lsl #4
    orr     r0, r0, r0, lsr #16
    strh    r0, [r7]
    sub     r11,r11,#3

FUNCTION(ssp_hle_07_036):
    ldr     r1, [r7, #0x1e0]	@ F1h F0h
    rsb     r5, r1, r1, lsr #16
    mov     r5, r5, lsl #16	@ AL not needed
    cmp     r5, #(4<<16)
    sub     r11,r11,#5
    bmi     hle_07_036_ending2
    ldr     r1, [r7, #0x1dc]	@ EEh
    cmp     r5, r1, lsl #16
    sub     r11,r11,#5
    bpl     hle_07_036_ret

    mov     r0, r5, lsr #16
    add     r1, r7, #0x100
    strh    r0, [r1, #0xea]	@ F5h
    ldr     r0, [r7, #0x1e0]	@ F0h
    and     r0, r0, #3
    strh    r0, [r1, #0xf0]	@ F8h
    add     r2, r0, #0xc0	@ r2
    add     r2, r7, r2, lsl #1
    ldrh    r2, [r2]
    ldr     r0, [r7]
    mov     r1, #4
    and     r0, r0, r2
    bl      ssp_pm_write
    @ will handle PMC later
    ldr     r0, [r7, #0x1e8]	@ F5h << 16
    ldr     r1, [r7, #0x1f0]	@ F8h
    ldr     r2, [r7, #0x1d4]	@ EAh
    sub     r0, r0, #(3<<16)
    add     r0, r0, r1, lsl #16
    sub     r0, r2, r0, asr #18
    and     r0, r0, #0x7f
    rsbs    r0, r0, #0x78	@ length
    ble     hle_07_036_ending1

    sub     r11,r11,r0

    @ copy part
    ldr     r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
    ldr     r2, [r7, #SSP_OFFS_DRAM]
    mov     r1, r1, lsl #16
    add     r1, r2, r1, lsr #15	@ addr (based)
    ldrh    r2, [r7, #0]	@ pattern
    ldrh    r3, [r7, #6]	@ mode

    mov     r12,    #0x4000
    orr     r12,r12,#0x0018
    subs    r12,r3, r12
    subsne  r12,r12,#0x0400
    blne    tr_unhandled

    orr     r2, r2, r2, lsl #16
    tst     r3, #0x400
    bne     hle_07_036_ovrwr

hle_07_036_no_ovrwr:
    tst     r1, #2
    strhne  r2, [r1], #0x3e	@ align
    subne   r0, r0, #1
    subs    r0, r0, #4
    blt     hle_07_036_l2

hle_07_036_l1:
    subs    r0, r0, #4
    str     r2, [r1], #0x40
    str     r2, [r1], #0x40
    bge     hle_07_036_l1

hle_07_036_l2:
    tst     r0, #2
    strne   r2, [r1], #0x40
    tst     r0, #1
    strhne  r2, [r1], #2
    b       hle_07_036_end_copy

hle_07_036_ovrwr:
    tst     r2,     #0x000f
    orreq   r12,r12,#0x000f
    tst     r2,     #0x00f0
    orreq   r12,r12,#0x00f0
    tst     r2,     #0x0f00
    orreq   r12,r12,#0x0f00
    tst     r2,     #0xf000
    orreq   r12,r12,#0xf000
    orrs    r12,r12,r12,lsl #16
    beq     hle_07_036_no_ovrwr

    tst     r1, #2
    beq     hle_07_036_ol0
    ldrh    r3, [r1]
    and     r3, r3, r12
    orr     r3, r3, r2
    strh    r3, [r1], #0x3e	@ align
    sub     r0, r0, #1

hle_07_036_ol0:
    subs    r0, r0, #2
    blt     hle_07_036_ol2

hle_07_036_ol1:
    subs    r0, r0, #2
    ldr     r3, [r1]
    and     r3, r3, r12
    orr     r3, r3, r2
    str     r3, [r1], #0x40
    bge     hle_07_036_ol1

hle_07_036_ol2:
    tst     r0, #1
    ldrhne  r3, [r1]
    andne   r3, r3, r12
    orrne   r3, r3, r2
    strhne  r3, [r1], #2

hle_07_036_end_copy:
    ldr     r2, [r7, #SSP_OFFS_DRAM]
    add     r3, r7, #0x400
    sub     r0, r1, r2          @ new addr
    mov     r0, r0, lsr #1
    strh    r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)

hle_07_036_ending1:
    ldr     r0, [r7, #0x1e0]	@ F1h << 16
    add     r0, r0, #(1<<16)
    and     r0, r0, #(3<<16)
    add     r0, r0, #(0xc4<<16)
    bic     r8, r8, #0xff0000
    orr     r8, r8, r0		@ r2
    add     r0, r7, r0, lsr #15
    ldrh    r0, [r0]
    ldr     r2, [r7]
    and     r0, r0, r2
    movs    r5, r0, lsl #16

    ldr     r1, [r7, #4]	@ new mode
    add     r2, r7, #0x400
    strh    r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
    mov     r1, #4
    bl      ssp_pm_write
    sub     r11,r11,#35

hle_07_036_ret:
    hle_popstack
    b       ssp_drc_next

hle_07_036_ending2:
    sub     r11,r11,#3
    movs    r5, r5, lsl #1
    bmi     hle_07_036_ret
    mov     r0, #0x87
    b       ssp_drc_next	@ let the dispatcher finish this

@ vim:filetype=armasm
Commit	Line	Data
cff531af	1	@*
	2	@* Compiler helper functions and some SVP HLE code
	3	@* (C) notaz, 2008,2009
	4	@*
	5	@* This work is licensed under the terms of MAME license.
	6	@* See COPYING file in the top-level directory.
	7	@*
65ca3034	8
f3fe3e5b	9	#include "../../arm_features.h"
e807ac75	10
f3fe3e5b	11	.syntax unified
e807ac75	12	.text
	13	.align 2
	14
f3fe3e5b	15	@ externals
	16	#define cache_flush_d_inval_i ESYM(cache_flush_d_inval_i)
	17	#define ssp_get_iram_context ESYM(ssp_get_iram_context)
	18	#define ssp_pm_read ESYM(ssp_pm_read)
	19	#define ssp_pm_write ESYM(ssp_pm_write)
	20	#define ssp_translate_block ESYM(ssp_translate_block)
	21	#define tr_unhandled ESYM(tr_unhandled)
	22
e807ac75	23	@ SSP_GR0, SSP_X, SSP_Y, SSP_A,
	24	@ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
	25	@ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
	26	@ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
	27
	28	@ register map:
	29	@ r4: XXYY
	30	@ r5: A
b9c1d012	31	@ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
e807ac75	32	@ r7: SSP context
5d817c91	33	@ r8: r0-r2 (.210)
5d817c91	34	@ r9: r4-r6 (.654)
e807ac75	35	@ r10: P
e807ac75	36	@ r11: cycles
f8af9634	37	@ r12: tmp
e807ac75	38
e807ac75	39
45883918	40	#define SSP_OFFS_GR 0x400
	41	#define SSP_PC 6
	42	#define SSP_P 7
	43	#define SSP_PM0 8
f5d1115f	44	#define SSP_PMC 14
f5d1115f	45	#define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
45883918	46	#define SSP_OFFS_EMUSTAT 0x484 // emu_status
f5d1115f	47	#define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
ee9ee9fd	48	#define SSP_OFFS_DRAM 0x490 // ptr_dram
45883918	49	#define SSP_OFFS_IRAM_DIRTY 0x494
	50	#define SSP_OFFS_IRAM_CTX 0x498 // iram_context
	51	#define SSP_OFFS_BLTAB 0x49c // block_table
	52	#define SSP_OFFS_BLTAB_IRAM 0x4a0
	53	#define SSP_OFFS_TMP0 0x4a4 // for entry PC
	54	#define SSP_OFFS_TMP1 0x4a8
	55	#define SSP_OFFS_TMP2 0x4ac
	56	#define SSP_WAIT_PM0 0x2000
	57
	58
	59	.macro ssp_drc_do_next patch_jump=0
	60	.if \patch_jump
	61	str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
	62	.endif
	63	mov r0, r0, lsl #16
	64	mov r0, r0, lsr #16
	65	str r0, [r7, #SSP_OFFS_TMP0]
	66	cmp r0, #0x400
	67	blt 0f @ ssp_de_iram
	68
	69	ldr r2, [r7, #SSP_OFFS_BLTAB]
	70	ldr r2, [r2, r0, lsl #2]
	71	tst r2, r2
	72	.if \patch_jump
	73	bne ssp_drc_do_patch
	74	.else
	75	bxne r2
	76	.endif
	77	bl ssp_translate_block
	78	mov r2, r0
	79	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
	80	ldr r1, [r7, #SSP_OFFS_BLTAB]
	81	str r2, [r1, r0, lsl #2]
	82	.if \patch_jump
	83	b ssp_drc_do_patch
	84	.else
	85	bx r2
	86	.endif
	87
	88	0: @ ssp_de_iram:
	89	ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
	90	tst r1, r1
	91	ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
	92	beq 1f @ ssp_de_iram_ctx
	93
	94	bl ssp_get_iram_context
	95	mov r1, #0
	96	str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
	97	mov r1, r0
	98	str r1, [r7, #SSP_OFFS_IRAM_CTX]
	99	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
	100
	101	1: @ ssp_de_iram_ctx:
	102	ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
	103	add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
	104	add r1, r2, r0, lsl #2
	105	ldr r2, [r1]
	106	tst r2, r2
	107	.if \patch_jump
	108	bne ssp_drc_do_patch
	109	.else
	110	bxne r2
	111	.endif
	112	str r1, [r7, #SSP_OFFS_TMP1]
113	bl ssp_translate_block
114	mov r2, r0
115	ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
116	ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
117	str r2, [r1]
118	.if \patch_jump
119	b ssp_drc_do_patch
120	.else
121	bx r2
122	.endif
123	.endm @ ssp_drc_do_next
124
125
f3fe3e5b	126	FUNCTION(ssp_drc_entry):
45883918	127	stmfd sp!, {r4-r11, lr}
f3fe3e5b	128	mov r7, r0 @ ssp
f3fe3e5b	129	mov r11, r1
71bb1b7b	130	ssp_regfile_load:
e807ac75	131	add r2, r7, #0x400
	132	add r2, r2, #4
	133	ldmia r2, {r3,r4,r5,r6,r8}
	134	mov r3, r3, lsr #16
	135	mov r3, r3, lsl #16
	136	orr r4, r3, r4, lsr #16 @ XXYY
b9c1d012	137
	138	and r8, r8, #0x0f0000
	139	mov r8, r8, lsl #13 @ sss0 *
	140	and r9, r6, #0x670000
	141	tst r6, #0x80000000
	142	orrne r8, r8, #0x8
	143	tst r6, #0x20000000
	144	orrne r8, r8, #0x4 @ sss0 * NZ..
a6fb500b	145	orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
b9c1d012	146
e807ac75	147	ldr r8, [r7, #0x440] @ r0-r2
e807ac75	148	ldr r9, [r7, #0x444] @ r4-r6
45883918	149	ldr r10,[r7, #(0x400+SSP_P*4)] @ P
	150
	151	ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
	152	mov r0, r0, lsr #16
	153
	154
f3fe3e5b	155	FUNCTION(ssp_drc_next):
45883918	156	ssp_drc_do_next 0
	157
	158
f3fe3e5b	159	FUNCTION(ssp_drc_next_patch):
45883918	160	ssp_drc_do_next 1
	161
	162	ssp_drc_do_patch:
	163	ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
	164	subs r12,r2, r1
	165	moveq r3, #0xe1000000
	166	orreq r3, r3, #0x00a00000 @ nop
	167	streq r3, [r1, #-4]
	168	beq ssp_drc_dp_end
	169
	170	cmp r12,#4
	171	ldreq r3, [r1]
	172	addeq r3, r3, #1
	173	streq r3, [r1, #-4] @ move the other cond up
	174	moveq r3, #0xe1000000
	175	orreq r3, r3, #0x00a00000
	176	streq r3, [r1] @ fill it's place with nop
	177	beq ssp_drc_dp_end
	178
	179	ldr r3, [r1, #-4]
	180	sub r12,r12,#4
	181	mov r3, r3, lsr #24
	182	bic r3, r3, #1 @ L bit
	183	orr r3, r3, r12,lsl #6
	184	mov r3, r3, ror #8 @ patched branch instruction
f8af9634	185	str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
45883918	186
	187	ssp_drc_dp_end:
	188	str r2, [r7, #SSP_OFFS_TMP1]
	189	sub r0, r1, #4
	190	add r1, r1, #4
84100c0f	191	bl cache_flush_d_inval_i
45883918	192	ldr r2, [r7, #SSP_OFFS_TMP1]
	193	ldr r0, [r7, #SSP_OFFS_TMP0]
	194	bx r2
e807ac75	195
e807ac75	196
f3fe3e5b	197	FUNCTION(ssp_drc_end):
45883918	198	mov r0, r0, lsl #16
	199	str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
	200
71bb1b7b	201	ssp_regfile_store:
45883918	202	str r10,[r7, #(0x400+SSP_P*4)] @ P
e807ac75	203	str r8, [r7, #0x440] @ r0-r2
e807ac75	204	str r9, [r7, #0x444] @ r4-r6
b9c1d012	205
b9c1d012	206	mov r9, r6, lsr #13
e807ac75	207	and r9, r9, #(7<<16) @ STACK
b9c1d012	208	mov r3, r6, lsl #28
f3fe3e5b	209	msr cpsr_f, r3 @ to to ARM PSR
b9c1d012	210	and r6, r6, #0x670
	211	mov r6, r6, lsl #12
	212	orrmi r6, r6, #0x80000000 @ N
	213	orreq r6, r6, #0x20000000 @ Z
	214
e807ac75	215	mov r3, r4, lsl #16 @ Y
	216	mov r2, r4, lsr #16
	217	mov r2, r2, lsl #16 @ X
	218	add r8, r7, #0x400
	219	add r8, r8, #4
	220	stmia r8, {r2,r3,r5,r6,r9}
71bb1b7b	221
71bb1b7b	222	mov r0, r11
	223	ldmfd sp!, {r4-r11, lr}
	224	bx lr
	225
	226
d5276282	227
	228	@ ld A, PM0
	229	@ andi 2
	230	@ bra z=1, gloc_0800
f3fe3e5b	231	FUNCTION(ssp_hle_800):
d5276282	232	ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
71bb1b7b	233	ldr r1, [r7, #SSP_OFFS_EMUSTAT]
d5276282	234	tst r0, #0x20000
f5d1115f	235	orreq r1, r1, #SSP_WAIT_PM0
45883918	236	subeq r11,r11, #1024
71bb1b7b	237	streq r1, [r7, #SSP_OFFS_EMUSTAT]
45883918	238	mov r0, #0x400
	239	beq ssp_drc_end
	240	orrne r0, r0, #0x004
45883918	241	b ssp_drc_next
d5276282	242
e807ac75	243
ee9ee9fd	244	.macro hle_flushflags
	245	bic r6, r6, #0xf
	246	mrs r1, cpsr
	247	orr r6, r6, r1, lsr #28
	248	.endm
	249
	250	.macro hle_popstack
	251	sub r6, r6, #0x20000000
	252	add r1, r7, #0x400
	253	add r1, r1, #0x048 @ stack
	254	add r1, r1, r6, lsr #28
	255	ldrh r0, [r1]
	256	.endm
	257
f3fe3e5b	258	FUNCTION(ssp_hle_902):
f5d1115f	259	cmp r11, #0
	260	ble ssp_drc_end
	261
	262	add r1, r7, #0x200
	263	ldrh r0, [r1]
	264	ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
	265	add r2, r3, r0, lsl #1 @ (r7\|00)
	266	ldrh r0, [r2], #2
	267	mov r5, r5, lsl #16
	268	mov r5, r5, lsr #16
	269	bic r0, r0, #0xfc00
	270	add r3, r3, r0, lsl #1 @ IRAM dest
	271	ldrh r12,[r2], #2 @ length
	272	bic r3, r3, #3 @ always seen aligned
	273	@ orr r5, r5, #0x08000000
	274	@ orr r5, r5, #0x00880000
	275	@ sub r5, r5, r12, lsl #16
	276	bic r6, r6, #0xf
	277	add r12,r12,#1
	278	mov r0, #1
	279	str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
	280	sub r11,r11,r12,lsl #1
	281	sub r11,r11,r12 @ -= length*3
	282
	283	ssp_hle_902_loop:
	284	ldrh r0, [r2], #2
	285	ldrh r1, [r2], #2
	286	subs r12,r12,#2
	287	orr r0, r0, r1, lsl #16
	288	str r0, [r3], #4
	289	bgt ssp_hle_902_loop
	290
	291	tst r12, #1
f3fe3e5b	292	ldrhne r0, [r2], #2
f3fe3e5b	293	strhne r0, [r3], #2
f5d1115f	294
	295	ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
	296	add r1, r7, #0x200
	297	sub r2, r2, r0
	298	mov r2, r2, lsr #1
	299	strh r2, [r1] @ (r7\|00)
	300
	301	sub r0, r3, r0
	302	mov r0, r0, lsr #1
	303	orr r0, r0, #0x08000000
	304	orr r0, r0, #0x001c8000
	305	str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
	306	str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
	307
ee9ee9fd	308	hle_popstack
f5d1115f	309	subs r11,r11,#16 @ timeslice is likely to end
	310	ble ssp_drc_end
	311	b ssp_drc_next
	312
ee9ee9fd	313
	314	@ this one is car rendering related
	315	.macro hle_11_12c_mla offs_in
	316	ldrsh r5, [r7, #(\offs_in+0)]
	317	ldrsh r0, [r7, #(\offs_in+2)]
	318	ldrsh r1, [r7, #(\offs_in+4)]
	319	mul r5, r2, r5
	320	ldrsh r12,[r7, #(\offs_in+6)]
	321	mla r5, r3, r0, r5
	322	mla r5, r4, r1, r5
	323	add r5, r5, r12,lsl #11
	324
	325	movs r5, r5, lsr #13
	326	add r1, r7, r8, lsr #23
	327	strh r5, [r1]
	328	add r8, r8, #(1<<24)
	329	.endm
	330
f3fe3e5b	331	FUNCTION(ssp_hle_11_12c):
ee9ee9fd	332	cmp r11, #0
	333	ble ssp_drc_end
	334
	335	mov r0, #0
	336	bl ssp_pm_read
	337	mov r4, r0
	338
	339	mov r0, #0
	340	bl ssp_pm_read
	341	mov r5, r0
	342
	343	mov r0, #0
	344	bl ssp_pm_read
	345
	346	mov r2, r4, lsl #16
	347	mov r2, r2, asr #15 @ (r7\|00) << 1
	348	mov r3, r5, lsl #16
	349	mov r3, r3, asr #15 @ (r7\|01) << 1
	350	mov r4, r0, lsl #16
	351	mov r4, r4, asr #15 @ (r7\|10) << 1
	352
	353	bic r8, r8, #0xff
	354	mov r8, r8, ror #16
	355
	356	hle_11_12c_mla 0x20
	357	hle_11_12c_mla 0x28
	358	hle_11_12c_mla 0x30
	359
	360	mov r8, r8, ror #16
	361	orr r8, r8, #0x1c
	362	@ hle_flushflags
	363	hle_popstack
	364	sub r11,r11,#33
	365	b ssp_drc_next
	366
	367
f3fe3e5b	368	FUNCTION(ssp_hle_11_384):
ee9ee9fd	369	mov r3, #2
	370	b ssp_hle_11_38x
	371
f3fe3e5b	372	FUNCTION(ssp_hle_11_38a):
ee9ee9fd	373	mov r3, #3 @ r5
	374
	375	ssp_hle_11_38x:
	376	cmp r11, #0
	377	ble ssp_drc_end
	378
	379	mov r2, #0 @ EFh, EEh
	380	mov r1, #1 @ r4
	381	add r0, r7, #0x1c0 @ r0 (based)
	382
	383	ssp_hle_11_38x_loop:
	384	ldrh r5, [r0], #2
	385	ldr r12,[r7, #0x224]
	386	mov r5, r5, lsl #16
	387	eor r5, r5, r5, asr #31
	388	add r5, r5, r5, lsr #31 @ abs(r5)
	389	cmp r5, r12,lsl #16
	390	orrpl r2, r2, r1,lsl #16 @ EFh \|= r4
	391
	392	ldrh r5, [r0, #2]!
	393	ldr r12,[r7, #0x220]
	394	cmp r5, r12,lsr #16
	395	orrpl r2, r2, r1,lsl #16 @ EFh \|= r4
	396
	397	ldr r12,[r7, #0x1e8]
	398	add r0, r0, #2
	399	mov r12,r12,lsl #16
	400	cmp r5, r12,lsr #16
	401	orrmi r2, r2, r1
	402
	403	mov r1, r1, lsl #1
	404	subs r3, r3, #1
	405	bpl ssp_hle_11_38x_loop
	406
	407	str r2, [r7, #0x1dc]
	408	sub r0, r0, r7
	409	bic r8, r8, #0xff
	410	orr r8, r8, r0, lsr #1
	411	bic r9, r9, #0xff
	412	orr r9, r9, r1
	413
	414	@ hle_flushflags
	415	hle_popstack
	416	sub r11,r11,#(9+30*4)
	417	b ssp_drc_next
	418
	419
f3fe3e5b	420	FUNCTION(ssp_hle_07_6d6):
ee9ee9fd	421	cmp r11, #0
	422	ble ssp_drc_end
	423
	424	ldr r1, [r7, #0x20c]
	425	and r0, r8, #0xff @ assuming alignment
	426	add r0, r7, r0, lsl #1
	427	mov r2, r1, lsr #16
	428	mov r1, r1, lsl #16 @ 106h << 16
	429	mov r2, r2, lsl #16 @ 107h << 16
	430
	431	ssp_hle_07_6d6_loop:
	432	ldr r5, [r0], #4
	433	tst r5, r5
	434	bmi ssp_hle_07_6d6_end
	435	mov r5, r5, lsl #16
	436	cmp r5, r1
	437	movmi r1, r5
	438	cmp r5, r2
	439	sub r11,r11,#16
	440	bmi ssp_hle_07_6d6_loop
	441	mov r2, r5
	442	b ssp_hle_07_6d6_loop
	443
	444	ssp_hle_07_6d6_end:
	445	sub r0, r0, r7
	446	mov r0, r0, lsr #1
	447	bic r8, r8, #0xff
	448	orr r8, r8, r0
	449	orr r1, r2, r1, lsr #16
	450	str r1, [r7, #0x20c]
	451	hle_popstack
	452	sub r11,r11,#6
	453	b ssp_drc_next
	454
	455
f3fe3e5b	456	FUNCTION(ssp_hle_07_030):
ee9ee9fd	457	ldrh r0, [r7]
	458	mov r0, r0, lsl #4
	459	orr r0, r0, r0, lsr #16
	460	strh r0, [r7]
	461	sub r11,r11,#3
	462
f3fe3e5b	463	FUNCTION(ssp_hle_07_036):
34e243f1	464	ldr r1, [r7, #0x1e0] @ F1h F0h
ee9ee9fd	465	rsb r5, r1, r1, lsr #16
34e243f1	466	mov r5, r5, lsl #16 @ AL not needed
ee9ee9fd	467	cmp r5, #(4<<16)
	468	sub r11,r11,#5
	469	bmi hle_07_036_ending2
34e243f1	470	ldr r1, [r7, #0x1dc] @ EEh
ee9ee9fd	471	cmp r5, r1, lsl #16
34e243f1	472	sub r11,r11,#5
ee9ee9fd	473	bpl hle_07_036_ret
34e243f1	474
34e243f1	475	mov r0, r5, lsr #16
ee9ee9fd	476	add r1, r7, #0x100
34e243f1	477	strh r0, [r1, #0xea] @ F5h
34e243f1	478	ldr r0, [r7, #0x1e0] @ F0h
ee9ee9fd	479	and r0, r0, #3
34e243f1	480	strh r0, [r1, #0xf0] @ F8h
34e243f1	481	add r2, r0, #0xc0 @ r2
ee9ee9fd	482	add r2, r7, r2, lsl #1
	483	ldrh r2, [r2]
	484	ldr r0, [r7]
	485	mov r1, #4
	486	and r0, r0, r2
	487	bl ssp_pm_write
	488	@ will handle PMC later
34e243f1	489	ldr r0, [r7, #0x1e8] @ F5h << 16
	490	ldr r1, [r7, #0x1f0] @ F8h
	491	ldr r2, [r7, #0x1d4] @ EAh
ee9ee9fd	492	sub r0, r0, #(3<<16)
ee9ee9fd	493	add r0, r0, r1, lsl #16
34e243f1	494	sub r0, r2, r0, asr #18
ee9ee9fd	495	and r0, r0, #0x7f
	496	rsbs r0, r0, #0x78 @ length
	497	ble hle_07_036_ending1
	498
34e243f1	499	sub r11,r11,r0
	500
	501	@ copy part
ee9ee9fd	502	ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
	503	ldr r2, [r7, #SSP_OFFS_DRAM]
	504	mov r1, r1, lsl #16
	505	add r1, r2, r1, lsr #15 @ addr (based)
	506	ldrh r2, [r7, #0] @ pattern
	507	ldrh r3, [r7, #6] @ mode
	508
	509	mov r12, #0x4000
	510	orr r12,r12,#0x0018
34e243f1	511	subs r12,r3, r12
f3fe3e5b	512	subsne r12,r12,#0x0400
34e243f1	513	blne tr_unhandled
ee9ee9fd	514
	515	orr r2, r2, r2, lsl #16
	516	tst r3, #0x400
	517	bne hle_07_036_ovrwr
	518
34e243f1	519	hle_07_036_no_ovrwr:
ee9ee9fd	520	tst r1, #2
f3fe3e5b	521	strhne r2, [r1], #0x3e @ align
ee9ee9fd	522	subne r0, r0, #1
34e243f1	523	subs r0, r0, #4
ee9ee9fd	524	blt hle_07_036_l2
	525
	526	hle_07_036_l1:
	527	subs r0, r0, #4
34e243f1	528	str r2, [r1], #0x40
	529	str r2, [r1], #0x40
	530	bge hle_07_036_l1
ee9ee9fd	531
	532	hle_07_036_l2:
	533	tst r0, #2
34e243f1	534	strne r2, [r1], #0x40
ee9ee9fd	535	tst r0, #1
f3fe3e5b	536	strhne r2, [r1], #2
34e243f1	537	b hle_07_036_end_copy
ee9ee9fd	538
ee9ee9fd	539	hle_07_036_ovrwr:
34e243f1	540	tst r2, #0x000f
	541	orreq r12,r12,#0x000f
	542	tst r2, #0x00f0
	543	orreq r12,r12,#0x00f0
	544	tst r2, #0x0f00
	545	orreq r12,r12,#0x0f00
	546	tst r2, #0xf000
	547	orreq r12,r12,#0xf000
	548	orrs r12,r12,r12,lsl #16
	549	beq hle_07_036_no_ovrwr
	550
	551	tst r1, #2
	552	beq hle_07_036_ol0
	553	ldrh r3, [r1]
	554	and r3, r3, r12
	555	orr r3, r3, r2
	556	strh r3, [r1], #0x3e @ align
	557	sub r0, r0, #1
	558
	559	hle_07_036_ol0:
	560	subs r0, r0, #2
	561	blt hle_07_036_ol2
	562
	563	hle_07_036_ol1:
	564	subs r0, r0, #2
	565	ldr r3, [r1]
	566	and r3, r3, r12
	567	orr r3, r3, r2
	568	str r3, [r1], #0x40
	569	bge hle_07_036_ol1
	570
	571	hle_07_036_ol2:
	572	tst r0, #1
f3fe3e5b	573	ldrhne r3, [r1]
34e243f1	574	andne r3, r3, r12
34e243f1	575	orrne r3, r3, r2
f3fe3e5b	576	strhne r3, [r1], #2
34e243f1	577
	578	hle_07_036_end_copy:
	579	ldr r2, [r7, #SSP_OFFS_DRAM]
	580	add r3, r7, #0x400
	581	sub r0, r1, r2 @ new addr
	582	mov r0, r0, lsr #1
	583	strh r0, [r3, #(0x6c+44)] @ SSP_OFFS_PM_WRITE+44 (low)
ee9ee9fd	584
ee9ee9fd	585	hle_07_036_ending1:
34e243f1	586	ldr r0, [r7, #0x1e0] @ F1h << 16
ee9ee9fd	587	add r0, r0, #(1<<16)
	588	and r0, r0, #(3<<16)
	589	add r0, r0, #(0xc4<<16)
	590	bic r8, r8, #0xff0000
34e243f1	591	orr r8, r8, r0 @ r2
34e243f1	592	add r0, r7, r0, lsr #15
ee9ee9fd	593	ldrh r0, [r0]
ee9ee9fd	594	ldr r2, [r7]
34e243f1	595	and r0, r0, r2
34e243f1	596	movs r5, r0, lsl #16
ee9ee9fd	597
34e243f1	598	ldr r1, [r7, #4] @ new mode
	599	add r2, r7, #0x400
	600	strh r1, [r2, #(0x6c+44+2)] @ SSP_OFFS_PM_WRITE+44 (high)
ee9ee9fd	601	mov r1, #4
ee9ee9fd	602	bl ssp_pm_write
34e243f1	603	sub r11,r11,#35
ee9ee9fd	604
	605	hle_07_036_ret:
	606	hle_popstack
	607	b ssp_drc_next
	608
	609	hle_07_036_ending2:
	610	sub r11,r11,#3
	611	movs r5, r5, lsl #1
	612	bmi hle_07_036_ret
34e243f1	613	mov r0, #0x87
ee9ee9fd	614	b ssp_drc_next @ let the dispatcher finish this
ee9ee9fd	615
cff531af	616	@ vim:filetype=armasm