3f23709e |
1 | /*************************************************************************************** |
2 | * Genesis Plus |
3 | * CD data controller (LC89510 compatible) |
4 | * |
5 | * Copyright (C) 2012 Eke-Eke (Genesis Plus GX) |
6 | * |
7 | * Redistribution and use of this code or any derivative works are permitted |
8 | * provided that the following conditions are met: |
9 | * |
10 | * - Redistributions may not be sold, nor may they be used in a commercial |
11 | * product or activity. |
12 | * |
13 | * - Redistributions that are modified from the original source must include the |
14 | * complete source code, including the source code for all components used by a |
15 | * binary built from the modified sources. However, as a special exception, the |
16 | * source code distributed need not include anything that is normally distributed |
17 | * (in either source or binary form) with the major components (compiler, kernel, |
18 | * and so on) of the operating system on which the executable runs, unless that |
19 | * component itself accompanies the executable. |
20 | * |
21 | * - Redistributions must reproduce the above copyright notice, this list of |
22 | * conditions and the following disclaimer in the documentation and/or other |
23 | * materials provided with the distribution. |
24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
28 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
29 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | * |
37 | ****************************************************************************************/ |
38 | |
39 | #include "../pico_int.h" |
40 | #include "genplus_macros.h" |
41 | |
42 | /* IFSTAT register bitmasks */ |
43 | #define BIT_DTEI 0x40 |
44 | #define BIT_DECI 0x20 |
45 | #define BIT_DTBSY 0x08 |
46 | #define BIT_DTEN 0x02 |
47 | |
48 | /* IFCTRL register bitmasks */ |
49 | #define BIT_DTEIEN 0x40 |
50 | #define BIT_DECIEN 0x20 |
51 | #define BIT_DOUTEN 0x02 |
52 | |
53 | /* CTRL0 register bitmasks */ |
54 | #define BIT_DECEN 0x80 |
55 | #define BIT_E01RQ 0x20 |
56 | #define BIT_AUTORQ 0x10 |
57 | #define BIT_WRRQ 0x04 |
58 | |
59 | /* CTRL1 register bitmasks */ |
60 | #define BIT_MODRQ 0x08 |
61 | #define BIT_FORMRQ 0x04 |
62 | #define BIT_SHDREN 0x01 |
63 | |
64 | /* CTRL2 register bitmask */ |
65 | #define BIT_VALST 0x80 |
66 | |
67 | /* PicoDrive: doing DMA at once, not using callbacks */ |
68 | //#define DMA_BYTES_PER_LINE 512 |
69 | |
70 | enum dma_type { |
71 | word_ram_0_dma_w = 1, |
72 | word_ram_1_dma_w = 2, |
73 | word_ram_2M_dma_w = 3, |
74 | pcm_ram_dma_w = 4, |
75 | prg_ram_dma_w = 5, |
76 | }; |
77 | |
78 | /* CDC hardware */ |
79 | typedef struct |
80 | { |
81 | uint8 ifstat; |
82 | uint8 ifctrl; |
83 | reg16_t dbc; |
84 | reg16_t dac; |
85 | reg16_t pt; |
86 | reg16_t wa; |
87 | uint8 ctrl[2]; |
88 | uint8 head[2][4]; |
89 | uint8 stat[4]; |
90 | int cycles; |
91 | //void (*dma_w)(unsigned int words); |
92 | int dma_w; |
93 | uint8 ram[0x4000 + 2352]; /* 16K external RAM (with one block overhead to handle buffer overrun) */ |
94 | } cdc_t; |
95 | |
96 | static cdc_t cdc; |
97 | |
98 | void cdc_init(void) |
99 | { |
100 | memset(&cdc, 0, sizeof(cdc_t)); |
101 | } |
102 | |
103 | void cdc_reset(void) |
104 | { |
105 | /* reset CDC register index */ |
106 | Pico_mcd->regs[0x04>>1].byte.l = 0x00; |
107 | |
108 | /* reset CDC registers */ |
109 | cdc.ifstat = 0xff; |
110 | cdc.ifctrl = 0x00; |
111 | cdc.ctrl[0] = 0x00; |
112 | cdc.ctrl[1] = 0x00; |
113 | cdc.stat[0] = 0x00; |
114 | cdc.stat[1] = 0x00; |
115 | cdc.stat[2] = 0x00; |
116 | cdc.stat[3] = 0x80; |
117 | cdc.head[0][0] = 0x00; |
118 | cdc.head[0][1] = 0x00; |
119 | cdc.head[0][2] = 0x00; |
120 | cdc.head[0][3] = 0x01; |
121 | cdc.head[1][0] = 0x00; |
122 | cdc.head[1][1] = 0x00; |
123 | cdc.head[1][2] = 0x00; |
124 | cdc.head[1][3] = 0x00; |
125 | |
126 | /* reset CDC cycle counter */ |
127 | cdc.cycles = 0; |
128 | |
129 | /* DMA transfer disabled */ |
130 | cdc.dma_w = 0; |
131 | } |
132 | |
133 | int cdc_context_save(uint8 *state) |
134 | { |
135 | uint8 tmp8; |
136 | int bufferptr = 0; |
137 | |
138 | if (cdc.dma_w == pcm_ram_dma_w) |
139 | { |
140 | tmp8 = 1; |
141 | } |
142 | else if (cdc.dma_w == prg_ram_dma_w) |
143 | { |
144 | tmp8 = 2; |
145 | } |
146 | else if (cdc.dma_w == word_ram_0_dma_w) |
147 | { |
148 | tmp8 = 3; |
149 | } |
150 | else if (cdc.dma_w == word_ram_1_dma_w) |
151 | { |
152 | tmp8 = 4; |
153 | } |
154 | else if (cdc.dma_w == word_ram_2M_dma_w) |
155 | { |
156 | tmp8 = 5; |
157 | } |
158 | else |
159 | { |
160 | tmp8 = 0; |
161 | } |
162 | |
163 | save_param(&cdc, sizeof(cdc)); |
164 | save_param(&tmp8, 1); |
165 | |
166 | return bufferptr; |
167 | } |
168 | |
169 | int cdc_context_load(uint8 *state) |
170 | { |
171 | uint8 tmp8; |
172 | int bufferptr = 0; |
173 | |
174 | load_param(&cdc, sizeof(cdc)); |
175 | load_param(&tmp8, 1); |
176 | |
177 | switch (tmp8) |
178 | { |
179 | case 1: |
180 | cdc.dma_w = pcm_ram_dma_w; |
181 | break; |
182 | case 2: |
183 | cdc.dma_w = prg_ram_dma_w; |
184 | break; |
185 | case 3: |
186 | cdc.dma_w = word_ram_0_dma_w; |
187 | break; |
188 | case 4: |
189 | cdc.dma_w = word_ram_1_dma_w; |
190 | break; |
191 | case 5: |
192 | cdc.dma_w = word_ram_2M_dma_w; |
193 | break; |
194 | default: |
195 | cdc.dma_w = 0; |
196 | break; |
197 | } |
198 | |
199 | return bufferptr; |
200 | } |
201 | |
202 | int cdc_context_load_old(uint8 *state) |
203 | { |
204 | #define old_load(v, ofs) \ |
205 | memcpy(&cdc.v, state + ofs, sizeof(cdc.v)) |
206 | |
207 | memcpy(cdc.ram, state, 0x4000); |
208 | old_load(ifstat, 67892); |
209 | old_load(ifctrl, 67924); |
210 | old_load(dbc, 67896); |
211 | old_load(dac, 67900); |
212 | old_load(pt, 67908); |
213 | old_load(wa, 67912); |
214 | old_load(ctrl, 67928); |
215 | old_load(head[0], 67904); |
216 | old_load(stat, 67916); |
217 | |
218 | cdc.dma_w = 0; |
219 | switch (Pico_mcd->regs[0x04>>1].byte.h & 0x07) |
220 | { |
221 | case 4: /* PCM RAM DMA */ |
222 | cdc.dma_w = pcm_ram_dma_w; |
223 | break; |
224 | case 5: /* PRG-RAM DMA */ |
225 | cdc.dma_w = prg_ram_dma_w; |
226 | break; |
227 | case 7: /* WORD-RAM DMA */ |
228 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x04) |
229 | { |
230 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x01) |
231 | cdc.dma_w = word_ram_0_dma_w; |
232 | else |
233 | cdc.dma_w = word_ram_1_dma_w; |
234 | } |
235 | else |
236 | { |
237 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x02) |
238 | cdc.dma_w = word_ram_2M_dma_w; |
239 | } |
240 | break; |
241 | } |
242 | |
243 | return 0x10960; // sizeof(old_cdc) |
244 | #undef old_load |
245 | } |
246 | |
247 | static void do_dma(enum dma_type type, int words_in) |
248 | { |
249 | int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b]; |
250 | int src_addr = cdc.dac.w & 0x3ffe; |
251 | int dst_addr = dma_addr; |
252 | int words = words_in; |
253 | int dst_limit = 0; |
254 | uint8 *dst; |
255 | int len; |
256 | |
257 | elprintf(EL_CD, "dma %d %04x->%04x %x", |
258 | type, cdc.dac.w, dst_addr, words_in); |
259 | |
260 | switch (type) |
261 | { |
262 | case pcm_ram_dma_w: |
263 | dst_addr = (dst_addr << 2) & 0xffc; |
264 | if (dst_addr + words * 2 > 0x1000) { |
265 | elprintf(EL_ANOMALY, "pcm dma oflow: %x %x", dst_addr, words); |
266 | words = (0x1000 - dst_addr) / 2; |
267 | } |
268 | dst = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank]; |
269 | dst = dst + dst_addr; |
270 | while (words > 0) |
271 | { |
272 | if (src_addr + words * 2 > 0x4000) { |
273 | len = 0x4000 - src_addr; |
274 | memcpy(dst, cdc.ram + src_addr, len); |
275 | dst += len; |
276 | src_addr = 0; |
277 | words -= len / 2; |
278 | continue; |
279 | } |
280 | memcpy(dst, cdc.ram + src_addr, words * 2); |
281 | break; |
282 | } |
283 | goto update_dma; |
284 | |
285 | case prg_ram_dma_w: |
286 | dst_addr <<= 3; |
287 | dst = Pico_mcd->prg_ram + dst_addr; |
288 | dst_limit = 0x80000; |
289 | break; |
290 | |
291 | case word_ram_0_dma_w: |
292 | dst_addr = (dst_addr << 3) & 0x1fffe; |
293 | dst = Pico_mcd->word_ram1M[0] + dst_addr; |
294 | dst_limit = 0x20000; |
295 | break; |
296 | |
297 | case word_ram_1_dma_w: |
298 | dst_addr = (dst_addr << 3) & 0x1fffe; |
299 | dst = Pico_mcd->word_ram1M[1] + dst_addr; |
300 | dst_limit = 0x20000; |
301 | break; |
302 | |
303 | case word_ram_2M_dma_w: |
304 | dst_addr = (dst_addr << 3) & 0x3fffe; |
305 | dst = Pico_mcd->word_ram2M + dst_addr; |
306 | dst_limit = 0x40000; |
307 | break; |
308 | |
309 | default: |
310 | elprintf(EL_ANOMALY, "invalid dma: %d", type); |
311 | goto update_dma; |
312 | } |
313 | |
314 | if (dst_addr + words * 2 > dst_limit) { |
315 | elprintf(EL_ANOMALY, "cd dma %d oflow: %x %x", type, dst_addr, words); |
316 | words = (dst_limit - dst_addr) / 2; |
317 | } |
318 | while (words > 0) |
319 | { |
320 | if (src_addr + words * 2 > 0x4000) { |
321 | len = 0x4000 - src_addr; |
322 | memcpy16bswap((void *)dst, cdc.ram + src_addr, len / 2); |
323 | dst += len; |
324 | src_addr = 0; |
325 | words -= len / 2; |
326 | continue; |
327 | } |
328 | memcpy16bswap((void *)dst, cdc.ram + src_addr, words); |
329 | break; |
330 | } |
331 | |
332 | update_dma: |
333 | /* update DMA addresses */ |
334 | cdc.dac.w += words_in * 2; |
335 | if (type == pcm_ram_dma_w) |
336 | dma_addr += words_in >> 1; |
337 | else |
338 | dma_addr += words_in >> 2; |
339 | |
340 | Pico_mcd->s68k_regs[0x0a] = dma_addr >> 8; |
341 | Pico_mcd->s68k_regs[0x0b] = dma_addr; |
342 | } |
343 | |
344 | // tmp |
345 | static void cdd_read_data(uint8 *dst) |
346 | { |
347 | int lba = Pico_mcd->scd.Cur_LBA; |
348 | |
349 | /* only read DATA track sectors */ |
350 | if (0 <= lba && lba < Pico_mcd->TOC.Tracks[0].Length) |
351 | { |
352 | /* read sector data (Mode 1 = 2048 bytes) */ |
353 | PicoCDBufferRead(dst, lba); |
354 | } |
355 | } |
356 | |
357 | void cdc_dma_update(void) |
358 | { |
359 | /* end of DMA transfer ? */ |
360 | //if (cdc.dbc.w < DMA_BYTES_PER_LINE) |
361 | { |
362 | /* transfer remaining words using 16-bit DMA */ |
363 | //cdc.dma_w((cdc.dbc.w + 1) >> 1); |
364 | do_dma(cdc.dma_w, (cdc.dbc.w + 1) >> 1); |
365 | |
366 | /* reset data byte counter (DBCH bits 4-7 should be set to 1) */ |
367 | cdc.dbc.w = 0xf000; |
368 | |
369 | /* clear !DTEN and !DTBSY */ |
370 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
371 | |
372 | /* pending Data Transfer End interrupt */ |
373 | cdc.ifstat &= ~BIT_DTEI; |
374 | |
375 | /* Data Transfer End interrupt enabled ? */ |
376 | if (cdc.ifctrl & BIT_DTEIEN) |
377 | { |
378 | /* level 5 interrupt enabled ? */ |
379 | if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5) |
380 | { |
381 | /* update IRQ level */ |
382 | elprintf(EL_INTS, "cdc DTE irq 5"); |
383 | SekInterruptS68k(5); |
384 | } |
385 | } |
386 | |
387 | /* clear DSR bit & set EDT bit (SCD register $04) */ |
388 | Pico_mcd->regs[0x04>>1].byte.h = (Pico_mcd->regs[0x04>>1].byte.h & 0x07) | 0x80; |
389 | |
390 | /* disable DMA transfer */ |
391 | cdc.dma_w = 0; |
392 | } |
393 | #if 0 |
394 | else |
395 | { |
396 | /* transfer all words using 16-bit DMA */ |
397 | cdc.dma_w(DMA_BYTES_PER_LINE >> 1); |
398 | |
399 | /* decrement data byte counter */ |
400 | cdc.dbc.w -= length; |
401 | } |
402 | #endif |
403 | } |
404 | |
405 | int cdc_decoder_update(uint8 header[4]) |
406 | { |
407 | /* data decoding enabled ? */ |
408 | if (cdc.ctrl[0] & BIT_DECEN) |
409 | { |
410 | /* update HEAD registers */ |
411 | memcpy(cdc.head[0], header, sizeof(cdc.head[0])); |
412 | |
413 | /* set !VALST */ |
414 | cdc.stat[3] = 0x00; |
415 | |
416 | /* pending decoder interrupt */ |
417 | cdc.ifstat &= ~BIT_DECI; |
418 | |
419 | /* decoder interrupt enabled ? */ |
420 | if (cdc.ifctrl & BIT_DECIEN) |
421 | { |
422 | /* level 5 interrupt enabled ? */ |
423 | if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5) |
424 | { |
425 | /* update IRQ level */ |
426 | elprintf(EL_INTS, "cdc DEC irq 5"); |
427 | SekInterruptS68k(5); |
428 | } |
429 | } |
430 | |
431 | /* buffer RAM write enabled ? */ |
432 | if (cdc.ctrl[0] & BIT_WRRQ) |
433 | { |
434 | uint16 offset; |
435 | |
436 | /* increment block pointer */ |
437 | cdc.pt.w += 2352; |
438 | |
439 | /* increment write address */ |
440 | cdc.wa.w += 2352; |
441 | |
442 | /* CDC buffer address */ |
443 | offset = cdc.pt.w & 0x3fff; |
444 | |
445 | /* write CDD block header (4 bytes) */ |
446 | memcpy(cdc.ram + offset, header, 4); |
447 | |
448 | /* write CDD block data (2048 bytes) */ |
449 | cdd_read_data(cdc.ram + 4 + offset); |
450 | |
451 | /* take care of buffer overrun */ |
452 | if (offset > (0x4000 - 2048 - 4)) |
453 | { |
454 | /* data should be written at the start of buffer */ |
455 | memcpy(cdc.ram, cdc.ram + 0x4000, offset + 2048 + 4 - 0x4000); |
456 | } |
457 | |
458 | /* read next data block */ |
459 | return 1; |
460 | } |
461 | } |
462 | |
463 | /* keep decoding same data block if Buffer Write is disabled */ |
464 | return 0; |
465 | } |
466 | |
467 | void cdc_reg_w(unsigned char data) |
468 | { |
469 | #ifdef LOG_CDC |
470 | elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->regs[0x04>>1].byte.l & 0x0F, data); |
471 | #endif |
472 | switch (Pico_mcd->regs[0x04>>1].byte.l & 0x0F) |
473 | { |
474 | case 0x01: /* IFCTRL */ |
475 | { |
476 | /* pending interrupts ? */ |
477 | if (((data & BIT_DTEIEN) && !(cdc.ifstat & BIT_DTEI)) || |
478 | ((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI))) |
479 | { |
480 | /* level 5 interrupt enabled ? */ |
481 | if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5) |
482 | { |
483 | /* update IRQ level */ |
484 | elprintf(EL_INTS, "cdc pending irq 5"); |
485 | SekInterruptS68k(5); |
486 | } |
487 | } |
488 | else // if (scd.pending & (1 << 5)) |
489 | { |
490 | /* clear pending level 5 interrupts */ |
491 | SekInterruptClearS68k(5); |
492 | } |
493 | |
494 | /* abort any data transfer if data output is disabled */ |
495 | if (!(data & BIT_DOUTEN)) |
496 | { |
497 | /* clear !DTBSY and !DTEN */ |
498 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
499 | } |
500 | |
501 | cdc.ifctrl = data; |
502 | Pico_mcd->regs[0x04>>1].byte.l = 0x02; |
503 | break; |
504 | } |
505 | |
506 | case 0x02: /* DBCL */ |
507 | cdc.dbc.byte.l = data; |
508 | Pico_mcd->regs[0x04>>1].byte.l = 0x03; |
509 | break; |
510 | |
511 | case 0x03: /* DBCH */ |
512 | cdc.dbc.byte.h = data; |
513 | Pico_mcd->regs[0x04>>1].byte.l = 0x04; |
514 | break; |
515 | |
516 | case 0x04: /* DACL */ |
517 | cdc.dac.byte.l = data; |
518 | Pico_mcd->regs[0x04>>1].byte.l = 0x05; |
519 | break; |
520 | |
521 | case 0x05: /* DACH */ |
522 | cdc.dac.byte.h = data; |
523 | Pico_mcd->regs[0x04>>1].byte.l = 0x06; |
524 | break; |
525 | |
526 | case 0x06: /* DTRG */ |
527 | { |
528 | /* start data transfer if data output is enabled */ |
529 | if (cdc.ifctrl & BIT_DOUTEN) |
530 | { |
531 | /* set !DTBSY */ |
532 | cdc.ifstat &= ~BIT_DTBSY; |
533 | |
534 | /* clear DBCH bits 4-7 */ |
535 | cdc.dbc.byte.h &= 0x0f; |
536 | |
537 | /* clear EDT & DSR bits (SCD register $04) */ |
538 | Pico_mcd->regs[0x04>>1].byte.h &= 0x07; |
539 | |
540 | cdc.dma_w = 0; |
541 | |
542 | /* setup data transfer destination */ |
543 | switch (Pico_mcd->regs[0x04>>1].byte.h & 0x07) |
544 | { |
545 | case 2: /* MAIN-CPU host read */ |
546 | case 3: /* SUB-CPU host read */ |
547 | { |
548 | /* set !DTEN */ |
549 | cdc.ifstat &= ~BIT_DTEN; |
550 | |
551 | /* set DSR bit (register $04) */ |
552 | Pico_mcd->regs[0x04>>1].byte.h |= 0x40; |
553 | break; |
554 | } |
555 | |
556 | case 4: /* PCM RAM DMA */ |
557 | { |
558 | cdc.dma_w = pcm_ram_dma_w; |
559 | break; |
560 | } |
561 | |
562 | case 5: /* PRG-RAM DMA */ |
563 | { |
564 | cdc.dma_w = prg_ram_dma_w; |
565 | break; |
566 | } |
567 | |
568 | case 7: /* WORD-RAM DMA */ |
569 | { |
570 | /* check memory mode */ |
571 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x04) |
572 | { |
573 | /* 1M mode */ |
574 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x01) |
575 | { |
576 | /* Word-RAM bank 0 is assigned to SUB-CPU */ |
577 | cdc.dma_w = word_ram_0_dma_w; |
578 | } |
579 | else |
580 | { |
581 | /* Word-RAM bank 1 is assigned to SUB-CPU */ |
582 | cdc.dma_w = word_ram_1_dma_w; |
583 | } |
584 | } |
585 | else |
586 | { |
587 | /* 2M mode */ |
588 | if (Pico_mcd->regs[0x02 >> 1].byte.l & 0x02) |
589 | { |
590 | /* only process DMA if Word-RAM is assigned to SUB-CPU */ |
591 | cdc.dma_w = word_ram_2M_dma_w; |
592 | } |
593 | } |
594 | break; |
595 | } |
596 | |
597 | default: /* invalid */ |
598 | { |
599 | elprintf(EL_ANOMALY, "invalid CDC tranfer destination (%d)", |
600 | Pico_mcd->regs[0x04>>1].byte.h & 0x07); |
601 | break; |
602 | } |
603 | } |
604 | |
605 | if (cdc.dma_w) |
606 | pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc.w / 2); |
607 | } |
608 | |
609 | Pico_mcd->regs[0x04>>1].byte.l = 0x07; |
610 | break; |
611 | } |
612 | |
613 | case 0x07: /* DTACK */ |
614 | { |
615 | /* clear pending data transfer end interrupt */ |
616 | cdc.ifstat |= BIT_DTEI; |
617 | |
618 | /* clear DBCH bits 4-7 */ |
619 | cdc.dbc.byte.h &= 0x0f; |
620 | |
621 | #if 0 |
622 | /* no pending decoder interrupt ? */ |
623 | if ((cdc.ifstat | BIT_DECI) || !(cdc.ifctrl & BIT_DECIEN)) |
624 | { |
625 | /* clear pending level 5 interrupt */ |
626 | SekInterruptClearS68k(5); |
627 | } |
628 | #endif |
629 | Pico_mcd->regs[0x04>>1].byte.l = 0x08; |
630 | break; |
631 | } |
632 | |
633 | case 0x08: /* WAL */ |
634 | cdc.wa.byte.l = data; |
635 | Pico_mcd->regs[0x04>>1].byte.l = 0x09; |
636 | break; |
637 | |
638 | case 0x09: /* WAH */ |
639 | cdc.wa.byte.h = data; |
640 | Pico_mcd->regs[0x04>>1].byte.l = 0x0a; |
641 | break; |
642 | |
643 | case 0x0a: /* CTRL0 */ |
644 | { |
645 | /* set CRCOK bit only if decoding is enabled */ |
646 | cdc.stat[0] = data & BIT_DECEN; |
647 | |
648 | /* update decoding mode */ |
649 | if (data & BIT_AUTORQ) |
650 | { |
651 | /* set MODE bit according to CTRL1 register & clear FORM bit */ |
652 | cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ; |
653 | } |
654 | else |
655 | { |
656 | /* set MODE & FORM bits according to CTRL1 register */ |
657 | cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ); |
658 | } |
659 | |
660 | cdc.ctrl[0] = data; |
661 | Pico_mcd->regs[0x04>>1].byte.l = 0x0b; |
662 | break; |
663 | } |
664 | |
665 | case 0x0b: /* CTRL1 */ |
666 | { |
667 | /* update decoding mode */ |
668 | if (cdc.ctrl[0] & BIT_AUTORQ) |
669 | { |
670 | /* set MODE bit according to CTRL1 register & clear FORM bit */ |
671 | cdc.stat[2] = data & BIT_MODRQ; |
672 | } |
673 | else |
674 | { |
675 | /* set MODE & FORM bits according to CTRL1 register */ |
676 | cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ); |
677 | } |
678 | |
679 | cdc.ctrl[1] = data; |
680 | Pico_mcd->regs[0x04>>1].byte.l = 0x0c; |
681 | break; |
682 | } |
683 | |
684 | case 0x0c: /* PTL */ |
685 | cdc.pt.byte.l = data; |
686 | Pico_mcd->regs[0x04>>1].byte.l = 0x0d; |
687 | break; |
688 | |
689 | case 0x0d: /* PTH */ |
690 | cdc.pt.byte.h = data; |
691 | Pico_mcd->regs[0x04>>1].byte.l = 0x0e; |
692 | break; |
693 | |
694 | case 0x0e: /* CTRL2 (unused) */ |
695 | Pico_mcd->regs[0x04>>1].byte.l = 0x0f; |
696 | break; |
697 | |
698 | case 0x0f: /* RESET */ |
699 | cdc_reset(); |
700 | break; |
701 | |
702 | default: /* by default, SBOUT is not used */ |
703 | break; |
704 | } |
705 | } |
706 | |
707 | unsigned char cdc_reg_r(void) |
708 | { |
709 | switch (Pico_mcd->regs[0x04>>1].byte.l & 0x0F) |
710 | { |
711 | case 0x01: /* IFSTAT */ |
712 | Pico_mcd->regs[0x04>>1].byte.l = 0x02; |
713 | return cdc.ifstat; |
714 | |
715 | case 0x02: /* DBCL */ |
716 | Pico_mcd->regs[0x04>>1].byte.l = 0x03; |
717 | return cdc.dbc.byte.l; |
718 | |
719 | case 0x03: /* DBCH */ |
720 | Pico_mcd->regs[0x04>>1].byte.l = 0x04; |
721 | return cdc.dbc.byte.h; |
722 | |
723 | case 0x04: /* HEAD0 */ |
724 | Pico_mcd->regs[0x04>>1].byte.l = 0x05; |
725 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0]; |
726 | |
727 | case 0x05: /* HEAD1 */ |
728 | Pico_mcd->regs[0x04>>1].byte.l = 0x06; |
729 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1]; |
730 | |
731 | case 0x06: /* HEAD2 */ |
732 | Pico_mcd->regs[0x04>>1].byte.l = 0x07; |
733 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2]; |
734 | |
735 | case 0x07: /* HEAD3 */ |
736 | Pico_mcd->regs[0x04>>1].byte.l = 0x08; |
737 | return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3]; |
738 | |
739 | case 0x08: /* PTL */ |
740 | Pico_mcd->regs[0x04>>1].byte.l = 0x09; |
741 | return cdc.pt.byte.l; |
742 | |
743 | case 0x09: /* PTH */ |
744 | Pico_mcd->regs[0x04>>1].byte.l = 0x0a; |
745 | return cdc.pt.byte.h; |
746 | |
747 | case 0x0a: /* WAL */ |
748 | Pico_mcd->regs[0x04>>1].byte.l = 0x0b; |
749 | return cdc.wa.byte.l; |
750 | |
751 | case 0x0b: /* WAH */ |
752 | Pico_mcd->regs[0x04>>1].byte.l = 0x0c; |
753 | return cdc.wa.byte.h; |
754 | |
755 | case 0x0c: /* STAT0 */ |
756 | Pico_mcd->regs[0x04>>1].byte.l = 0x0d; |
757 | return cdc.stat[0]; |
758 | |
759 | case 0x0d: /* STAT1 (always return 0) */ |
760 | Pico_mcd->regs[0x04>>1].byte.l = 0x0e; |
761 | return 0x00; |
762 | |
763 | case 0x0e: /* STAT2 */ |
764 | Pico_mcd->regs[0x04>>1].byte.l = 0x0f; |
765 | return cdc.stat[2]; |
766 | |
767 | case 0x0f: /* STAT3 */ |
768 | { |
769 | uint8 data = cdc.stat[3]; |
770 | |
771 | /* clear !VALST (note: this is not 100% correct but BIOS do not seem to care) */ |
772 | cdc.stat[3] = BIT_VALST; |
773 | |
774 | /* clear pending decoder interrupt */ |
775 | cdc.ifstat |= BIT_DECI; |
776 | |
777 | #if 0 |
778 | /* no pending data transfer end interrupt */ |
779 | if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN)) |
780 | { |
781 | /* clear pending level 5 interrupt */ |
782 | SekInterruptClearS68k(5); |
783 | } |
784 | #endif |
785 | |
786 | Pico_mcd->regs[0x04>>1].byte.l = 0x00; |
787 | return data; |
788 | } |
789 | |
790 | default: /* by default, COMIN is always empty */ |
791 | return 0xff; |
792 | } |
793 | } |
794 | |
795 | unsigned short cdc_host_r(void) |
796 | { |
797 | /* check if data is available */ |
798 | if (!(cdc.ifstat & BIT_DTEN)) |
799 | { |
800 | /* read data word from CDC RAM buffer */ |
801 | uint8 *datap = cdc.ram + (cdc.dac.w & 0x3ffe); |
802 | uint16 data = (datap[0] << 8) | datap[1]; |
803 | |
804 | #ifdef LOG_CDC |
805 | error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac.w, data, cdc.dbc.w, s68k.pc); |
806 | #endif |
807 | |
808 | /* increment data address counter */ |
809 | cdc.dac.w += 2; |
810 | |
811 | /* decrement data byte counter */ |
812 | cdc.dbc.w -= 2; |
813 | |
814 | /* end of transfer ? */ |
815 | if ((int16)cdc.dbc.w <= 0) |
816 | { |
817 | /* reset data byte counter (DBCH bits 4-7 should be set to 1) */ |
818 | cdc.dbc.w = 0xf000; |
819 | |
820 | /* clear !DTEN and !DTBSY */ |
821 | cdc.ifstat |= (BIT_DTBSY | BIT_DTEN); |
822 | |
823 | /* pending Data Transfer End interrupt */ |
824 | cdc.ifstat &= ~BIT_DTEI; |
825 | |
826 | /* Data Transfer End interrupt enabled ? */ |
827 | if (cdc.ifctrl & BIT_DTEIEN) |
828 | { |
829 | /* level 5 interrupt enabled ? */ |
830 | if (Pico_mcd->regs[0x32>>1].byte.l & PCDS_IEN5) |
831 | { |
832 | /* update IRQ level */ |
833 | elprintf(EL_INTS, "cdc DTE irq 5"); |
834 | SekInterruptS68k(5); |
835 | } |
836 | } |
837 | |
838 | /* clear DSR bit & set EDT bit (SCD register $04) */ |
839 | Pico_mcd->regs[0x04>>1].byte.h = (Pico_mcd->regs[0x04>>1].byte.h & 0x07) | 0x80; |
840 | } |
841 | |
842 | return data; |
843 | } |
844 | |
845 | #ifdef LOG_CDC |
846 | error("error reading CDC host (data transfer disabled)\n"); |
847 | #endif |
848 | return 0xffff; |
849 | } |
850 | |
851 | // vim:shiftwidth=2:ts=2:expandtab |