32x: mode2 draw, debug, poll detection
[picodrive.git] / pico / eeprom.c
CommitLineData
45f2f245 1/*\r
2 * rarely used EEPROM code\r
3 *\r
4 * (see Genesis Plus for Wii/GC code and docs for info,\r
5 * full game list and better code).\r
6 */\r
7\r
8#include "pico_int.h"\r
9\r
10static unsigned int last_write = 0xffff0000;\r
11\r
12// eeprom_status: LA.. s.la (L=pending SCL, A=pending SDA,\r
13// s=started, l=old SCL, a=old SDA)\r
14static void EEPROM_write_do(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
15{\r
16 unsigned int sreg = Pico.m.eeprom_status, saddr = Pico.m.eeprom_addr;\r
17 unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
18\r
19 elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
20 (d&2)>>1, d&1, SekCyclesDoneT() - last_write);\r
21 saddr &= 0x1fff;\r
22\r
23 if(sreg & d & 2) {\r
24 // SCL was and is still high..\r
25 if((sreg & 1) && !(d&1)) {\r
26 // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
27 elprintf(EL_EEPROM, "eeprom: -start-");\r
28 //saddr = 0;\r
29 scyc = 0;\r
30 sreg |= 8;\r
31 } else if(!(sreg & 1) && (d&1)) {\r
32 // SDA went high == stop command\r
33 elprintf(EL_EEPROM, "eeprom: -stop-");\r
34 sreg &= ~8;\r
35 }\r
36 }\r
37 else if((sreg & 8) && !(sreg & 2) && (d&2))\r
38 {\r
39 // we are started and SCL went high - next cycle\r
40 scyc++; // pre-increment\r
41 if(SRam.eeprom_type) {\r
42 // X24C02+\r
43 if((ssa&1) && scyc == 18) {\r
44 scyc = 9;\r
45 saddr++; // next address in read mode\r
46 /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
47 }\r
48 else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
49 else if(scyc == 36) scyc = 27;\r
50 } else {\r
51 // X24C01\r
52 if(scyc == 18) {\r
53 scyc = 9; // wrap\r
54 if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
55 }\r
56 }\r
57 elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);\r
58 }\r
59 else if((sreg & 8) && (sreg & 2) && !(d&2))\r
60 {\r
61 // we are started and SCL went low (falling edge)\r
62 if(SRam.eeprom_type) {\r
63 // X24C02+\r
64 if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
65 else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {\r
66 if(!(ssa&1)) {\r
67 // data write\r
68 unsigned char *pm=SRam.data+saddr;\r
69 *pm <<= 1; *pm |= d&1;\r
70 if(scyc == 26 || scyc == 35) {\r
71 saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
72 elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
73 }\r
74 SRam.changed = 1;\r
75 }\r
76 } else if(scyc > 9) {\r
77 if(!(ssa&1)) {\r
78 // we latch another addr bit\r
79 saddr<<=1;\r
80 if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
81 saddr|=d&1;\r
82 if(scyc==17||scyc==26) {\r
83 elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
84 if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
85 }\r
86 }\r
87 } else {\r
88 // slave address\r
89 ssa<<=1; ssa|=d&1;\r
90 if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);\r
91 }\r
92 } else {\r
93 // X24C01\r
94 if(scyc == 9); // ACK cycle, do nothing\r
95 else if(scyc > 9) {\r
96 if(!(saddr&1)) {\r
97 // data write\r
98 unsigned char *pm=SRam.data+(saddr>>1);\r
99 *pm <<= 1; *pm |= d&1;\r
100 if(scyc == 17) {\r
101 saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented\r
102 elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
103 }\r
104 SRam.changed = 1;\r
105 }\r
106 } else {\r
107 // we latch another addr bit\r
108 saddr<<=1; saddr|=d&1; saddr&=0xff;\r
109 if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);\r
110 }\r
111 }\r
112 }\r
113\r
114 sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
115 Pico.m.eeprom_status = (unsigned char) sreg;\r
116 Pico.m.eeprom_cycle = (unsigned char) scyc;\r
117 Pico.m.eeprom_slave = (unsigned char) ssa;\r
118 Pico.m.eeprom_addr = (unsigned short)saddr;\r
119}\r
120\r
121static void EEPROM_upd_pending(unsigned int d)\r
122{\r
123 unsigned int d1, sreg = Pico.m.eeprom_status;\r
124\r
125 sreg &= ~0xc0;\r
126\r
127 // SCL\r
128 d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
129 sreg |= d1 << 7;\r
130\r
131 // SDA in\r
132 d1 = (d >> SRam.eeprom_bit_in) & 1;\r
133 sreg |= d1 << 6;\r
134\r
135 Pico.m.eeprom_status = (unsigned char) sreg;\r
136}\r
137\r
138void EEPROM_write16(unsigned int d)\r
139{\r
140 // this diff must be at most 16 for NBA Jam to work\r
141 if (SekCyclesDoneT() - last_write < 16) {\r
142 // just update pending state\r
143 elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",\r
144 SekCyclesDoneT() - last_write);\r
145 EEPROM_upd_pending(d);\r
146 } else {\r
147 int srs = Pico.m.eeprom_status;\r
148 EEPROM_write_do(srs >> 6); // execute pending\r
149 EEPROM_upd_pending(d);\r
150 if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed\r
151 last_write = SekCyclesDoneT();\r
152 }\r
153}\r
154\r
155void EEPROM_write8(unsigned int a, unsigned int d)\r
156{\r
157 unsigned char *wb = Pico.m.eeprom_wb;\r
158 wb[a & 1] = d;\r
159 EEPROM_write16((wb[0] << 8) | wb[1]);\r
160}\r
161\r
162unsigned int EEPROM_read(void)\r
163{\r
164 unsigned int shift, d;\r
165 unsigned int sreg, saddr, scyc, ssa, interval;\r
166\r
167 // flush last pending write\r
168 EEPROM_write_do(Pico.m.eeprom_status>>6);\r
169\r
170 sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
171 interval = SekCyclesDoneT() - last_write;\r
172 d = (sreg>>6)&1; // use SDA as "open bus"\r
173\r
174 // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
175 // this is probably valid because data changes occur while SCL is low and data can be read\r
176 // before it's actual cycle begins.\r
177 if (!(sreg&0x80) && interval >= 24) {\r
178 elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);\r
179 scyc++;\r
180 }\r
181\r
182 if (!(sreg & 8)); // not started, use open bus\r
183 else if (scyc == 9 || scyc == 18 || scyc == 27) {\r
184 elprintf(EL_EEPROM, "eeprom: r ack");\r
185 d = 0;\r
186 } else if (scyc > 9 && scyc < 18) {\r
187 // started and first command word received\r
188 shift = 17-scyc;\r
189 if (SRam.eeprom_type) {\r
190 // X24C02+\r
191 if (ssa&1) {\r
192 elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
193 if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
194 d = (SRam.data[saddr]>>shift)&1;\r
195 }\r
196 } else {\r
197 // X24C01\r
198 if (saddr&1) {\r
199 elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
200 if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
201 d = (SRam.data[saddr>>1]>>shift)&1;\r
202 }\r
203 }\r
204 }\r
205\r
206 return (d << SRam.eeprom_bit_out);\r
207}\r
208\r