[picodrive.git] / pico / misc.c

// This is part of Pico Library\r
\r
// (c) Copyright 2006 notaz, All rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
\r
\r
#include "pico_int.h"\r
\r
// H-counter table for hvcounter reads in 40col mode\r
// based on Gens code\r
const unsigned char hcounts_40[] = {\r
0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,\r
0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x13,0x14,\r
0x14,0x15,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,\r
0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x20,0x20,0x20,0x21,0x21,\r
0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,\r
0x28,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,\r
0x2f,0x30,0x30,0x30,0x31,0x31,0x32,0x32,0x32,0x33,0x33,0x34,0x34,0x35,0x35,0x35,\r
0x36,0x36,0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3c,0x3c,\r
0x3d,0x3d,0x3d,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x41,0x41,0x42,0x42,0x42,0x43,\r
0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x47,0x47,0x47,0x48,0x48,0x49,0x49,0x4a,\r
0x4a,0x4a,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,0x4d,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,\r
0x51,0x51,0x52,0x52,0x52,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x57,0x57,\r
0x57,0x58,0x58,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5e,\r
0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x61,0x61,0x62,0x62,0x62,0x63,0x63,0x64,0x64,0x64,\r
0x65,0x65,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,\r
0x6c,0x6c,0x6c,0x6d,0x6d,0x6e,0x6e,0x6f,0x6f,0x6f,0x70,0x70,0x71,0x71,0x71,0x72,\r
0x72,0x73,0x73,0x74,0x74,0x74,0x75,0x75,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x79,\r
0x79,0x79,0x7a,0x7a,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7e,0x7e,0x7f,0x7f,0x7f,\r
0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x84,0x84,0x84,0x85,0x85,0x86,0x86,\r
0x86,0x87,0x87,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,\r
0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x90,0x90,0x91,0x91,0x91,0x92,0x92,0x93,0x93,0x94,\r
0x94,0x94,0x95,0x95,0x96,0x96,0x96,0x97,0x97,0x98,0x98,0x99,0x99,0x99,0x9a,0x9a,\r
0x9b,0x9b,0x9b,0x9c,0x9c,0x9d,0x9d,0x9e,0x9e,0x9e,0x9f,0x9f,0xa0,0xa0,0xa1,0xa1,\r
0xa1,0xa2,0xa2,0xa3,0xa3,0xa3,0xa4,0xa4,0xa5,0xa5,0xa6,0xa6,0xa6,0xa7,0xa7,0xa8,\r
0xa8,0xa9,0xa9,0xa9,0xaa,0xaa,0xab,0xab,0xab,0xac,0xac,0xad,0xad,0xae,0xae,0xae,\r
0xaf,0xaf,0xb0,0xb0,\r
0xe4,0xe4,0xe4,0xe5,0xe5,0xe6,0xe6,0xe6,0xe7,0xe7,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,\r
0xea,0xeb,0xeb,0xeb,0xec,0xec,0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf1,\r
0xf1,0xf1,0xf2,0xf2,0xf3,0xf3,0xf3,0xf4,0xf4,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,\r
0xf8,0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfd,0xfd,0xfe,0xfe,\r
0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x03,0x04,0x04,0x05,\r
0x05,0x06,0x06,0x06,\r
0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,\r
0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,\r
};\r
\r
// H-counter table for hvcounter reads in 32col mode\r
const unsigned char hcounts_32[] = {\r
0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,\r
0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x0f,0x10,\r
0x10,0x10,0x11,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x13,0x14,0x14,0x14,0x15,0x15,\r
0x15,0x16,0x16,0x17,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x19,0x1a,0x1a,0x1a,0x1b,\r
0x1b,0x1b,0x1c,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x1f,0x20,0x20,0x20,\r
0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x24,0x25,0x25,0x26,0x26,\r
0x26,0x27,0x27,0x27,0x28,0x28,0x28,0x29,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2b,\r
0x2c,0x2c,0x2c,0x2d,0x2d,0x2e,0x2e,0x2e,0x2f,0x2f,0x2f,0x30,0x30,0x30,0x31,0x31,\r
0x31,0x32,0x32,0x32,0x33,0x33,0x33,0x34,0x34,0x34,0x35,0x35,0x36,0x36,0x36,0x37,\r
0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3b,0x3c,0x3c,\r
0x3d,0x3d,0x3d,0x3e,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x40,0x41,0x41,0x41,0x42,\r
0x42,0x42,0x43,0x43,0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x46,0x47,0x47,0x47,\r
0x48,0x48,0x48,0x49,0x49,0x49,0x4a,0x4a,0x4a,0x4b,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,\r
0x4d,0x4e,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,0x50,0x51,0x51,0x51,0x52,0x52,0x52,\r
0x53,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x56,0x57,0x57,0x57,0x58,0x58,\r
0x58,0x59,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5d,0x5e,\r
0x5e,0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x60,0x61,0x61,0x61,0x62,0x62,0x62,0x63,0x63,\r
0x64,0x64,0x64,0x65,0x65,0x65,0x66,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x68,0x69,\r
0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,0x6c,0x6c,0x6c,0x6d,0x6d,0x6d,0x6e,0x6e,0x6e,\r
0x6f,0x6f,0x6f,0x70,0x70,0x70,0x71,0x71,0x71,0x72,0x72,0x72,0x73,0x73,0x74,0x74,\r
0x74,0x75,0x75,0x75,0x76,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x78,0x79,0x79,0x79,\r
0x7a,0x7a,0x7b,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7d,0x7e,0x7e,0x7e,0x7f,0x7f,\r
0x7f,0x80,0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x83,0x84,0x84,0x84,0x85,\r
0x85,0x85,0x86,0x86,0x86,0x87,0x87,0x87,0x88,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,\r
0x8b,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,0x8d,0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x8f,0x90,\r
0x90,0x90,0x91,0x91,\r
0xe8,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,0xea,0xea,0xeb,0xeb,0xeb,0xec,0xec,0xec,0xed,\r
0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf0,0xf1,0xf1,0xf1,0xf2,0xf2,0xf2,\r
0xf3,0xf3,0xf3,0xf4,0xf4,0xf4,0xf5,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,0xf8,0xf8,\r
0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfc,0xfd,0xfd,0xfd,\r
0xfe,0xfe,0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x01,0x02,0x02,0x02,0x03,0x03,\r
0x03,0x04,0x04,0x04,\r
0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,\r
0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,\r
};\r
\r
\r
// rarely used EEPROM SRAM code\r
// known games which use this:\r
// Wonder Boy in Monster World, Megaman - The Wily Wars (X24C01, 128 bytes)\r
\r
// (see Genesis Plus for Wii/GC code and docs for info,\r
//  full game list and better code).\r
\r
unsigned int lastSSRamWrite = 0xffff0000;\r
\r
// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),\r
//                      d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)\r
PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
{\r
  unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
\r
  elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
    (d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);\r
  saddr&=0x1fff;\r
\r
  if(sreg & d & 2) {\r
    // SCL was and is still high..\r
    if((sreg & 1) && !(d&1)) {\r
      // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
      elprintf(EL_EEPROM, "eeprom: -start-");\r
      //saddr = 0;\r
      scyc = 0;\r
      sreg |= 8;\r
    } else if(!(sreg & 1) && (d&1)) {\r
      // SDA went high == stop command\r
      elprintf(EL_EEPROM, "eeprom: -stop-");\r
      sreg &= ~8;\r
    }\r
  }\r
  else if((sreg & 8) && !(sreg & 2) && (d&2))\r
  {\r
    // we are started and SCL went high - next cycle\r
    scyc++; // pre-increment\r
    if(SRam.eeprom_type) {\r
      // X24C02+\r
      if((ssa&1) && scyc == 18) {\r
        scyc = 9;\r
        saddr++; // next address in read mode\r
        /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
      }\r
      else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
      else if(scyc == 36) scyc = 27;\r
    } else {\r
      // X24C01\r
      if(scyc == 18) {\r
        scyc = 9;  // wrap\r
        if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
      }\r
    }\r
    elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);\r
  }\r
  else if((sreg & 8) && (sreg & 2) && !(d&2))\r
  {\r
    // we are started and SCL went low (falling edge)\r
    if(SRam.eeprom_type) {\r
      // X24C02+\r
      if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
      else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {\r
        if(!(ssa&1)) {\r
          // data write\r
          unsigned char *pm=SRam.data+saddr;\r
          *pm <<= 1; *pm |= d&1;\r
          if(scyc == 26 || scyc == 35) {\r
            saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
            elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
          }\r
          SRam.changed = 1;\r
        }\r
      } else if(scyc > 9) {\r
        if(!(ssa&1)) {\r
          // we latch another addr bit\r
          saddr<<=1;\r
          if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
          saddr|=d&1;\r
          if(scyc==17||scyc==26) {\r
            elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
            if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
          }\r
        }\r
      } else {\r
        // slave address\r
        ssa<<=1; ssa|=d&1;\r
        if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);\r
      }\r
    } else {\r
      // X24C01\r
      if(scyc == 9); // ACK cycle, do nothing\r
      else if(scyc > 9) {\r
        if(!(saddr&1)) {\r
          // data write\r
          unsigned char *pm=SRam.data+(saddr>>1);\r
          *pm <<= 1; *pm |= d&1;\r
          if(scyc == 17) {\r
            saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented\r
            elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
          }\r
          SRam.changed = 1;\r
        }\r
      } else {\r
        // we latch another addr bit\r
        saddr<<=1; saddr|=d&1; saddr&=0xff;\r
        if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);\r
      }\r
    }\r
  }\r
\r
  sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
  Pico.m.sram_reg    = (unsigned char) sreg;\r
  Pico.m.eeprom_cycle= (unsigned char) scyc;\r
  Pico.m.eeprom_slave= (unsigned char) ssa;\r
  Pico.m.eeprom_addr = (unsigned short)saddr;\r
}\r
\r
PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)\r
{\r
  unsigned int shift, d;\r
  unsigned int sreg, saddr, scyc, ssa, interval;\r
\r
  // flush last pending write\r
  SRAMWriteEEPROM(Pico.m.sram_reg>>6);\r
\r
  sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
  interval = SekCyclesDoneT()-lastSSRamWrite;\r
  d = (sreg>>6)&1; // use SDA as "open bus"\r
\r
  // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
  // this is probably valid because data changes occur while SCL is low and data can be read\r
  // before it's actual cycle begins.\r
  if (!(sreg&0x80) && interval >= 24) {\r
    elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);\r
    scyc++;\r
  }\r
\r
  if (!(sreg & 8)); // not started, use open bus\r
  else if (scyc == 9 || scyc == 18 || scyc == 27) {\r
    elprintf(EL_EEPROM, "eeprom: r ack");\r
    d = 0;\r
  } else if (scyc > 9 && scyc < 18) {\r
    // started and first command word received\r
    shift = 17-scyc;\r
    if (SRam.eeprom_type) {\r
      // X24C02+\r
      if (ssa&1) {\r
        elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
	if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
        d = (SRam.data[saddr]>>shift)&1;\r
      }\r
    } else {\r
      // X24C01\r
      if (saddr&1) {\r
        elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
	if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
        d = (SRam.data[saddr>>1]>>shift)&1;\r
      }\r
    }\r
  }\r
\r
  return (d << SRam.eeprom_bit_out);\r
}\r
\r
PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)\r
{\r
  unsigned int d1, sreg = Pico.m.sram_reg;\r
\r
  if (!((SRam.eeprom_abits^a)&1))\r
  {\r
    // SCL\r
    sreg &= ~0x80;\r
    d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
    sreg |= d1<<7;\r
  }\r
  if (!(((SRam.eeprom_abits>>1)^a)&1))\r
  {\r
    // SDA in\r
    sreg &= ~0x40;\r
    d1 = (d >> SRam.eeprom_bit_in) & 1;\r
    sreg |= d1<<6;\r
  }\r
\r
  Pico.m.sram_reg = (unsigned char) sreg;\r
}\r
\r
\r
#ifndef _ASM_MISC_C\r
typedef struct\r
{\r
	int b0;\r
	int b1;\r
	int b2;\r
	int b3;\r
	int b4;\r
	int b5;\r
	int b6;\r
	int b7;\r
} intblock;\r
\r
PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count)\r
{\r
	if ((((int)dest | (int)src) & 3) == 0)\r
	{\r
		if (count >= 32) {\r
			memcpy32((int *)dest, (int *)src, count/2);\r
			count&=1;\r
		} else {\r
			for (; count >= 2; count -= 2, dest+=2, src+=2)\r
				*(int *)dest = *(int *)src;\r
		}\r
	}\r
	while (count--)\r
		*dest++ = *src++;\r
}\r
\r
\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count)\r
{\r
	unsigned char *src_ = src;\r
\r
	for (; count; count--, src_ += 2)\r
		*dest++ = (src_[0] << 8) | src_[1];\r
}\r
\r
#ifndef _ASM_MISC_C_AMIPS\r
PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count)\r
{\r
	intblock *bd = (intblock *) dest, *bs = (intblock *) src;\r
\r
	for (; count >= sizeof(*bd)/4; count -= sizeof(*bd)/4)\r
		*bd++ = *bs++;\r
\r
	dest = (int *)bd; src = (int *)bs;\r
	while (count--)\r
		*dest++ = *src++;\r
}\r
\r
\r
PICO_INTERNAL_ASM void memset32(int *dest, int c, int count)\r
{\r
	for (; count >= 8; count -= 8, dest += 8)\r
		dest[0] = dest[1] = dest[2] = dest[3] =\r
		dest[4] = dest[5] = dest[6] = dest[7] = c;\r
\r
	while (count--)\r
		*dest++ = c;\r
}\r
void memset32_uncached(int *dest, int c, int count) { memset32(dest, c, count); }\r
#endif\r
#endif\r
\r
Commit	Line	Data
cc68a136	1	// This is part of Pico Library\r
	2	\r
	3	// (c) Copyright 2006 notaz, All rights reserved.\r
	4	// Free for non-commercial use.\r
	5	\r
	6	// For commercial use, separate licencing terms must be obtained.\r
	7	\r
	8	\r
efcba75f	9	#include "pico_int.h"\r
cc68a136	10	\r
	11	// H-counter table for hvcounter reads in 40col mode\r
	12	// based on Gens code\r
	13	const unsigned char hcounts_40[] = {\r
	14	0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,\r
	15	0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x13,0x14,\r
	16	0x14,0x15,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,\r
	17	0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x20,0x20,0x20,0x21,0x21,\r
	18	0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,\r
	19	0x28,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,\r
	20	0x2f,0x30,0x30,0x30,0x31,0x31,0x32,0x32,0x32,0x33,0x33,0x34,0x34,0x35,0x35,0x35,\r
	21	0x36,0x36,0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3c,0x3c,\r
	22	0x3d,0x3d,0x3d,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x41,0x41,0x42,0x42,0x42,0x43,\r
	23	0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x47,0x47,0x47,0x48,0x48,0x49,0x49,0x4a,\r
	24	0x4a,0x4a,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,0x4d,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,\r
	25	0x51,0x51,0x52,0x52,0x52,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x57,0x57,\r
	26	0x57,0x58,0x58,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5e,\r
	27	0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x61,0x61,0x62,0x62,0x62,0x63,0x63,0x64,0x64,0x64,\r
	28	0x65,0x65,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,\r
	29	0x6c,0x6c,0x6c,0x6d,0x6d,0x6e,0x6e,0x6f,0x6f,0x6f,0x70,0x70,0x71,0x71,0x71,0x72,\r
	30	0x72,0x73,0x73,0x74,0x74,0x74,0x75,0x75,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x79,\r
	31	0x79,0x79,0x7a,0x7a,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7e,0x7e,0x7f,0x7f,0x7f,\r
	32	0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x84,0x84,0x84,0x85,0x85,0x86,0x86,\r
	33	0x86,0x87,0x87,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,\r
	34	0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x90,0x90,0x91,0x91,0x91,0x92,0x92,0x93,0x93,0x94,\r
	35	0x94,0x94,0x95,0x95,0x96,0x96,0x96,0x97,0x97,0x98,0x98,0x99,0x99,0x99,0x9a,0x9a,\r
	36	0x9b,0x9b,0x9b,0x9c,0x9c,0x9d,0x9d,0x9e,0x9e,0x9e,0x9f,0x9f,0xa0,0xa0,0xa1,0xa1,\r
	37	0xa1,0xa2,0xa2,0xa3,0xa3,0xa3,0xa4,0xa4,0xa5,0xa5,0xa6,0xa6,0xa6,0xa7,0xa7,0xa8,\r
	38	0xa8,0xa9,0xa9,0xa9,0xaa,0xaa,0xab,0xab,0xab,0xac,0xac,0xad,0xad,0xae,0xae,0xae,\r
	39	0xaf,0xaf,0xb0,0xb0,\r
	40	0xe4,0xe4,0xe4,0xe5,0xe5,0xe6,0xe6,0xe6,0xe7,0xe7,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,\r
	41	0xea,0xeb,0xeb,0xeb,0xec,0xec,0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf1,\r
	42	0xf1,0xf1,0xf2,0xf2,0xf3,0xf3,0xf3,0xf4,0xf4,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,\r
	43	0xf8,0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfd,0xfd,0xfe,0xfe,\r
	44	0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x03,0x04,0x04,0x05,\r
	45	0x05,0x06,0x06,0x06,\r
	46	0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,\r
	47	0x0e,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x10,\r
	48	};\r
	49	\r
	50	// H-counter table for hvcounter reads in 32col mode\r
	51	const unsigned char hcounts_32[] = {\r
	52	0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,\r
	53	0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x0f,0x10,\r
	54	0x10,0x10,0x11,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x13,0x14,0x14,0x14,0x15,0x15,\r
	55	0x15,0x16,0x16,0x17,0x17,0x17,0x18,0x18,0x18,0x19,0x19,0x19,0x1a,0x1a,0x1a,0x1b,\r
	56	0x1b,0x1b,0x1c,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,0x1f,0x1f,0x1f,0x20,0x20,0x20,\r
	57	0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x23,0x24,0x24,0x24,0x25,0x25,0x26,0x26,\r
	58	0x26,0x27,0x27,0x27,0x28,0x28,0x28,0x29,0x29,0x29,0x2a,0x2a,0x2a,0x2b,0x2b,0x2b,\r
	59	0x2c,0x2c,0x2c,0x2d,0x2d,0x2e,0x2e,0x2e,0x2f,0x2f,0x2f,0x30,0x30,0x30,0x31,0x31,\r
	60	0x31,0x32,0x32,0x32,0x33,0x33,0x33,0x34,0x34,0x34,0x35,0x35,0x36,0x36,0x36,0x37,\r
	61	0x37,0x37,0x38,0x38,0x38,0x39,0x39,0x39,0x3a,0x3a,0x3a,0x3b,0x3b,0x3b,0x3c,0x3c,\r
	62	0x3d,0x3d,0x3d,0x3e,0x3e,0x3e,0x3f,0x3f,0x3f,0x40,0x40,0x40,0x41,0x41,0x41,0x42,\r
	63	0x42,0x42,0x43,0x43,0x43,0x44,0x44,0x45,0x45,0x45,0x46,0x46,0x46,0x47,0x47,0x47,\r
	64	0x48,0x48,0x48,0x49,0x49,0x49,0x4a,0x4a,0x4a,0x4b,0x4b,0x4b,0x4c,0x4c,0x4d,0x4d,\r
	65	0x4d,0x4e,0x4e,0x4e,0x4f,0x4f,0x4f,0x50,0x50,0x50,0x51,0x51,0x51,0x52,0x52,0x52,\r
	66	0x53,0x53,0x53,0x54,0x54,0x55,0x55,0x55,0x56,0x56,0x56,0x57,0x57,0x57,0x58,0x58,\r
	67	0x58,0x59,0x59,0x59,0x5a,0x5a,0x5a,0x5b,0x5b,0x5c,0x5c,0x5c,0x5d,0x5d,0x5d,0x5e,\r
	68	0x5e,0x5e,0x5f,0x5f,0x5f,0x60,0x60,0x60,0x61,0x61,0x61,0x62,0x62,0x62,0x63,0x63,\r
	69	0x64,0x64,0x64,0x65,0x65,0x65,0x66,0x66,0x66,0x67,0x67,0x67,0x68,0x68,0x68,0x69,\r
	70	0x69,0x69,0x6a,0x6a,0x6a,0x6b,0x6b,0x6c,0x6c,0x6c,0x6d,0x6d,0x6d,0x6e,0x6e,0x6e,\r
	71	0x6f,0x6f,0x6f,0x70,0x70,0x70,0x71,0x71,0x71,0x72,0x72,0x72,0x73,0x73,0x74,0x74,\r
	72	0x74,0x75,0x75,0x75,0x76,0x76,0x76,0x77,0x77,0x77,0x78,0x78,0x78,0x79,0x79,0x79,\r
	73	0x7a,0x7a,0x7b,0x7b,0x7b,0x7c,0x7c,0x7c,0x7d,0x7d,0x7d,0x7e,0x7e,0x7e,0x7f,0x7f,\r
74	0x7f,0x80,0x80,0x80,0x81,0x81,0x81,0x82,0x82,0x83,0x83,0x83,0x84,0x84,0x84,0x85,\r
75	0x85,0x85,0x86,0x86,0x86,0x87,0x87,0x87,0x88,0x88,0x88,0x89,0x89,0x89,0x8a,0x8a,\r
76	0x8b,0x8b,0x8b,0x8c,0x8c,0x8c,0x8d,0x8d,0x8d,0x8e,0x8e,0x8e,0x8f,0x8f,0x8f,0x90,\r
77	0x90,0x90,0x91,0x91,\r
78	0xe8,0xe8,0xe8,0xe9,0xe9,0xe9,0xea,0xea,0xea,0xeb,0xeb,0xeb,0xec,0xec,0xec,0xed,\r
79	0xed,0xed,0xee,0xee,0xee,0xef,0xef,0xf0,0xf0,0xf0,0xf1,0xf1,0xf1,0xf2,0xf2,0xf2,\r
80	0xf3,0xf3,0xf3,0xf4,0xf4,0xf4,0xf5,0xf5,0xf5,0xf6,0xf6,0xf6,0xf7,0xf7,0xf8,0xf8,\r
81	0xf8,0xf9,0xf9,0xf9,0xfa,0xfa,0xfa,0xfb,0xfb,0xfb,0xfc,0xfc,0xfc,0xfd,0xfd,0xfd,\r
82	0xfe,0xfe,0xfe,0xff,0xff,0x00,0x00,0x00,0x01,0x01,0x01,0x02,0x02,0x02,0x03,0x03,\r
83	0x03,0x04,0x04,0x04,\r
84	0x05,0x05,0x05,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a,0x0a,\r
85	0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,\r
86	};\r
87	\r
cc68a136	88	\r
	89	// rarely used EEPROM SRAM code\r
	90	// known games which use this:\r
	91	// Wonder Boy in Monster World, Megaman - The Wily Wars (X24C01, 128 bytes)\r
cc68a136	92	\r
1dceadae	93	// (see Genesis Plus for Wii/GC code and docs for info,\r
1dceadae	94	// full game list and better code).\r
cc68a136	95	\r
	96	unsigned int lastSSRamWrite = 0xffff0000;\r
	97	\r
1dceadae	98	// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=(unused),\r
cc68a136	99	// d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)\r
eff55556	100	PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
cc68a136	101	{\r
1dceadae	102	unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.eeprom_addr, scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
cc68a136	103	\r
1dceadae	104	elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
1dceadae	105	(d&2)>>1, d&1, SekCyclesDoneT()-lastSSRamWrite);\r
cc68a136	106	saddr&=0x1fff;\r
	107	\r
	108	if(sreg & d & 2) {\r
	109	// SCL was and is still high..\r
	110	if((sreg & 1) && !(d&1)) {\r
	111	// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
1dceadae	112	elprintf(EL_EEPROM, "eeprom: -start-");\r
cc68a136	113	//saddr = 0;\r
	114	scyc = 0;\r
	115	sreg \|= 8;\r
	116	} else if(!(sreg & 1) && (d&1)) {\r
	117	// SDA went high == stop command\r
1dceadae	118	elprintf(EL_EEPROM, "eeprom: -stop-");\r
cc68a136	119	sreg &= ~8;\r
	120	}\r
	121	}\r
1dceadae	122	else if((sreg & 8) && !(sreg & 2) && (d&2))\r
1dceadae	123	{\r
cc68a136	124	// we are started and SCL went high - next cycle\r
cc68a136	125	scyc++; // pre-increment\r
1dceadae	126	if(SRam.eeprom_type) {\r
cc68a136	127	// X24C02+\r
7969166e	128	if((ssa&1) && scyc == 18) {\r
	129	scyc = 9;\r
	130	saddr++; // next address in read mode\r
1dceadae	131	/if(SRam.eeprom_type==2) saddr&=0xff; else/ saddr&=0x1fff; // mask\r
7969166e	132	}\r
1dceadae	133	else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
7969166e	134	else if(scyc == 36) scyc = 27;\r
	135	} else {\r
	136	// X24C01\r
cc68a136	137	if(scyc == 18) {\r
	138	scyc = 9; // wrap\r
	139	if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
7969166e	140	}\r
7969166e	141	}\r
1dceadae	142	elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);\r
cc68a136	143	}\r
1dceadae	144	else if((sreg & 8) && (sreg & 2) && !(d&2))\r
1dceadae	145	{\r
cc68a136	146	// we are started and SCL went low (falling edge)\r
1dceadae	147	if(SRam.eeprom_type) {\r
7969166e	148	// X24C02+\r
7969166e	149	if(scyc == 9 \|\| scyc == 18 \|\| scyc == 27); // ACK cycles\r
1dceadae	150	else if( (SRam.eeprom_type == 3 && scyc > 27) \|\| (SRam.eeprom_type == 2 && scyc > 18) ) {\r
cc68a136	151	if(!(ssa&1)) {\r
	152	// data write\r
	153	unsigned char *pm=SRam.data+saddr;\r
	154	pm <<= 1; pm \|= d&1;\r
	155	if(scyc == 26 \|\| scyc == 35) {\r
	156	saddr=(saddr&~0xf)\|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
1dceadae	157	elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
cc68a136	158	}\r
	159	SRam.changed = 1;\r
	160	}\r
	161	} else if(scyc > 9) {\r
	162	if(!(ssa&1)) {\r
	163	// we latch another addr bit\r
7969166e	164	saddr<<=1;\r
1dceadae	165	if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
7969166e	166	saddr\|=d&1;\r
1dceadae	167	if(scyc==17\|\|scyc==26) {\r
	168	elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
	169	if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr\|=(ssa<<7)&0x700; } // add device bits too\r
	170	}\r
7969166e	171	}\r
cc68a136	172	} else {\r
7969166e	173	// slave address\r
7969166e	174	ssa<<=1; ssa\|=d&1;\r
1dceadae	175	if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);\r
cc68a136	176	}\r
7969166e	177	} else {\r
7969166e	178	// X24C01\r
cc68a136	179	if(scyc == 9); // ACK cycle, do nothing\r
	180	else if(scyc > 9) {\r
	181	if(!(saddr&1)) {\r
	182	// data write\r
	183	unsigned char *pm=SRam.data+(saddr>>1);\r
	184	pm <<= 1; pm \|= d&1;\r
	185	if(scyc == 17) {\r
	186	saddr=(saddr&0xf9)\|((saddr+2)&6); // only 2 lowest bits are incremented\r
1dceadae	187	elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
cc68a136	188	}\r
	189	SRam.changed = 1;\r
	190	}\r
	191	} else {\r
	192	// we latch another addr bit\r
	193	saddr<<=1; saddr\|=d&1; saddr&=0xff;\r
1dceadae	194	if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);\r
cc68a136	195	}\r
7969166e	196	}\r
cc68a136	197	}\r
	198	\r
	199	sreg &= ~3; sreg \|= d&3; // remember SCL and SDA\r
1dceadae	200	Pico.m.sram_reg = (unsigned char) sreg;\r
	201	Pico.m.eeprom_cycle= (unsigned char) scyc;\r
	202	Pico.m.eeprom_slave= (unsigned char) ssa;\r
	203	Pico.m.eeprom_addr = (unsigned short)saddr;\r
cc68a136	204	}\r
cc68a136	205	\r
eff55556	206	PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)\r
cc68a136	207	{\r
1dceadae	208	unsigned int shift, d;\r
1dceadae	209	unsigned int sreg, saddr, scyc, ssa, interval;\r
cc68a136	210	\r
	211	// flush last pending write\r
	212	SRAMWriteEEPROM(Pico.m.sram_reg>>6);\r
	213	\r
1dceadae	214	sreg = Pico.m.sram_reg; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
	215	interval = SekCyclesDoneT()-lastSSRamWrite;\r
	216	d = (sreg>>6)&1; // use SDA as "open bus"\r
cc68a136	217	\r
1dceadae	218	// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
	219	// this is probably valid because data changes occur while SCL is low and data can be read\r
	220	// before it's actual cycle begins.\r
	221	if (!(sreg&0x80) && interval >= 24) {\r
	222	elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);\r
	223	scyc++;\r
	224	}\r
	225	\r
	226	if (!(sreg & 8)); // not started, use open bus\r
	227	else if (scyc == 9 \|\| scyc == 18 \|\| scyc == 27) {\r
	228	elprintf(EL_EEPROM, "eeprom: r ack");\r
	229	d = 0;\r
	230	} else if (scyc > 9 && scyc < 18) {\r
cc68a136	231	// started and first command word received\r
cc68a136	232	shift = 17-scyc;\r
1dceadae	233	if (SRam.eeprom_type) {\r
7969166e	234	// X24C02+\r
1dceadae	235	if (ssa&1) {\r
	236	elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
	237	if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
7969166e	238	d = (SRam.data[saddr]>>shift)&1;\r
	239	}\r
	240	} else {\r
	241	// X24C01\r
1dceadae	242	if (saddr&1) {\r
	243	elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
	244	if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
7969166e	245	d = (SRam.data[saddr>>1]>>shift)&1;\r
	246	}\r
	247	}\r
cc68a136	248	}\r
cc68a136	249	\r
1dceadae	250	return (d << SRam.eeprom_bit_out);\r
cc68a136	251	}\r
cc68a136	252	\r
eff55556	253	PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)\r
cc68a136	254	{\r
1dceadae	255	unsigned int d1, sreg = Pico.m.sram_reg;\r
	256	\r
	257	if (!((SRam.eeprom_abits^a)&1))\r
	258	{\r
	259	// SCL\r
	260	sreg &= ~0x80;\r
	261	d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
	262	sreg \|= d1<<7;\r
	263	}\r
	264	if (!(((SRam.eeprom_abits>>1)^a)&1))\r
	265	{\r
	266	// SDA in\r
	267	sreg &= ~0x40;\r
	268	d1 = (d >> SRam.eeprom_bit_in) & 1;\r
	269	sreg \|= d1<<6;\r
cc68a136	270	}\r
	271	\r
	272	Pico.m.sram_reg = (unsigned char) sreg;\r
	273	}\r
cea65903	274	\r
	275	\r
	276	#ifndef _ASM_MISC_C\r
70357ce5	277	typedef struct\r
	278	{\r
	279	int b0;\r
	280	int b1;\r
	281	int b2;\r
	282	int b3;\r
	283	int b4;\r
	284	int b5;\r
	285	int b6;\r
	286	int b7;\r
	287	} intblock;\r
	288	\r
eff55556	289	PICO_INTERNAL_ASM void memcpy16(unsigned short dest, unsigned short src, int count)\r
cea65903	290	{\r
80db4442	291	if ((((int)dest \| (int)src) & 3) == 0)\r
70357ce5	292	{\r
	293	if (count >= 32) {\r
	294	memcpy32((int )dest, (int )src, count/2);\r
	295	count&=1;\r
	296	} else {\r
	297	for (; count >= 2; count -= 2, dest+=2, src+=2)\r
	298	(int )dest = (int )src;\r
	299	}\r
	300	}\r
cea65903	301	while (count--)\r
	302	dest++ = src++;\r
	303	}\r
	304	\r
	305	\r
eff55556	306	PICO_INTERNAL_ASM void memcpy16bswap(unsigned short dest, void src, int count)\r
0a051f55	307	{\r
	308	unsigned char *src_ = src;\r
	309	\r
	310	for (; count; count--, src_ += 2)\r
	311	*dest++ = (src_[0] << 8) \| src_[1];\r
	312	}\r
	313	\r
b542be46	314	#ifndef _ASM_MISC_C_AMIPS\r
eff55556	315	PICO_INTERNAL_ASM void memcpy32(int dest, int src, int count)\r
cea65903	316	{\r
70357ce5	317	intblock bd = (intblock ) dest, bs = (intblock ) src;\r
	318	\r
	319	for (; count >= sizeof(bd)/4; count -= sizeof(bd)/4)\r
	320	bd++ = bs++;\r
	321	\r
	322	dest = (int )bd; src = (int )bs;\r
cea65903	323	while (count--)\r
	324	dest++ = src++;\r
	325	}\r
	326	\r
	327	\r
eff55556	328	PICO_INTERNAL_ASM void memset32(int *dest, int c, int count)\r
cea65903	329	{\r
70357ce5	330	for (; count >= 8; count -= 8, dest += 8)\r
	331	dest[0] = dest[1] = dest[2] = dest[3] =\r
	332	dest[4] = dest[5] = dest[6] = dest[7] = c;\r
	333	\r
cea65903	334	while (count--)\r
	335	*dest++ = c;\r
	336	}\r
b542be46	337	void memset32_uncached(int *dest, int c, int count) { memset32(dest, c, count); }\r
b542be46	338	#endif\r
cea65903	339	#endif\r
cea65903	340	\r