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platform ps2, handle audio similar to psp
[picodrive.git] / pico / sound / ym2612.h
CommitLineData
cc68a136 1/*\r
2 header file for software emulation for FM sound generator\r
3\r
4*/\r
5#ifndef _H_FM_FM_\r
6#define _H_FM_FM_\r
7\r
8/* compiler dependence */\r
f821bb70 9#include "../pico_types.h"\r
cc68a136 10#ifndef UINT8\r
f821bb70 11typedef u8 UINT8; /* unsigned 8bit */\r
12typedef u16 UINT16; /* unsigned 16bit */\r
13typedef u32 UINT32; /* unsigned 32bit */\r
cc68a136 14#endif\r
15#ifndef INT8\r
f821bb70 16typedef s8 INT8; /* signed 8bit */\r
17typedef s16 INT16; /* signed 16bit */\r
18typedef s32 INT32; /* signed 32bit */\r
cc68a136 19#endif\r
20\r
21#if 1\r
22/* struct describing a single operator (SLOT) */\r
23typedef struct\r
24{\r
25 INT32 *DT; /* #0x00 detune :dt_tab[DT] */\r
d2721b08 26 UINT8 ar; /* #0x04 attack rate */\r
cc68a136 27 UINT8 d1r; /* #0x05 decay rate */\r
28 UINT8 d2r; /* #0x06 sustain rate */\r
d2721b08 29 UINT8 rr; /* #0x07 release rate */\r
cc68a136 30 UINT32 mul; /* #0x08 multiple :ML_TABLE[ML] */\r
31\r
32 /* Phase Generator */\r
d2721b08 33 UINT32 phase; /* #0x0c phase counter | need_save */\r
db49317b 34 UINT32 Incr; /* #0x10 phase step */\r
cc68a136 35\r
36 UINT8 KSR; /* #0x14 key scale rate :3-KSR */\r
37 UINT8 ksr; /* #0x15 key scale rate :kcode>>(3-KSR) */\r
38\r
39 UINT8 key; /* #0x16 0=last key was KEY OFF, 1=KEY ON */\r
40\r
41 /* Envelope Generator */\r
d2721b08 42 UINT8 state; /* #0x17 phase type: EG_OFF=0, EG_REL, EG_SUS, EG_DEC, EG_ATT | need_save */\r
43 UINT16 tl; /* #0x18 total level: TL << 3 */\r
44 INT16 volume; /* #0x1a envelope counter | need_save */\r
45 UINT32 sl; /* #0x1c sustain level:sl_table[SL] */\r
cc68a136 46\r
6d28fb50 47 /* asm relies on this order: */\r
48 union {\r
49 struct {\r
50 UINT32 eg_pack_rr; /* #0x20 1 (release state) */\r
51 UINT32 eg_pack_d2r; /* #0x24 2 (sustain state) */\r
52 UINT32 eg_pack_d1r; /* #0x28 3 (decay state) */\r
53 UINT32 eg_pack_ar; /* #0x2c 4 (attack state) */\r
54 };\r
55 UINT32 eg_pack[4];\r
56 };\r
8ac9ab7f 57\r
58 UINT8 ssg; /* 0x30 SSG-EG waveform */\r
59 UINT8 ssgn;\r
b9bc876c 60 UINT16 ar_ksr; /* 0x32 ar+ksr */\r
61 UINT16 vol_out; /* 0x34 current output from EG (without LFO) */\r
d127b3f3 62 UINT16 pad;\r
cc68a136 63} FM_SLOT;\r
64\r
65\r
66typedef struct\r
67{\r
68 FM_SLOT SLOT[4]; /* four SLOTs (operators) */\r
69\r
db49317b 70 UINT8 ALGO; /* +00 algorithm */\r
d2721b08 71 UINT8 FB; /* feedback shift */\r
eaa9417a 72 UINT8 pad[2];\r
cc68a136 73 INT32 op1_out; /* op1 output for feedback */\r
74\r
db49317b 75 INT32 mem_value; /* +08 delayed sample (MEM) value */\r
cc68a136 76\r
77 INT32 pms; /* channel PMS */\r
78 UINT8 ams; /* channel AMS */\r
79\r
db49317b 80 UINT8 kcode; /* +11 key code: */\r
68e06234 81 UINT8 pad2;\r
d127b3f3 82 UINT8 upd_cnt; /* eg update counter */\r
d2721b08 83 UINT32 fc; /* fnum,blk:adjusted to sample rate */\r
cc68a136 84 UINT32 block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */\r
85\r
86 /* LFO */\r
87 UINT8 AMmasks; /* AM enable flag */\r
eaa9417a 88 UINT8 pad3[3];\r
cc68a136 89} FM_CH;\r
90\r
91typedef struct\r
92{\r
93 int clock; /* master clock (Hz) */\r
94 int rate; /* sampling rate (Hz) */\r
b542be46 95 double freqbase; /* 08 frequency base */\r
d2721b08 96 UINT8 address; /* 10 address register | need_save */\r
97 UINT8 status; /* 11 status flag | need_save */\r
cc68a136 98 UINT8 mode; /* mode CSM / 3SLOT */\r
324bd685 99 UINT8 flags; /* operational flags */\r
cc68a136 100 int TA; /* timer a */\r
101 int TAC; /* timer a maxval */\r
d2721b08 102 int TAT; /* timer a ticker | need_save */\r
cc68a136 103 UINT8 TB; /* timer b */\r
68e06234 104 UINT8 fn_h; /* freq latch */\r
105 UINT8 pad2[2];\r
cc68a136 106 int TBC; /* timer b maxval */\r
d2721b08 107 int TBT; /* timer b ticker | need_save */\r
cc68a136 108 /* local time tables */\r
109 INT32 dt_tab[8][32];/* DeTune table */\r
110} FM_ST;\r
111\r
8794ba5c 112#define ST_SSG 1\r
23cd73bc 113#define ST_DAC 2\r
8794ba5c 114\r
cc68a136 115/***********************************************************/\r
116/* OPN unit */\r
117/***********************************************************/\r
118\r
119/* OPN 3slot struct */\r
120typedef struct\r
121{\r
122 UINT32 fc[3]; /* fnum3,blk3: calculated */\r
123 UINT8 fn_h; /* freq3 latch */\r
124 UINT8 kcode[3]; /* key code */\r
125 UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */\r
126} FM_3SLOT;\r
127\r
128/* OPN/A/B common state */\r
129typedef struct\r
130{\r
131 FM_ST ST; /* general state */\r
132 FM_3SLOT SL3; /* 3 slot mode state */\r
133 UINT32 pan; /* fm channels output mask (bit 1 = enable) */\r
134\r
eaa9417a 135 UINT32 eg_cnt; /* global envelope generator counter | need_save */\r
136 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 | need_save */\r
137 UINT32 eg_timer_add; /* step of eg_timer */\r
cc68a136 138\r
139 /* LFO */\r
d2721b08 140 UINT32 lfo_cnt; /* need_save */\r
cc68a136 141 UINT32 lfo_inc;\r
142\r
143 UINT32 lfo_freq[8]; /* LFO FREQ table */\r
144} FM_OPN;\r
145\r
146/* here's the virtual YM2612 */\r
147typedef struct\r
148{\r
d2721b08 149 UINT8 REGS[0x200]; /* registers (for save states) */\r
150 INT32 addr_A1; /* address line A1 | need_save */\r
cc68a136 151\r
eaa9417a 152 FM_CH CH[6]; /* channel state */\r
cc68a136 153\r
154 /* dac output (YM2612) */\r
d2721b08 155 int dacen;\r
cc68a136 156 INT32 dacout;\r
157\r
158 FM_OPN OPN; /* OPN state */\r
b542be46 159\r
160 UINT32 slot_mask; /* active slot mask (performance hack) */\r
1dbda5f8 161 UINT32 ssg_mask; /* active ssg mask (performance hack) */\r
cc68a136 162} YM2612;\r
163#endif\r
164\r
4b9c5888 165#ifndef EXTERNAL_YM2612\r
166extern YM2612 ym2612;\r
167#endif\r
b542be46 168\r
8794ba5c 169void YM2612Init_(int baseclock, int rate, int flags);\r
cc68a136 170void YM2612ResetChip_(void);\r
f7741cac 171int YM2612UpdateOne_(s32 *buffer, int length, int stereo, int is_buf_empty);\r
cc68a136 172\r
173int YM2612Write_(unsigned int a, unsigned int v);\r
43e6eaad 174//unsigned char YM2612Read_(void);\r
cc68a136 175\r
176int YM2612PicoTick_(int n);\r
177void YM2612PicoStateLoad_(void);\r
178\r
179void *YM2612GetRegs(void);\r
f5c022a8 180void YM2612PicoStateSave2(int tat, int tbt, int busy);\r
181int YM2612PicoStateLoad2(int *tat, int *tbt, int *busy);\r
cc68a136 182\r
3167aa9a 183/* NB must be macros for compiling GP2X 940 code */\r
cc68a136 184#ifndef __GP2X__\r
185#define YM2612Init YM2612Init_\r
186#define YM2612ResetChip YM2612ResetChip_\r
187#define YM2612UpdateOne YM2612UpdateOne_\r
cc68a136 188#define YM2612PicoStateLoad YM2612PicoStateLoad_\r
189#else\r
190/* GP2X specific */\r
f821bb70 191#include <platform/gp2x/940ctl.h>\r
3167aa9a 192#define YM2612Init(baseclock, rate, flags) \\r
193 (PicoIn.opt & POPT_EXT_FM ? YM2612Init_940 : YM2612Init_)(baseclock, rate, flags)\r
194#define YM2612ResetChip() \\r
195 (PicoIn.opt & POPT_EXT_FM ? YM2612ResetChip_940 : YM2612ResetChip_)()\r
196#define YM2612PicoStateLoad() \\r
197 (PicoIn.opt & POPT_EXT_FM ? YM2612PicoStateLoad_940 : YM2612PicoStateLoad_)()\r
198#define YM2612UpdateOne(buffer, length, sterao, isempty) \\r
199 (PicoIn.opt & POPT_EXT_FM ? YM2612UpdateOne_940 : YM2612UpdateOne_)(buffer, length, stereo, isempty)\r
cc68a136 200#endif /* __GP2X__ */\r
201\r
202\r
203#endif /* _H_FM_FM_ */\r
fast MegaDrive/MegaCD/32X emulator